1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
2 /*
3  * This file is provided under a dual BSD/GPLv2 license. When using or
4  * redistributing this file, you may do so under either license.
5  *
6  * Copyright(c) 2021 Advanced Micro Devices, Inc. All rights reserved.
7  *
8  * Author: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com>
9  */
10 
11 #ifndef __AMD_ACP_H
12 #define __AMD_ACP_H
13 
14 #include <sound/pcm.h>
15 #include <sound/soc.h>
16 #include <sound/soc-acpi.h>
17 #include <sound/soc-dai.h>
18 
19 #include "chip_offset_byte.h"
20 
21 #define ACP3X_DEV			3
22 #define ACP6X_DEV			6
23 
24 #define DMIC_INSTANCE			0x00
25 #define I2S_SP_INSTANCE			0x01
26 #define I2S_BT_INSTANCE			0x02
27 #define I2S_HS_INSTANCE			0x03
28 
29 #define MEM_WINDOW_START		0x4080000
30 
31 #define ACP_I2S_REG_START		0x1242400
32 #define ACP_I2S_REG_END			0x1242810
33 #define ACP3x_I2STDM_REG_START		0x1242400
34 #define ACP3x_I2STDM_REG_END		0x1242410
35 #define ACP3x_BT_TDM_REG_START		0x1242800
36 #define ACP3x_BT_TDM_REG_END		0x1242810
37 
38 #define THRESHOLD(bit, base)	((bit) + (base))
39 #define I2S_RX_THRESHOLD(base)	THRESHOLD(7, base)
40 #define I2S_TX_THRESHOLD(base)	THRESHOLD(8, base)
41 #define BT_TX_THRESHOLD(base)	THRESHOLD(6, base)
42 #define BT_RX_THRESHOLD(base)	THRESHOLD(5, base)
43 #define HS_TX_THRESHOLD(base)	THRESHOLD(4, base)
44 #define HS_RX_THRESHOLD(base)	THRESHOLD(3, base)
45 
46 #define ACP_SRAM_SP_PB_PTE_OFFSET	0x0
47 #define ACP_SRAM_SP_CP_PTE_OFFSET	0x100
48 #define ACP_SRAM_BT_PB_PTE_OFFSET	0x200
49 #define ACP_SRAM_BT_CP_PTE_OFFSET	0x300
50 #define ACP_SRAM_PDM_PTE_OFFSET		0x400
51 #define ACP_SRAM_HS_PB_PTE_OFFSET       0x500
52 #define ACP_SRAM_HS_CP_PTE_OFFSET       0x600
53 #define PAGE_SIZE_4K_ENABLE		0x2
54 
55 #define I2S_SP_TX_MEM_WINDOW_START	0x4000000
56 #define I2S_SP_RX_MEM_WINDOW_START	0x4020000
57 #define I2S_BT_TX_MEM_WINDOW_START	0x4040000
58 #define I2S_BT_RX_MEM_WINDOW_START	0x4060000
59 #define I2S_HS_TX_MEM_WINDOW_START      0x40A0000
60 #define I2S_HS_RX_MEM_WINDOW_START      0x40C0000
61 
62 #define SP_PB_FIFO_ADDR_OFFSET		0x500
63 #define SP_CAPT_FIFO_ADDR_OFFSET	0x700
64 #define BT_PB_FIFO_ADDR_OFFSET		0x900
65 #define BT_CAPT_FIFO_ADDR_OFFSET	0xB00
66 #define HS_PB_FIFO_ADDR_OFFSET		0xD00
67 #define HS_CAPT_FIFO_ADDR_OFFSET	0xF00
68 #define PLAYBACK_MIN_NUM_PERIODS	2
69 #define PLAYBACK_MAX_NUM_PERIODS	8
70 #define PLAYBACK_MAX_PERIOD_SIZE	8192
71 #define PLAYBACK_MIN_PERIOD_SIZE	1024
72 #define CAPTURE_MIN_NUM_PERIODS		2
73 #define CAPTURE_MAX_NUM_PERIODS		8
74 #define CAPTURE_MAX_PERIOD_SIZE		8192
75 #define CAPTURE_MIN_PERIOD_SIZE		1024
76 
77 #define MAX_BUFFER			65536
78 #define MIN_BUFFER			MAX_BUFFER
79 #define FIFO_SIZE			0x100
80 #define DMA_SIZE			0x40
81 #define FRM_LEN				0x100
82 
83 #define ACP3x_ITER_IRER_SAMP_LEN_MASK	0x38
84 
85 #define ACP_MAX_STREAM			8
86 
87 #define TDM_ENABLE	1
88 #define TDM_DISABLE	0
89 
90 #define SLOT_WIDTH_8	0x8
91 #define SLOT_WIDTH_16	0x10
92 #define SLOT_WIDTH_24	0x18
93 #define SLOT_WIDTH_32	0x20
94 
95 struct acp_chip_info {
96 	char *name;		/* Platform name */
97 	unsigned int acp_rev;	/* ACP Revision id */
98 	void __iomem *base;	/* ACP memory PCI base */
99 };
100 
101 struct acp_stream {
102 	struct list_head list;
103 	struct snd_pcm_substream *substream;
104 	int irq_bit;
105 	int dai_id;
106 	int id;
107 	int dir;
108 	u64 bytescount;
109 	u32 reg_offset;
110 	u32 pte_offset;
111 	u32 fifo_offset;
112 };
113 
114 struct acp_resource {
115 	int offset;
116 	int no_of_ctrls;
117 	int irqp_used;
118 	bool soc_mclk;
119 	u32 irq_reg_offset;
120 	u32 i2s_pin_cfg_offset;
121 	int i2s_mode;
122 	u64 scratch_reg_offset;
123 	u64 sram_pte_offset;
124 };
125 
126 struct acp_dev_data {
127 	char *name;
128 	struct device *dev;
129 	void __iomem *acp_base;
130 	unsigned int i2s_irq;
131 
132 	bool tdm_mode;
133 	/* SOC specific dais */
134 	struct snd_soc_dai_driver *dai_driver;
135 	int num_dai;
136 
137 	struct list_head stream_list;
138 	spinlock_t acp_lock;
139 
140 	struct snd_soc_acpi_mach *machines;
141 	struct platform_device *mach_dev;
142 
143 	u32 bclk_div;
144 	u32 lrclk_div;
145 
146 	struct acp_resource *rsrc;
147 	u32 tdm_tx_fmt[3];
148 	u32 tdm_rx_fmt[3];
149 };
150 
151 union acp_i2stdm_mstrclkgen {
152 	struct {
153 		u32 i2stdm_master_mode : 1;
154 		u32 i2stdm_format_mode : 1;
155 		u32 i2stdm_lrclk_div_val : 9;
156 		u32 i2stdm_bclk_div_val : 11;
157 		u32:10;
158 	} bitfields, bits;
159 	u32  u32_all;
160 };
161 
162 extern const struct snd_soc_dai_ops asoc_acp_cpu_dai_ops;
163 extern const struct snd_soc_dai_ops acp_dmic_dai_ops;
164 
165 int asoc_acp_i2s_probe(struct snd_soc_dai *dai);
166 int acp_platform_register(struct device *dev);
167 int acp_platform_unregister(struct device *dev);
168 
169 int acp_machine_select(struct acp_dev_data *adata);
170 
171 /* Machine configuration */
172 int snd_amd_acp_find_config(struct pci_dev *pci);
173 
acp_get_byte_count(struct acp_dev_data * adata,int dai_id,int direction)174 static inline u64 acp_get_byte_count(struct acp_dev_data *adata, int dai_id, int direction)
175 {
176 	u64 byte_count, low = 0, high = 0;
177 
178 	if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
179 		switch (dai_id) {
180 		case I2S_BT_INSTANCE:
181 			high = readl(adata->acp_base + ACP_BT_TX_LINEARPOSITIONCNTR_HIGH);
182 			low = readl(adata->acp_base + ACP_BT_TX_LINEARPOSITIONCNTR_LOW);
183 			break;
184 		case I2S_SP_INSTANCE:
185 			high = readl(adata->acp_base + ACP_I2S_TX_LINEARPOSITIONCNTR_HIGH);
186 			low = readl(adata->acp_base + ACP_I2S_TX_LINEARPOSITIONCNTR_LOW);
187 			break;
188 		case I2S_HS_INSTANCE:
189 			high = readl(adata->acp_base + ACP_HS_TX_LINEARPOSITIONCNTR_HIGH);
190 			low = readl(adata->acp_base + ACP_HS_TX_LINEARPOSITIONCNTR_LOW);
191 			break;
192 		default:
193 			dev_err(adata->dev, "Invalid dai id %x\n", dai_id);
194 			return -EINVAL;
195 		}
196 	} else {
197 		switch (dai_id) {
198 		case I2S_BT_INSTANCE:
199 			high = readl(adata->acp_base + ACP_BT_RX_LINEARPOSITIONCNTR_HIGH);
200 			low = readl(adata->acp_base + ACP_BT_RX_LINEARPOSITIONCNTR_LOW);
201 			break;
202 		case I2S_SP_INSTANCE:
203 			high = readl(adata->acp_base + ACP_I2S_RX_LINEARPOSITIONCNTR_HIGH);
204 			low = readl(adata->acp_base + ACP_I2S_RX_LINEARPOSITIONCNTR_LOW);
205 			break;
206 		case I2S_HS_INSTANCE:
207 			high = readl(adata->acp_base + ACP_HS_RX_LINEARPOSITIONCNTR_HIGH);
208 			low = readl(adata->acp_base + ACP_HS_RX_LINEARPOSITIONCNTR_LOW);
209 			break;
210 		case DMIC_INSTANCE:
211 			high = readl(adata->acp_base + ACP_WOV_RX_LINEARPOSITIONCNTR_HIGH);
212 			low = readl(adata->acp_base + ACP_WOV_RX_LINEARPOSITIONCNTR_LOW);
213 			break;
214 		default:
215 			dev_err(adata->dev, "Invalid dai id %x\n", dai_id);
216 			return -EINVAL;
217 		}
218 	}
219 	/* Get 64 bit value from two 32 bit registers */
220 	byte_count = (high << 32) | low;
221 
222 	return byte_count;
223 }
224 
acp_set_i2s_clk(struct acp_dev_data * adata,int dai_id)225 static inline void acp_set_i2s_clk(struct acp_dev_data *adata, int dai_id)
226 {
227 	union acp_i2stdm_mstrclkgen mclkgen;
228 	u32 master_reg;
229 
230 	switch (dai_id) {
231 	case I2S_SP_INSTANCE:
232 		master_reg = ACP_I2STDM0_MSTRCLKGEN;
233 		break;
234 	case I2S_BT_INSTANCE:
235 		master_reg = ACP_I2STDM1_MSTRCLKGEN;
236 		break;
237 	case I2S_HS_INSTANCE:
238 		master_reg = ACP_I2STDM2_MSTRCLKGEN;
239 		break;
240 	default:
241 		master_reg = ACP_I2STDM0_MSTRCLKGEN;
242 		break;
243 	}
244 
245 	mclkgen.bits.i2stdm_master_mode = 0x1;
246 	mclkgen.bits.i2stdm_format_mode = 0x00;
247 
248 	mclkgen.bits.i2stdm_bclk_div_val = adata->bclk_div;
249 	mclkgen.bits.i2stdm_lrclk_div_val = adata->lrclk_div;
250 	writel(mclkgen.u32_all, adata->acp_base + master_reg);
251 }
252 #endif
253