1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // Driver for Microchip Pulse Density Microphone Controller (PDMC) interfaces
4 //
5 // Copyright (C) 2019-2022 Microchip Technology Inc. and its subsidiaries
6 //
7 // Author: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
8
9 #include <dt-bindings/sound/microchip,pdmc.h>
10
11 #include <linux/clk.h>
12 #include <linux/module.h>
13 #include <linux/of.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/regmap.h>
16
17 #include <sound/core.h>
18 #include <sound/dmaengine_pcm.h>
19 #include <sound/pcm_params.h>
20 #include <sound/tlv.h>
21
22 /*
23 * ---- PDMC Register map ----
24 */
25 #define MCHP_PDMC_CR 0x00 /* Control Register */
26 #define MCHP_PDMC_MR 0x04 /* Mode Register */
27 #define MCHP_PDMC_CFGR 0x08 /* Configuration Register */
28 #define MCHP_PDMC_RHR 0x0C /* Receive Holding Register */
29 #define MCHP_PDMC_IER 0x14 /* Interrupt Enable Register */
30 #define MCHP_PDMC_IDR 0x18 /* Interrupt Disable Register */
31 #define MCHP_PDMC_IMR 0x1C /* Interrupt Mask Register */
32 #define MCHP_PDMC_ISR 0x20 /* Interrupt Status Register */
33 #define MCHP_PDMC_VER 0x50 /* Version Register */
34
35 /*
36 * ---- Control Register (Write-only) ----
37 */
38 #define MCHP_PDMC_CR_SWRST BIT(0) /* Software Reset */
39
40 /*
41 * ---- Mode Register (Read/Write) ----
42 */
43 #define MCHP_PDMC_MR_PDMCEN_MASK GENMASK(3, 0)
44 #define MCHP_PDMC_MR_PDMCEN(ch) (BIT(ch) & MCHP_PDMC_MR_PDMCEN_MASK)
45
46 #define MCHP_PDMC_MR_OSR_MASK GENMASK(17, 16)
47 #define MCHP_PDMC_MR_OSR64 (1 << 16)
48 #define MCHP_PDMC_MR_OSR128 (2 << 16)
49 #define MCHP_PDMC_MR_OSR256 (3 << 16)
50
51 #define MCHP_PDMC_MR_SINCORDER_MASK GENMASK(23, 20)
52 #define MCHP_PDMC_MR_SINCORDER(order) (((order) << 20) & \
53 MCHP_PDMC_MR_SINCORDER_MASK)
54
55 #define MCHP_PDMC_MR_SINC_OSR_MASK GENMASK(27, 24)
56 #define MCHP_PDMC_MR_SINC_OSR_DIS (0 << 24)
57 #define MCHP_PDMC_MR_SINC_OSR_8 (1 << 24)
58 #define MCHP_PDMC_MR_SINC_OSR_16 (2 << 24)
59 #define MCHP_PDMC_MR_SINC_OSR_32 (3 << 24)
60 #define MCHP_PDMC_MR_SINC_OSR_64 (4 << 24)
61 #define MCHP_PDMC_MR_SINC_OSR_128 (5 << 24)
62 #define MCHP_PDMC_MR_SINC_OSR_256 (6 << 24)
63
64 #define MCHP_PDMC_MR_CHUNK_MASK GENMASK(31, 28)
65 #define MCHP_PDMC_MR_CHUNK(chunk) (((chunk) << 28) & \
66 MCHP_PDMC_MR_CHUNK_MASK)
67
68 /*
69 * ---- Configuration Register (Read/Write) ----
70 */
71 #define MCHP_PDMC_CFGR_BSSEL_MASK (BIT(0) | BIT(2) | BIT(4) | BIT(6))
72 #define MCHP_PDMC_CFGR_BSSEL(ch) BIT((ch) * 2)
73
74 #define MCHP_PDMC_CFGR_PDMSEL_MASK (BIT(16) | BIT(18) | BIT(20) | BIT(22))
75 #define MCHP_PDMC_CFGR_PDMSEL(ch) BIT((ch) * 2 + 16)
76
77 /*
78 * ---- Interrupt Enable/Disable/Mask/Status Registers ----
79 */
80 #define MCHP_PDMC_IR_RXRDY BIT(0)
81 #define MCHP_PDMC_IR_RXEMPTY BIT(1)
82 #define MCHP_PDMC_IR_RXFULL BIT(2)
83 #define MCHP_PDMC_IR_RXCHUNK BIT(3)
84 #define MCHP_PDMC_IR_RXUDR BIT(4)
85 #define MCHP_PDMC_IR_RXOVR BIT(5)
86
87 /*
88 * ---- Version Register (Read-only) ----
89 */
90 #define MCHP_PDMC_VER_VERSION GENMASK(11, 0)
91
92 #define MCHP_PDMC_MAX_CHANNELS 4
93 #define MCHP_PDMC_DS_NO 2
94 #define MCHP_PDMC_EDGE_NO 2
95
96 struct mic_map {
97 int ds_pos;
98 int clk_edge;
99 };
100
101 struct mchp_pdmc_chmap {
102 struct snd_pcm_chmap_elem *chmap;
103 struct mchp_pdmc *dd;
104 struct snd_pcm *pcm;
105 struct snd_kcontrol *kctl;
106 };
107
108 struct mchp_pdmc {
109 struct mic_map channel_mic_map[MCHP_PDMC_MAX_CHANNELS];
110 struct device *dev;
111 struct snd_dmaengine_dai_dma_data addr;
112 struct regmap *regmap;
113 struct clk *pclk;
114 struct clk *gclk;
115 u32 pdmcen;
116 u32 suspend_irq;
117 u32 startup_delay_us;
118 int mic_no;
119 int sinc_order;
120 bool audio_filter_en;
121 };
122
123 static const char *const mchp_pdmc_sinc_filter_order_text[] = {
124 "1", "2", "3", "4", "5"
125 };
126
127 static const unsigned int mchp_pdmc_sinc_filter_order_values[] = {
128 1, 2, 3, 4, 5,
129 };
130
131 static const struct soc_enum mchp_pdmc_sinc_filter_order_enum = {
132 .items = ARRAY_SIZE(mchp_pdmc_sinc_filter_order_text),
133 .texts = mchp_pdmc_sinc_filter_order_text,
134 .values = mchp_pdmc_sinc_filter_order_values,
135 };
136
mchp_pdmc_sinc_order_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * uvalue)137 static int mchp_pdmc_sinc_order_get(struct snd_kcontrol *kcontrol,
138 struct snd_ctl_elem_value *uvalue)
139 {
140 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
141 struct mchp_pdmc *dd = snd_soc_component_get_drvdata(component);
142 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
143 unsigned int item;
144
145 item = snd_soc_enum_val_to_item(e, dd->sinc_order);
146 uvalue->value.enumerated.item[0] = item;
147
148 return 0;
149 }
150
mchp_pdmc_sinc_order_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * uvalue)151 static int mchp_pdmc_sinc_order_put(struct snd_kcontrol *kcontrol,
152 struct snd_ctl_elem_value *uvalue)
153 {
154 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
155 struct mchp_pdmc *dd = snd_soc_component_get_drvdata(component);
156 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
157 unsigned int *item = uvalue->value.enumerated.item;
158 unsigned int val;
159
160 if (item[0] >= e->items)
161 return -EINVAL;
162
163 val = snd_soc_enum_item_to_val(e, item[0]) << e->shift_l;
164 if (val == dd->sinc_order)
165 return 0;
166
167 dd->sinc_order = val;
168
169 return 1;
170 }
171
mchp_pdmc_af_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * uvalue)172 static int mchp_pdmc_af_get(struct snd_kcontrol *kcontrol,
173 struct snd_ctl_elem_value *uvalue)
174 {
175 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
176 struct mchp_pdmc *dd = snd_soc_component_get_drvdata(component);
177
178 uvalue->value.integer.value[0] = !!dd->audio_filter_en;
179
180 return 0;
181 }
182
mchp_pdmc_af_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * uvalue)183 static int mchp_pdmc_af_put(struct snd_kcontrol *kcontrol,
184 struct snd_ctl_elem_value *uvalue)
185 {
186 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
187 struct mchp_pdmc *dd = snd_soc_component_get_drvdata(component);
188 bool af = uvalue->value.integer.value[0] ? true : false;
189
190 if (dd->audio_filter_en == af)
191 return 0;
192
193 dd->audio_filter_en = af;
194
195 return 1;
196 }
197
mchp_pdmc_chmap_ctl_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)198 static int mchp_pdmc_chmap_ctl_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
199 {
200 struct mchp_pdmc_chmap *info = snd_kcontrol_chip(kcontrol);
201
202 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
203 uinfo->count = info->dd->mic_no;
204 uinfo->value.integer.min = 0;
205 uinfo->value.integer.max = SNDRV_CHMAP_RR; /* maxmimum 4 channels */
206 return 0;
207 }
208
209 static inline struct snd_pcm_substream *
mchp_pdmc_chmap_substream(struct mchp_pdmc_chmap * info,unsigned int idx)210 mchp_pdmc_chmap_substream(struct mchp_pdmc_chmap *info, unsigned int idx)
211 {
212 struct snd_pcm_substream *s;
213
214 for (s = info->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream; s; s = s->next)
215 if (s->number == idx)
216 return s;
217 return NULL;
218 }
219
mchp_pdmc_chmap_get(struct snd_pcm_substream * substream,struct mchp_pdmc_chmap * ch_info)220 static struct snd_pcm_chmap_elem *mchp_pdmc_chmap_get(struct snd_pcm_substream *substream,
221 struct mchp_pdmc_chmap *ch_info)
222 {
223 struct snd_pcm_chmap_elem *map;
224
225 for (map = ch_info->chmap; map->channels; map++) {
226 if (map->channels == substream->runtime->channels)
227 return map;
228 }
229 return NULL;
230 }
231
mchp_pdmc_chmap_ctl_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)232 static int mchp_pdmc_chmap_ctl_get(struct snd_kcontrol *kcontrol,
233 struct snd_ctl_elem_value *ucontrol)
234 {
235 struct mchp_pdmc_chmap *info = snd_kcontrol_chip(kcontrol);
236 struct mchp_pdmc *dd = info->dd;
237 unsigned int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
238 struct snd_pcm_substream *substream;
239 const struct snd_pcm_chmap_elem *map;
240 int i;
241 u32 cfgr_val = 0;
242
243 if (!info->chmap)
244 return -EINVAL;
245 substream = mchp_pdmc_chmap_substream(info, idx);
246 if (!substream)
247 return -ENODEV;
248 memset(ucontrol->value.integer.value, 0, sizeof(long) * info->dd->mic_no);
249 if (!substream->runtime)
250 return 0; /* no channels set */
251
252 map = mchp_pdmc_chmap_get(substream, info);
253 if (!map)
254 return -EINVAL;
255
256 for (i = 0; i < map->channels; i++) {
257 int map_idx = map->channels == 1 ? map->map[i] - SNDRV_CHMAP_MONO :
258 map->map[i] - SNDRV_CHMAP_FL;
259
260 /* make sure the reported channel map is the real one, so write the map */
261 if (dd->channel_mic_map[map_idx].ds_pos)
262 cfgr_val |= MCHP_PDMC_CFGR_PDMSEL(i);
263 if (dd->channel_mic_map[map_idx].clk_edge)
264 cfgr_val |= MCHP_PDMC_CFGR_BSSEL(i);
265
266 ucontrol->value.integer.value[i] = map->map[i];
267 }
268
269 regmap_write(dd->regmap, MCHP_PDMC_CFGR, cfgr_val);
270
271 return 0;
272 }
273
mchp_pdmc_chmap_ctl_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)274 static int mchp_pdmc_chmap_ctl_put(struct snd_kcontrol *kcontrol,
275 struct snd_ctl_elem_value *ucontrol)
276 {
277 struct mchp_pdmc_chmap *info = snd_kcontrol_chip(kcontrol);
278 struct mchp_pdmc *dd = info->dd;
279 unsigned int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
280 struct snd_pcm_substream *substream;
281 struct snd_pcm_chmap_elem *map;
282 u32 cfgr_val = 0;
283 int i;
284
285 if (!info->chmap)
286 return -EINVAL;
287 substream = mchp_pdmc_chmap_substream(info, idx);
288 if (!substream)
289 return -ENODEV;
290
291 map = mchp_pdmc_chmap_get(substream, info);
292 if (!map)
293 return -EINVAL;
294
295 for (i = 0; i < map->channels; i++) {
296 int map_idx;
297
298 map->map[i] = ucontrol->value.integer.value[i];
299 map_idx = map->channels == 1 ? map->map[i] - SNDRV_CHMAP_MONO :
300 map->map[i] - SNDRV_CHMAP_FL;
301
302 /* configure IP for the desired channel map */
303 if (dd->channel_mic_map[map_idx].ds_pos)
304 cfgr_val |= MCHP_PDMC_CFGR_PDMSEL(i);
305 if (dd->channel_mic_map[map_idx].clk_edge)
306 cfgr_val |= MCHP_PDMC_CFGR_BSSEL(i);
307 }
308
309 regmap_write(dd->regmap, MCHP_PDMC_CFGR, cfgr_val);
310
311 return 0;
312 }
313
mchp_pdmc_chmap_ctl_private_free(struct snd_kcontrol * kcontrol)314 static void mchp_pdmc_chmap_ctl_private_free(struct snd_kcontrol *kcontrol)
315 {
316 struct mchp_pdmc_chmap *info = snd_kcontrol_chip(kcontrol);
317
318 info->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].chmap_kctl = NULL;
319 kfree(info);
320 }
321
mchp_pdmc_chmap_ctl_tlv(struct snd_kcontrol * kcontrol,int op_flag,unsigned int size,unsigned int __user * tlv)322 static int mchp_pdmc_chmap_ctl_tlv(struct snd_kcontrol *kcontrol, int op_flag,
323 unsigned int size, unsigned int __user *tlv)
324 {
325 struct mchp_pdmc_chmap *info = snd_kcontrol_chip(kcontrol);
326 const struct snd_pcm_chmap_elem *map;
327 unsigned int __user *dst;
328 int c, count = 0;
329
330 if (!info->chmap)
331 return -EINVAL;
332 if (size < 8)
333 return -ENOMEM;
334 if (put_user(SNDRV_CTL_TLVT_CONTAINER, tlv))
335 return -EFAULT;
336 size -= 8;
337 dst = tlv + 2;
338 for (map = info->chmap; map->channels; map++) {
339 int chs_bytes = map->channels * 4;
340
341 if (size < 8)
342 return -ENOMEM;
343 if (put_user(SNDRV_CTL_TLVT_CHMAP_VAR, dst) ||
344 put_user(chs_bytes, dst + 1))
345 return -EFAULT;
346 dst += 2;
347 size -= 8;
348 count += 8;
349 if (size < chs_bytes)
350 return -ENOMEM;
351 size -= chs_bytes;
352 count += chs_bytes;
353 for (c = 0; c < map->channels; c++) {
354 if (put_user(map->map[c], dst))
355 return -EFAULT;
356 dst++;
357 }
358 }
359 if (put_user(count, tlv + 1))
360 return -EFAULT;
361 return 0;
362 }
363
364 static const struct snd_kcontrol_new mchp_pdmc_snd_controls[] = {
365 SOC_SINGLE_BOOL_EXT("Audio Filter", 0, &mchp_pdmc_af_get, &mchp_pdmc_af_put),
366 {
367 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
368 .name = "SINC Filter Order",
369 .info = snd_soc_info_enum_double,
370 .get = mchp_pdmc_sinc_order_get,
371 .put = mchp_pdmc_sinc_order_put,
372 .private_value = (unsigned long)&mchp_pdmc_sinc_filter_order_enum,
373 },
374 };
375
mchp_pdmc_close(struct snd_soc_component * component,struct snd_pcm_substream * substream)376 static int mchp_pdmc_close(struct snd_soc_component *component,
377 struct snd_pcm_substream *substream)
378 {
379 return snd_soc_add_component_controls(component, mchp_pdmc_snd_controls,
380 ARRAY_SIZE(mchp_pdmc_snd_controls));
381 }
382
mchp_pdmc_open(struct snd_soc_component * component,struct snd_pcm_substream * substream)383 static int mchp_pdmc_open(struct snd_soc_component *component,
384 struct snd_pcm_substream *substream)
385 {
386 int i;
387
388 /* remove controls that can't be changed at runtime */
389 for (i = 0; i < ARRAY_SIZE(mchp_pdmc_snd_controls); i++) {
390 const struct snd_kcontrol_new *control = &mchp_pdmc_snd_controls[i];
391 struct snd_ctl_elem_id id;
392 struct snd_kcontrol *kctl;
393 int err;
394
395 if (component->name_prefix)
396 snprintf(id.name, sizeof(id.name), "%s %s", component->name_prefix,
397 control->name);
398 else
399 strscpy(id.name, control->name, sizeof(id.name));
400
401 id.numid = 0;
402 id.iface = control->iface;
403 id.device = control->device;
404 id.subdevice = control->subdevice;
405 id.index = control->index;
406 kctl = snd_ctl_find_id(component->card->snd_card, &id);
407 if (!kctl) {
408 dev_err(component->dev, "Failed to find %s\n", control->name);
409 continue;
410 }
411 err = snd_ctl_remove(component->card->snd_card, kctl);
412 if (err < 0) {
413 dev_err(component->dev, "%d: Failed to remove %s\n", err,
414 control->name);
415 continue;
416 }
417 }
418
419 return 0;
420 }
421
422 static const struct snd_soc_component_driver mchp_pdmc_dai_component = {
423 .name = "mchp-pdmc",
424 .controls = mchp_pdmc_snd_controls,
425 .num_controls = ARRAY_SIZE(mchp_pdmc_snd_controls),
426 .open = &mchp_pdmc_open,
427 .close = &mchp_pdmc_close,
428 .legacy_dai_naming = 1,
429 .start_dma_last = 1,
430 };
431
432 static const unsigned int mchp_pdmc_1mic[] = {1};
433 static const unsigned int mchp_pdmc_2mic[] = {1, 2};
434 static const unsigned int mchp_pdmc_3mic[] = {1, 2, 3};
435 static const unsigned int mchp_pdmc_4mic[] = {1, 2, 3, 4};
436
437 static const struct snd_pcm_hw_constraint_list mchp_pdmc_chan_constr[] = {
438 {
439 .list = mchp_pdmc_1mic,
440 .count = ARRAY_SIZE(mchp_pdmc_1mic),
441 },
442 {
443 .list = mchp_pdmc_2mic,
444 .count = ARRAY_SIZE(mchp_pdmc_2mic),
445 },
446 {
447 .list = mchp_pdmc_3mic,
448 .count = ARRAY_SIZE(mchp_pdmc_3mic),
449 },
450 {
451 .list = mchp_pdmc_4mic,
452 .count = ARRAY_SIZE(mchp_pdmc_4mic),
453 },
454 };
455
mchp_pdmc_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)456 static int mchp_pdmc_startup(struct snd_pcm_substream *substream,
457 struct snd_soc_dai *dai)
458 {
459 struct mchp_pdmc *dd = snd_soc_dai_get_drvdata(dai);
460
461 regmap_write(dd->regmap, MCHP_PDMC_CR, MCHP_PDMC_CR_SWRST);
462
463 snd_pcm_hw_constraint_list(substream->runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
464 &mchp_pdmc_chan_constr[dd->mic_no - 1]);
465
466 return 0;
467 }
468
mchp_pdmc_dai_probe(struct snd_soc_dai * dai)469 static int mchp_pdmc_dai_probe(struct snd_soc_dai *dai)
470 {
471 struct mchp_pdmc *dd = snd_soc_dai_get_drvdata(dai);
472
473 snd_soc_dai_init_dma_data(dai, NULL, &dd->addr);
474
475 return 0;
476 }
477
mchp_pdmc_set_fmt(struct snd_soc_dai * dai,unsigned int fmt)478 static int mchp_pdmc_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
479 {
480 unsigned int fmt_master = fmt & SND_SOC_DAIFMT_MASTER_MASK;
481 unsigned int fmt_format = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
482
483 /* IP needs to be bitclock master */
484 if (fmt_master != SND_SOC_DAIFMT_BP_FP &&
485 fmt_master != SND_SOC_DAIFMT_BP_FC)
486 return -EINVAL;
487
488 /* IP supports only PDM interface */
489 if (fmt_format != SND_SOC_DAIFMT_PDM)
490 return -EINVAL;
491
492 return 0;
493 }
494
mchp_pdmc_mr_set_osr(int audio_filter_en,unsigned int osr)495 static u32 mchp_pdmc_mr_set_osr(int audio_filter_en, unsigned int osr)
496 {
497 if (audio_filter_en) {
498 switch (osr) {
499 case 64:
500 return MCHP_PDMC_MR_OSR64;
501 case 128:
502 return MCHP_PDMC_MR_OSR128;
503 case 256:
504 return MCHP_PDMC_MR_OSR256;
505 }
506 } else {
507 switch (osr) {
508 case 8:
509 return MCHP_PDMC_MR_SINC_OSR_8;
510 case 16:
511 return MCHP_PDMC_MR_SINC_OSR_16;
512 case 32:
513 return MCHP_PDMC_MR_SINC_OSR_32;
514 case 64:
515 return MCHP_PDMC_MR_SINC_OSR_64;
516 case 128:
517 return MCHP_PDMC_MR_SINC_OSR_128;
518 case 256:
519 return MCHP_PDMC_MR_SINC_OSR_256;
520 }
521 }
522 return 0;
523 }
524
mchp_pdmc_period_to_maxburst(int period_size)525 static inline int mchp_pdmc_period_to_maxburst(int period_size)
526 {
527 if (!(period_size % 8))
528 return 8;
529 if (!(period_size % 4))
530 return 4;
531 if (!(period_size % 2))
532 return 2;
533 return 1;
534 }
535
536 static struct snd_pcm_chmap_elem mchp_pdmc_std_chmaps[] = {
537 { .channels = 1,
538 .map = { SNDRV_CHMAP_MONO } },
539 { .channels = 2,
540 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR } },
541 { .channels = 3,
542 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
543 SNDRV_CHMAP_RL } },
544 { .channels = 4,
545 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
546 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
547 { }
548 };
549
mchp_pdmc_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)550 static int mchp_pdmc_hw_params(struct snd_pcm_substream *substream,
551 struct snd_pcm_hw_params *params,
552 struct snd_soc_dai *dai)
553 {
554 struct mchp_pdmc *dd = snd_soc_dai_get_drvdata(dai);
555 struct snd_soc_component *comp = dai->component;
556 unsigned long gclk_rate = 0;
557 unsigned long best_diff_rate = ~0UL;
558 unsigned int channels = params_channels(params);
559 unsigned int osr = 0, osr_start;
560 unsigned int fs = params_rate(params);
561 u32 mr_val = 0;
562 u32 cfgr_val = 0;
563 int i;
564 int ret;
565
566 dev_dbg(comp->dev, "%s() rate=%u format=%#x width=%u channels=%u\n",
567 __func__, params_rate(params), params_format(params),
568 params_width(params), params_channels(params));
569
570 if (channels > dd->mic_no) {
571 dev_err(comp->dev, "more channels %u than microphones %d\n",
572 channels, dd->mic_no);
573 return -EINVAL;
574 }
575
576 dd->pdmcen = 0;
577 for (i = 0; i < channels; i++) {
578 dd->pdmcen |= MCHP_PDMC_MR_PDMCEN(i);
579 if (dd->channel_mic_map[i].ds_pos)
580 cfgr_val |= MCHP_PDMC_CFGR_PDMSEL(i);
581 if (dd->channel_mic_map[i].clk_edge)
582 cfgr_val |= MCHP_PDMC_CFGR_BSSEL(i);
583 }
584
585 for (osr_start = dd->audio_filter_en ? 64 : 8;
586 osr_start <= 256 && best_diff_rate; osr_start *= 2) {
587 long round_rate;
588 unsigned long diff_rate;
589
590 round_rate = clk_round_rate(dd->gclk,
591 (unsigned long)fs * 16 * osr_start);
592 if (round_rate < 0)
593 continue;
594 diff_rate = abs((fs * 16 * osr_start) - round_rate);
595 if (diff_rate < best_diff_rate) {
596 best_diff_rate = diff_rate;
597 osr = osr_start;
598 gclk_rate = fs * 16 * osr;
599 }
600 }
601 if (!gclk_rate) {
602 dev_err(comp->dev, "invalid sampling rate: %u\n", fs);
603 return -EINVAL;
604 }
605
606 /* CLK is enabled by runtime PM. */
607 clk_disable_unprepare(dd->gclk);
608
609 /* set the rate */
610 ret = clk_set_rate(dd->gclk, gclk_rate);
611 clk_prepare_enable(dd->gclk);
612 if (ret) {
613 dev_err(comp->dev, "unable to set rate %lu to GCLK: %d\n",
614 gclk_rate, ret);
615 return ret;
616 }
617
618 mr_val |= mchp_pdmc_mr_set_osr(dd->audio_filter_en, osr);
619
620 mr_val |= MCHP_PDMC_MR_SINCORDER(dd->sinc_order);
621
622 dd->addr.maxburst = mchp_pdmc_period_to_maxburst(snd_pcm_lib_period_bytes(substream));
623 mr_val |= MCHP_PDMC_MR_CHUNK(dd->addr.maxburst);
624 dev_dbg(comp->dev, "maxburst set to %d\n", dd->addr.maxburst);
625
626 snd_soc_component_update_bits(comp, MCHP_PDMC_MR,
627 MCHP_PDMC_MR_OSR_MASK |
628 MCHP_PDMC_MR_SINCORDER_MASK |
629 MCHP_PDMC_MR_SINC_OSR_MASK |
630 MCHP_PDMC_MR_CHUNK_MASK, mr_val);
631
632 snd_soc_component_write(comp, MCHP_PDMC_CFGR, cfgr_val);
633
634 return 0;
635 }
636
mchp_pdmc_noise_filter_workaround(struct mchp_pdmc * dd)637 static void mchp_pdmc_noise_filter_workaround(struct mchp_pdmc *dd)
638 {
639 u32 tmp, steps = 16;
640
641 /*
642 * PDMC doesn't wait for microphones' startup time thus the acquisition
643 * may start before the microphones are ready leading to poc noises at
644 * the beginning of capture. To avoid this, we need to wait 50ms (in
645 * normal startup procedure) or 150 ms (worst case after resume from sleep
646 * states) after microphones are enabled and then clear the FIFOs (by
647 * reading the RHR 16 times) and possible interrupts before continuing.
648 * Also, for this to work the DMA needs to be started after interrupts
649 * are enabled.
650 */
651 usleep_range(dd->startup_delay_us, dd->startup_delay_us + 5);
652
653 while (steps--)
654 regmap_read(dd->regmap, MCHP_PDMC_RHR, &tmp);
655
656 /* Clear interrupts. */
657 regmap_read(dd->regmap, MCHP_PDMC_ISR, &tmp);
658 }
659
mchp_pdmc_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)660 static int mchp_pdmc_trigger(struct snd_pcm_substream *substream,
661 int cmd, struct snd_soc_dai *dai)
662 {
663 struct mchp_pdmc *dd = snd_soc_dai_get_drvdata(dai);
664 struct snd_soc_component *cpu = dai->component;
665 #ifdef DEBUG
666 u32 val;
667 #endif
668
669 switch (cmd) {
670 case SNDRV_PCM_TRIGGER_RESUME:
671 case SNDRV_PCM_TRIGGER_START:
672 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
673 snd_soc_component_update_bits(cpu, MCHP_PDMC_MR,
674 MCHP_PDMC_MR_PDMCEN_MASK,
675 dd->pdmcen);
676
677 mchp_pdmc_noise_filter_workaround(dd);
678
679 /* Enable interrupts. */
680 regmap_write(dd->regmap, MCHP_PDMC_IER, dd->suspend_irq |
681 MCHP_PDMC_IR_RXOVR | MCHP_PDMC_IR_RXUDR);
682 dd->suspend_irq = 0;
683 break;
684 case SNDRV_PCM_TRIGGER_SUSPEND:
685 regmap_read(dd->regmap, MCHP_PDMC_IMR, &dd->suspend_irq);
686 fallthrough;
687 case SNDRV_PCM_TRIGGER_STOP:
688 /* Disable overrun and underrun error interrupts */
689 regmap_write(dd->regmap, MCHP_PDMC_IDR, dd->suspend_irq |
690 MCHP_PDMC_IR_RXOVR | MCHP_PDMC_IR_RXUDR);
691 fallthrough;
692 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
693 snd_soc_component_update_bits(cpu, MCHP_PDMC_MR,
694 MCHP_PDMC_MR_PDMCEN_MASK, 0);
695 break;
696 default:
697 return -EINVAL;
698 }
699
700 #ifdef DEBUG
701 regmap_read(dd->regmap, MCHP_PDMC_MR, &val);
702 dev_dbg(dd->dev, "MR (0x%02x): 0x%08x\n", MCHP_PDMC_MR, val);
703 regmap_read(dd->regmap, MCHP_PDMC_CFGR, &val);
704 dev_dbg(dd->dev, "CFGR (0x%02x): 0x%08x\n", MCHP_PDMC_CFGR, val);
705 regmap_read(dd->regmap, MCHP_PDMC_IMR, &val);
706 dev_dbg(dd->dev, "IMR (0x%02x): 0x%08x\n", MCHP_PDMC_IMR, val);
707 #endif
708
709 return 0;
710 }
711
712 static const struct snd_soc_dai_ops mchp_pdmc_dai_ops = {
713 .set_fmt = mchp_pdmc_set_fmt,
714 .startup = mchp_pdmc_startup,
715 .hw_params = mchp_pdmc_hw_params,
716 .trigger = mchp_pdmc_trigger,
717 };
718
mchp_pdmc_add_chmap_ctls(struct snd_pcm * pcm,struct mchp_pdmc * dd)719 static int mchp_pdmc_add_chmap_ctls(struct snd_pcm *pcm, struct mchp_pdmc *dd)
720 {
721 struct mchp_pdmc_chmap *info;
722 struct snd_kcontrol_new knew = {
723 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
724 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
725 SNDRV_CTL_ELEM_ACCESS_TLV_READ |
726 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK,
727 .info = mchp_pdmc_chmap_ctl_info,
728 .get = mchp_pdmc_chmap_ctl_get,
729 .put = mchp_pdmc_chmap_ctl_put,
730 .tlv.c = mchp_pdmc_chmap_ctl_tlv,
731 };
732 int err;
733
734 if (WARN_ON(pcm->streams[SNDRV_PCM_STREAM_CAPTURE].chmap_kctl))
735 return -EBUSY;
736 info = kzalloc(sizeof(*info), GFP_KERNEL);
737 if (!info)
738 return -ENOMEM;
739 info->pcm = pcm;
740 info->dd = dd;
741 info->chmap = mchp_pdmc_std_chmaps;
742 knew.name = "Capture Channel Map";
743 knew.device = pcm->device;
744 knew.count = pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream_count;
745 info->kctl = snd_ctl_new1(&knew, info);
746 if (!info->kctl) {
747 kfree(info);
748 return -ENOMEM;
749 }
750 info->kctl->private_free = mchp_pdmc_chmap_ctl_private_free;
751 err = snd_ctl_add(pcm->card, info->kctl);
752 if (err < 0)
753 return err;
754 pcm->streams[SNDRV_PCM_STREAM_CAPTURE].chmap_kctl = info->kctl;
755 return 0;
756 }
757
mchp_pdmc_pcm_new(struct snd_soc_pcm_runtime * rtd,struct snd_soc_dai * dai)758 static int mchp_pdmc_pcm_new(struct snd_soc_pcm_runtime *rtd,
759 struct snd_soc_dai *dai)
760 {
761 struct mchp_pdmc *dd = snd_soc_dai_get_drvdata(dai);
762 int ret;
763
764 ret = mchp_pdmc_add_chmap_ctls(rtd->pcm, dd);
765 if (ret < 0) {
766 dev_err(dd->dev, "failed to add channel map controls: %d\n", ret);
767 return ret;
768 }
769
770 return 0;
771 }
772
773 static struct snd_soc_dai_driver mchp_pdmc_dai = {
774 .probe = mchp_pdmc_dai_probe,
775 .capture = {
776 .stream_name = "Capture",
777 .channels_min = 1,
778 .channels_max = 4,
779 .rate_min = 8000,
780 .rate_max = 192000,
781 .rates = SNDRV_PCM_RATE_KNOT,
782 .formats = SNDRV_PCM_FMTBIT_S24_LE,
783 },
784 .ops = &mchp_pdmc_dai_ops,
785 .pcm_new = &mchp_pdmc_pcm_new,
786 };
787
788 /* PDMC interrupt handler */
mchp_pdmc_interrupt(int irq,void * dev_id)789 static irqreturn_t mchp_pdmc_interrupt(int irq, void *dev_id)
790 {
791 struct mchp_pdmc *dd = (struct mchp_pdmc *)dev_id;
792 u32 isr, msr, pending;
793 irqreturn_t ret = IRQ_NONE;
794
795 regmap_read(dd->regmap, MCHP_PDMC_ISR, &isr);
796 regmap_read(dd->regmap, MCHP_PDMC_IMR, &msr);
797
798 pending = isr & msr;
799 dev_dbg(dd->dev, "ISR (0x%02x): 0x%08x, IMR (0x%02x): 0x%08x, pending: 0x%08x\n",
800 MCHP_PDMC_ISR, isr, MCHP_PDMC_IMR, msr, pending);
801 if (!pending)
802 return IRQ_NONE;
803
804 if (pending & MCHP_PDMC_IR_RXUDR) {
805 dev_warn(dd->dev, "underrun detected\n");
806 regmap_write(dd->regmap, MCHP_PDMC_IDR, MCHP_PDMC_IR_RXUDR);
807 ret = IRQ_HANDLED;
808 }
809 if (pending & MCHP_PDMC_IR_RXOVR) {
810 dev_warn(dd->dev, "overrun detected\n");
811 regmap_write(dd->regmap, MCHP_PDMC_IDR, MCHP_PDMC_IR_RXOVR);
812 ret = IRQ_HANDLED;
813 }
814
815 return ret;
816 }
817
818 /* regmap configuration */
mchp_pdmc_readable_reg(struct device * dev,unsigned int reg)819 static bool mchp_pdmc_readable_reg(struct device *dev, unsigned int reg)
820 {
821 switch (reg) {
822 case MCHP_PDMC_MR:
823 case MCHP_PDMC_CFGR:
824 case MCHP_PDMC_IMR:
825 case MCHP_PDMC_ISR:
826 case MCHP_PDMC_RHR:
827 case MCHP_PDMC_VER:
828 return true;
829 default:
830 return false;
831 }
832 }
833
mchp_pdmc_writeable_reg(struct device * dev,unsigned int reg)834 static bool mchp_pdmc_writeable_reg(struct device *dev, unsigned int reg)
835 {
836 switch (reg) {
837 case MCHP_PDMC_CR:
838 case MCHP_PDMC_MR:
839 case MCHP_PDMC_CFGR:
840 case MCHP_PDMC_IER:
841 case MCHP_PDMC_IDR:
842 return true;
843 default:
844 return false;
845 }
846 }
847
mchp_pdmc_volatile_reg(struct device * dev,unsigned int reg)848 static bool mchp_pdmc_volatile_reg(struct device *dev, unsigned int reg)
849 {
850 switch (reg) {
851 case MCHP_PDMC_ISR:
852 case MCHP_PDMC_RHR:
853 return true;
854 default:
855 return false;
856 }
857 }
858
mchp_pdmc_precious_reg(struct device * dev,unsigned int reg)859 static bool mchp_pdmc_precious_reg(struct device *dev, unsigned int reg)
860 {
861 switch (reg) {
862 case MCHP_PDMC_RHR:
863 case MCHP_PDMC_ISR:
864 return true;
865 default:
866 return false;
867 }
868 }
869
870 static const struct regmap_config mchp_pdmc_regmap_config = {
871 .reg_bits = 32,
872 .reg_stride = 4,
873 .val_bits = 32,
874 .max_register = MCHP_PDMC_VER,
875 .readable_reg = mchp_pdmc_readable_reg,
876 .writeable_reg = mchp_pdmc_writeable_reg,
877 .precious_reg = mchp_pdmc_precious_reg,
878 .volatile_reg = mchp_pdmc_volatile_reg,
879 .cache_type = REGCACHE_FLAT,
880 };
881
mchp_pdmc_dt_init(struct mchp_pdmc * dd)882 static int mchp_pdmc_dt_init(struct mchp_pdmc *dd)
883 {
884 struct device_node *np = dd->dev->of_node;
885 bool mic_ch[MCHP_PDMC_DS_NO][MCHP_PDMC_EDGE_NO] = {0};
886 int i;
887 int ret;
888
889 if (!np) {
890 dev_err(dd->dev, "device node not found\n");
891 return -EINVAL;
892 }
893
894 dd->mic_no = of_property_count_u32_elems(np, "microchip,mic-pos");
895 if (dd->mic_no < 0) {
896 dev_err(dd->dev, "failed to get microchip,mic-pos: %d",
897 dd->mic_no);
898 return dd->mic_no;
899 }
900 if (!dd->mic_no || dd->mic_no % 2 ||
901 dd->mic_no / 2 > MCHP_PDMC_MAX_CHANNELS) {
902 dev_err(dd->dev, "invalid array length for microchip,mic-pos: %d",
903 dd->mic_no);
904 return -EINVAL;
905 }
906
907 dd->mic_no /= 2;
908
909 dev_info(dd->dev, "%d PDM microphones declared\n", dd->mic_no);
910
911 /*
912 * by default, we consider the order of microphones in
913 * microchip,mic-pos to be the same with the channel mapping;
914 * 1st microphone channel 0, 2nd microphone channel 1, etc.
915 */
916 for (i = 0; i < dd->mic_no; i++) {
917 int ds;
918 int edge;
919
920 ret = of_property_read_u32_index(np, "microchip,mic-pos", i * 2,
921 &ds);
922 if (ret) {
923 dev_err(dd->dev,
924 "failed to get value no %d value from microchip,mic-pos: %d",
925 i * 2, ret);
926 return ret;
927 }
928 if (ds >= MCHP_PDMC_DS_NO) {
929 dev_err(dd->dev,
930 "invalid DS index in microchip,mic-pos array: %d",
931 ds);
932 return -EINVAL;
933 }
934
935 ret = of_property_read_u32_index(np, "microchip,mic-pos", i * 2 + 1,
936 &edge);
937 if (ret) {
938 dev_err(dd->dev,
939 "failed to get value no %d value from microchip,mic-pos: %d",
940 i * 2 + 1, ret);
941 return ret;
942 }
943
944 if (edge != MCHP_PDMC_CLK_POSITIVE &&
945 edge != MCHP_PDMC_CLK_NEGATIVE) {
946 dev_err(dd->dev,
947 "invalid edge in microchip,mic-pos array: %d", edge);
948 return -EINVAL;
949 }
950 if (mic_ch[ds][edge]) {
951 dev_err(dd->dev,
952 "duplicated mic (DS %d, edge %d) in microchip,mic-pos array",
953 ds, edge);
954 return -EINVAL;
955 }
956 mic_ch[ds][edge] = true;
957 dd->channel_mic_map[i].ds_pos = ds;
958 dd->channel_mic_map[i].clk_edge = edge;
959 }
960
961 dd->startup_delay_us = 150000;
962 of_property_read_u32(np, "microchip,startup-delay-us", &dd->startup_delay_us);
963
964 return 0;
965 }
966
967 /* used to clean the channel index found on RHR's MSB */
mchp_pdmc_process(struct snd_pcm_substream * substream,int channel,unsigned long hwoff,void * buf,unsigned long bytes)968 static int mchp_pdmc_process(struct snd_pcm_substream *substream,
969 int channel, unsigned long hwoff,
970 void *buf, unsigned long bytes)
971 {
972 struct snd_pcm_runtime *runtime = substream->runtime;
973 u8 *dma_ptr = runtime->dma_area + hwoff +
974 channel * (runtime->dma_bytes / runtime->channels);
975 u8 *dma_ptr_end = dma_ptr + bytes;
976 unsigned int sample_size = samples_to_bytes(runtime, 1);
977
978 for (; dma_ptr < dma_ptr_end; dma_ptr += sample_size)
979 *dma_ptr = 0;
980
981 return 0;
982 }
983
984 static struct snd_dmaengine_pcm_config mchp_pdmc_config = {
985 .process = mchp_pdmc_process,
986 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
987 };
988
mchp_pdmc_runtime_suspend(struct device * dev)989 static int mchp_pdmc_runtime_suspend(struct device *dev)
990 {
991 struct mchp_pdmc *dd = dev_get_drvdata(dev);
992
993 regcache_cache_only(dd->regmap, true);
994
995 clk_disable_unprepare(dd->gclk);
996 clk_disable_unprepare(dd->pclk);
997
998 return 0;
999 }
1000
mchp_pdmc_runtime_resume(struct device * dev)1001 static int mchp_pdmc_runtime_resume(struct device *dev)
1002 {
1003 struct mchp_pdmc *dd = dev_get_drvdata(dev);
1004 int ret;
1005
1006 ret = clk_prepare_enable(dd->pclk);
1007 if (ret) {
1008 dev_err(dd->dev,
1009 "failed to enable the peripheral clock: %d\n", ret);
1010 return ret;
1011 }
1012 ret = clk_prepare_enable(dd->gclk);
1013 if (ret) {
1014 dev_err(dd->dev,
1015 "failed to enable generic clock: %d\n", ret);
1016 goto disable_pclk;
1017 }
1018
1019 regcache_cache_only(dd->regmap, false);
1020 regcache_mark_dirty(dd->regmap);
1021 ret = regcache_sync(dd->regmap);
1022 if (ret) {
1023 regcache_cache_only(dd->regmap, true);
1024 clk_disable_unprepare(dd->gclk);
1025 disable_pclk:
1026 clk_disable_unprepare(dd->pclk);
1027 }
1028
1029 return ret;
1030 }
1031
mchp_pdmc_probe(struct platform_device * pdev)1032 static int mchp_pdmc_probe(struct platform_device *pdev)
1033 {
1034 struct device *dev = &pdev->dev;
1035 struct mchp_pdmc *dd;
1036 struct resource *res;
1037 void __iomem *io_base;
1038 u32 version;
1039 int irq;
1040 int ret;
1041
1042 dd = devm_kzalloc(dev, sizeof(*dd), GFP_KERNEL);
1043 if (!dd)
1044 return -ENOMEM;
1045
1046 dd->dev = &pdev->dev;
1047 ret = mchp_pdmc_dt_init(dd);
1048 if (ret < 0)
1049 return ret;
1050
1051 irq = platform_get_irq(pdev, 0);
1052 if (irq < 0)
1053 return irq;
1054
1055 dd->pclk = devm_clk_get(dev, "pclk");
1056 if (IS_ERR(dd->pclk)) {
1057 ret = PTR_ERR(dd->pclk);
1058 dev_err(dev, "failed to get peripheral clock: %d\n", ret);
1059 return ret;
1060 }
1061
1062 dd->gclk = devm_clk_get(dev, "gclk");
1063 if (IS_ERR(dd->gclk)) {
1064 ret = PTR_ERR(dd->gclk);
1065 dev_err(dev, "failed to get GCK: %d\n", ret);
1066 return ret;
1067 }
1068
1069 io_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1070 if (IS_ERR(io_base)) {
1071 ret = PTR_ERR(io_base);
1072 dev_err(dev, "failed to remap register memory: %d\n", ret);
1073 return ret;
1074 }
1075
1076 dd->regmap = devm_regmap_init_mmio(dev, io_base,
1077 &mchp_pdmc_regmap_config);
1078 if (IS_ERR(dd->regmap)) {
1079 ret = PTR_ERR(dd->regmap);
1080 dev_err(dev, "failed to init register map: %d\n", ret);
1081 return ret;
1082 }
1083
1084 ret = devm_request_irq(dev, irq, mchp_pdmc_interrupt, 0,
1085 dev_name(&pdev->dev), (void *)dd);
1086 if (ret < 0) {
1087 dev_err(dev, "can't register ISR for IRQ %u (ret=%i)\n",
1088 irq, ret);
1089 return ret;
1090 }
1091
1092 /* by default audio filter is enabled and the SINC Filter order
1093 * will be set to the recommended value, 3
1094 */
1095 dd->audio_filter_en = true;
1096 dd->sinc_order = 3;
1097
1098 dd->addr.addr = (dma_addr_t)res->start + MCHP_PDMC_RHR;
1099 platform_set_drvdata(pdev, dd);
1100
1101 pm_runtime_enable(dd->dev);
1102 if (!pm_runtime_enabled(dd->dev)) {
1103 ret = mchp_pdmc_runtime_resume(dd->dev);
1104 if (ret)
1105 return ret;
1106 }
1107
1108 /* register platform */
1109 ret = devm_snd_dmaengine_pcm_register(dev, &mchp_pdmc_config, 0);
1110 if (ret) {
1111 dev_err(dev, "could not register platform: %d\n", ret);
1112 goto pm_runtime_suspend;
1113 }
1114
1115 ret = devm_snd_soc_register_component(dev, &mchp_pdmc_dai_component,
1116 &mchp_pdmc_dai, 1);
1117 if (ret) {
1118 dev_err(dev, "could not register CPU DAI: %d\n", ret);
1119 goto pm_runtime_suspend;
1120 }
1121
1122 /* print IP version */
1123 regmap_read(dd->regmap, MCHP_PDMC_VER, &version);
1124 dev_info(dd->dev, "hw version: %#lx\n",
1125 version & MCHP_PDMC_VER_VERSION);
1126
1127 return 0;
1128
1129 pm_runtime_suspend:
1130 if (!pm_runtime_status_suspended(dd->dev))
1131 mchp_pdmc_runtime_suspend(dd->dev);
1132 pm_runtime_disable(dd->dev);
1133
1134 return ret;
1135 }
1136
mchp_pdmc_remove(struct platform_device * pdev)1137 static int mchp_pdmc_remove(struct platform_device *pdev)
1138 {
1139 struct mchp_pdmc *dd = platform_get_drvdata(pdev);
1140
1141 if (!pm_runtime_status_suspended(dd->dev))
1142 mchp_pdmc_runtime_suspend(dd->dev);
1143
1144 pm_runtime_disable(dd->dev);
1145
1146 return 0;
1147 }
1148
1149 static const struct of_device_id mchp_pdmc_of_match[] = {
1150 {
1151 .compatible = "microchip,sama7g5-pdmc",
1152 }, {
1153 /* sentinel */
1154 }
1155 };
1156 MODULE_DEVICE_TABLE(of, mchp_pdmc_of_match);
1157
1158 static const struct dev_pm_ops mchp_pdmc_pm_ops = {
1159 SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
1160 RUNTIME_PM_OPS(mchp_pdmc_runtime_suspend, mchp_pdmc_runtime_resume,
1161 NULL)
1162 };
1163
1164 static struct platform_driver mchp_pdmc_driver = {
1165 .driver = {
1166 .name = "mchp-pdmc",
1167 .of_match_table = of_match_ptr(mchp_pdmc_of_match),
1168 .pm = pm_ptr(&mchp_pdmc_pm_ops),
1169 },
1170 .probe = mchp_pdmc_probe,
1171 .remove = mchp_pdmc_remove,
1172 };
1173 module_platform_driver(mchp_pdmc_driver);
1174
1175 MODULE_DESCRIPTION("Microchip PDMC driver under ALSA SoC architecture");
1176 MODULE_AUTHOR("Codrin Ciubotariu <codrin.ciubotariu@microchip.com>");
1177 MODULE_LICENSE("GPL v2");
1178