1# The basic row format is:
2# LEAF, SUBLEAF, register_name, bits, short_name, long_description
3
4# Leaf 00H
5         0,    0,  EAX,   31:0, max_basic_leafs, Max input value for supported subleafs
6
7# Leaf 01H
8         1,    0,  EAX,    3:0, stepping, Stepping ID
9         1,    0,  EAX,    7:4, model, Model
10         1,    0,  EAX,   11:8, family, Family ID
11         1,    0,  EAX,  13:12, processor, Processor Type
12         1,    0,  EAX,  19:16, model_ext, Extended Model ID
13         1,    0,  EAX,  27:20, family_ext, Extended Family ID
14
15         1,    0,  EBX,    7:0, brand, Brand Index
16         1,    0,  EBX,   15:8, clflush_size, CLFLUSH line size (value * 8) in bytes
17         1,    0,  EBX,  23:16, max_cpu_id, Maxim number of addressable logic cpu in this package
18         1,    0,  EBX,  31:24, apic_id, Initial APIC ID
19
20         1,    0,  ECX,      0, sse3, Streaming SIMD Extensions 3(SSE3)
21         1,    0,  ECX,      1, pclmulqdq, PCLMULQDQ instruction supported
22         1,    0,  ECX,      2, dtes64, DS area uses 64-bit layout
23         1,    0,  ECX,      3, mwait, MONITOR/MWAIT supported
24         1,    0,  ECX,      4, ds_cpl, CPL Qualified Debug Store which allows for branch message storage qualified by CPL
25         1,    0,  ECX,      5, vmx, Virtual Machine Extensions supported
26         1,    0,  ECX,      6, smx, Safer Mode Extension supported
27         1,    0,  ECX,      7, eist, Enhanced Intel SpeedStep Technology
28         1,    0,  ECX,      8, tm2, Thermal Monitor 2
29         1,    0,  ECX,      9, ssse3, Supplemental Streaming SIMD Extensions 3 (SSSE3)
30         1,    0,  ECX,     10, l1_ctx_id, L1 data cache could be set to either adaptive mode or shared mode (check IA32_MISC_ENABLE bit 24 definition)
31         1,    0,  ECX,     11, sdbg, IA32_DEBUG_INTERFACE MSR for silicon debug supported
32         1,    0,  ECX,     12, fma, FMA extensions using YMM state supported
33         1,    0,  ECX,     13, cmpxchg16b, 'CMPXCHG16B - Compare and Exchange Bytes' supported
34         1,    0,  ECX,     14, xtpr_update, xTPR Update Control supported
35         1,    0,  ECX,     15, pdcm, Perfmon and Debug Capability present
36         1,    0,  ECX,     17, pcid, Process-Context Identifiers feature present
37         1,    0,  ECX,     18, dca, Prefetching data from a memory mapped device supported
38         1,    0,  ECX,     19, sse4_1, SSE4.1 feature present
39         1,    0,  ECX,     20, sse4_2, SSE4.2 feature present
40         1,    0,  ECX,     21, x2apic, x2APIC supported
41         1,    0,  ECX,     22, movbe, MOVBE instruction supported
42         1,    0,  ECX,     23, popcnt, POPCNT instruction supported
43         1,    0,  ECX,     24, tsc_deadline_timer, LAPIC supports one-shot operation using a TSC deadline value
44         1,    0,  ECX,     25, aesni, AESNI instruction supported
45         1,    0,  ECX,     26, xsave, XSAVE/XRSTOR processor extended states (XSETBV/XGETBV/XCR0)
46         1,    0,  ECX,     27, osxsave, OS has set CR4.OSXSAVE bit to enable XSETBV/XGETBV/XCR0
47         1,    0,  ECX,     28, avx, AVX instruction supported
48         1,    0,  ECX,     29, f16c, 16-bit floating-point conversion instruction supported
49         1,    0,  ECX,     30, rdrand, RDRAND instruction supported
50
51         1,    0,  EDX,      0, fpu, x87 FPU on chip
52         1,    0,  EDX,      1, vme, Virtual-8086 Mode Enhancement
53         1,    0,  EDX,      2, de, Debugging Extensions
54         1,    0,  EDX,      3, pse, Page Size Extensions
55         1,    0,  EDX,      4, tsc, Time Stamp Counter
56         1,    0,  EDX,      5, msr, RDMSR and WRMSR Support
57         1,    0,  EDX,      6, pae, Physical Address Extensions
58         1,    0,  EDX,      7, mce, Machine Check Exception
59         1,    0,  EDX,      8, cx8, CMPXCHG8B instr
60         1,    0,  EDX,      9, apic, APIC on Chip
61         1,    0,  EDX,     11, sep, SYSENTER and SYSEXIT instrs
62         1,    0,  EDX,     12, mtrr, Memory Type Range Registers
63         1,    0,  EDX,     13, pge, Page Global Bit
64         1,    0,  EDX,     14, mca, Machine Check Architecture
65         1,    0,  EDX,     15, cmov, Conditional Move Instrs
66         1,    0,  EDX,     16, pat, Page Attribute Table
67         1,    0,  EDX,     17, pse36, 36-Bit Page Size Extension
68         1,    0,  EDX,     18, psn, Processor Serial Number
69         1,    0,  EDX,     19, clflush, CLFLUSH instr
70#         1,    0,  EDX,     20,
71         1,    0,  EDX,     21, ds, Debug Store
72         1,    0,  EDX,     22, acpi, Thermal Monitor and Software Controlled Clock Facilities
73         1,    0,  EDX,     23, mmx, Intel MMX Technology
74         1,    0,  EDX,     24, fxsr, XSAVE and FXRSTOR Instrs
75         1,    0,  EDX,     25, sse, SSE
76         1,    0,  EDX,     26, sse2, SSE2
77         1,    0,  EDX,     27, ss, Self Snoop
78         1,    0,  EDX,     28, hit, Max APIC IDs
79         1,    0,  EDX,     29, tm, Thermal Monitor
80#         1,    0,  EDX,     30,
81         1,    0,  EDX,     31, pbe, Pending Break Enable
82
83# Leaf 02H
84# cache and TLB descriptor info
85
86# Leaf 03H
87# Precessor Serial Number, introduced on Pentium III, not valid for
88# latest models
89
90# Leaf 04H
91# thread/core and cache topology
92         4,    0,  EAX,    4:0, cache_type, Cache type like instr/data or unified
93         4,    0,  EAX,    7:5, cache_level, Cache Level (starts at 1)
94         4,    0,  EAX,      8, cache_self_init, Cache Self Initialization
95         4,    0,  EAX,      9, fully_associate, Fully Associative cache
96#         4,    0,  EAX,  13:10, resvd, resvd
97         4,    0,  EAX,  25:14, max_logical_id, Max number of addressable IDs for logical processors sharing the cache
98         4,    0,  EAX,  31:26, max_phy_id, Max number of addressable IDs for processors in phy package
99
100         4,    0,  EBX,   11:0, cache_linesize, Size of a cache line in bytes
101         4,    0,  EBX,  21:12, cache_partition, Physical Line partitions
102         4,    0,  EBX,  31:22, cache_ways, Ways of associativity
103         4,    0,  ECX,   31:0, cache_sets, Number of Sets - 1
104         4,    0,  EDX,      0, c_wbinvd, 1 means WBINVD/INVD is not ganranteed to act upon lower level caches of non-originating threads sharing this cache
105         4,    0,  EDX,      1, c_incl, Whether cache is inclusive of lower cache level
106         4,    0,  EDX,      2, c_comp_index, Complex Cache Indexing
107
108# Leaf 05H
109# MONITOR/MWAIT
110	 5,    0,  EAX,   15:0, min_mon_size, Smallest monitor line size in bytes
111	 5,    0,  EBX,   15:0, max_mon_size, Largest monitor line size in bytes
112	 5,    0,  ECX,      0, mwait_ext, Enum of Monitor-Mwait extensions supported
113	 5,    0,  ECX,      1, mwait_irq_break, Largest monitor line size in bytes
114	 5,    0,  EDX,    3:0, c0_sub_stats, Number of C0* sub C-states supported using MWAIT
115	 5,    0,  EDX,    7:4, c1_sub_stats, Number of C1* sub C-states supported using MWAIT
116	 5,    0,  EDX,   11:8, c2_sub_stats, Number of C2* sub C-states supported using MWAIT
117	 5,    0,  EDX,  15:12, c3_sub_stats, Number of C3* sub C-states supported using MWAIT
118	 5,    0,  EDX,  19:16, c4_sub_stats, Number of C4* sub C-states supported using MWAIT
119	 5,    0,  EDX,  23:20, c5_sub_stats, Number of C5* sub C-states supported using MWAIT
120	 5,    0,  EDX,  27:24, c6_sub_stats, Number of C6* sub C-states supported using MWAIT
121	 5,    0,  EDX,  31:28, c7_sub_stats, Number of C7* sub C-states supported using MWAIT
122
123# Leaf 06H
124# Thermal & Power Management
125
126	 6,    0,  EAX,      0, dig_temp, Digital temperature sensor supported
127	 6,    0,  EAX,      1, turbo, Intel Turbo Boost
128	 6,    0,  EAX,      2, arat, Always running APIC timer
129#	 6,    0,  EAX,      3, resv, Reserved
130	 6,    0,  EAX,      4, pln, Power limit notifications supported
131	 6,    0,  EAX,      5, ecmd, Clock modulation duty cycle extension supported
132	 6,    0,  EAX,      6, ptm, Package thermal management supported
133	 6,    0,  EAX,      7, hwp, HWP base register
134	 6,    0,  EAX,      8, hwp_notify, HWP notification
135	 6,    0,  EAX,      9, hwp_act_window, HWP activity window
136	 6,    0,  EAX,     10, hwp_energy, HWP energy performance preference
137	 6,    0,  EAX,     11, hwp_pkg_req, HWP package level request
138#	 6,    0,  EAX,     12, resv, Reserved
139	 6,    0,  EAX,     13, hdc, HDC base registers supported
140	 6,    0,  EAX,     14, turbo3, Turbo Boost Max 3.0
141	 6,    0,  EAX,     15, hwp_cap, Highest Performance change supported
142	 6,    0,  EAX,     16, hwp_peci, HWP PECI override is supported
143	 6,    0,  EAX,     17, hwp_flex, Flexible HWP is supported
144	 6,    0,  EAX,     18, hwp_fast, Fast access mode for the IA32_HWP_REQUEST MSR is supported
145#	 6,    0,  EAX,     19, resv, Reserved
146	 6,    0,  EAX,     20, hwp_ignr, Ignoring Idle Logical Processor HWP request is supported
147
148	 6,    0,  EBX,    3:0, therm_irq_thresh, Number of Interrupt Thresholds in Digital Thermal Sensor
149	 6,    0,  ECX,      0, aperfmperf, Presence of IA32_MPERF and IA32_APERF
150	 6,    0,  ECX,      3, energ_bias, Performance-energy bias preference supported
151
152# Leaf 07H
153#	ECX == 0
154# AVX512 refers to https://en.wikipedia.org/wiki/AVX-512
155# XXX: Do we really need to enumerate each and every AVX512 sub features
156
157	 7,    0,  EBX,      0, fsgsbase, RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE supported
158	 7,    0,  EBX,      1, tsc_adjust, TSC_ADJUST MSR supported
159	 7,    0,  EBX,      2, sgx, Software Guard Extensions
160	 7,    0,  EBX,      3, bmi1, BMI1
161	 7,    0,  EBX,      4, hle, Hardware Lock Elision
162	 7,    0,  EBX,      5, avx2, AVX2
163#	 7,    0,  EBX,      6, fdp_excp_only, x87 FPU Data Pointer updated only on x87 exceptions
164	 7,    0,  EBX,      7, smep, Supervisor-Mode Execution Prevention
165	 7,    0,  EBX,      8, bmi2, BMI2
166	 7,    0,  EBX,      9, rep_movsb, Enhanced REP MOVSB/STOSB
167	 7,    0,  EBX,     10, invpcid, INVPCID instruction
168	 7,    0,  EBX,     11, rtm, Restricted Transactional Memory
169	 7,    0,  EBX,     12, rdt_m, Intel RDT Monitoring capability
170	 7,    0,  EBX,     13, depc_fpu_cs_ds, Deprecates FPU CS and FPU DS
171	 7,    0,  EBX,     14, mpx, Memory Protection Extensions
172	 7,    0,  EBX,     15, rdt_a, Intel RDT Allocation capability
173	 7,    0,  EBX,     16, avx512f, AVX512 Foundation instr
174	 7,    0,  EBX,     17, avx512dq, AVX512 Double and Quadword AVX512 instr
175	 7,    0,  EBX,     18, rdseed, RDSEED instr
176	 7,    0,  EBX,     19, adx, ADX instr
177	 7,    0,  EBX,     20, smap, Supervisor Mode Access Prevention
178	 7,    0,  EBX,     21, avx512ifma, AVX512 Integer Fused Multiply Add
179#	 7,    0,  EBX,     22, resvd, resvd
180	 7,    0,  EBX,     23, clflushopt, CLFLUSHOPT instr
181	 7,    0,  EBX,     24, clwb, CLWB instr
182	 7,    0,  EBX,     25, intel_pt, Intel Processor Trace instr
183	 7,    0,  EBX,     26, avx512pf, Prefetch
184	 7,    0,  EBX,     27, avx512er, AVX512 Exponent Reciproca instr
185	 7,    0,  EBX,     28, avx512cd, AVX512 Conflict Detection instr
186	 7,    0,  EBX,     29, sha, Intel Secure Hash Algorithm Extensions instr
187	 7,    0,  EBX,     26, avx512bw, AVX512 Byte & Word instr
188	 7,    0,  EBX,     28, avx512vl, AVX512 Vector Length Extentions (VL)
189	 7,    0,  ECX,      0, prefetchwt1, X
190	 7,    0,  ECX,      1, avx512vbmi, AVX512 Vector Byte Manipulation Instructions
191	 7,    0,  ECX,      2, umip, User-mode Instruction Prevention
192
193	 7,    0,  ECX,      3, pku, Protection Keys for User-mode pages
194	 7,    0,  ECX,      4, ospke, CR4 PKE set to enable protection keys
195#	 7,    0,  ECX,   16:5, resvd, resvd
196	 7,    0,  ECX,  21:17, mawau, The value of MAWAU used by the BNDLDX and BNDSTX instructions in 64-bit mode
197	 7,    0,  ECX,     22, rdpid, RDPID and IA32_TSC_AUX
198#	 7,    0,  ECX,  29:23, resvd, resvd
199	 7,    0,  ECX,     30, sgx_lc, SGX Launch Configuration
200#	 7,    0,  ECX,     31, resvd, resvd
201
202# Leaf 08H
203#
204
205
206# Leaf 09H
207# Direct Cache Access (DCA) information
208	 9,    0,  ECX,   31:0, dca_cap, The value of IA32_PLATFORM_DCA_CAP
209
210# Leaf 0AH
211# Architectural Performance Monitoring
212#
213# Do we really need to print out the PMU related stuff?
214# Does normal user really care about it?
215#
216       0xA,    0,  EAX,    7:0, pmu_ver, Performance Monitoring Unit version
217       0xA,    0,  EAX,   15:8, pmu_gp_cnt_num, Numer of general-purose PMU counters per logical CPU
218       0xA,    0,  EAX,  23:16, pmu_cnt_bits, Bit wideth of PMU counter
219       0xA,    0,  EAX,  31:24, pmu_ebx_bits, Length of EBX bit vector to enumerate PMU events
220
221       0xA,    0,  EBX,      0, pmu_no_core_cycle_evt, Core cycle event not available
222       0xA,    0,  EBX,      1, pmu_no_instr_ret_evt, Instruction retired event not available
223       0xA,    0,  EBX,      2, pmu_no_ref_cycle_evt, Reference cycles event not available
224       0xA,    0,  EBX,      3, pmu_no_llc_ref_evt, Last-level cache reference event not available
225       0xA,    0,  EBX,      4, pmu_no_llc_mis_evt, Last-level cache misses event not available
226       0xA,    0,  EBX,      5, pmu_no_br_instr_ret_evt, Branch instruction retired event not available
227       0xA,    0,  EBX,      6, pmu_no_br_mispredict_evt, Branch mispredict retired event not available
228
229       0xA,    0,  ECX,    4:0, pmu_fixed_cnt_num, Performance Monitoring Unit version
230       0xA,    0,  ECX,   12:5, pmu_fixed_cnt_bits, Numer of PMU counters per logical CPU
231
232# Leaf 0BH
233# Extended Topology Enumeration Leaf
234#
235
236       0xB,    0,  EAX,    4:0, id_shift, Number of bits to shift right on x2APIC ID to get a unique topology ID of the next level type
237       0xB,    0,  EBX,   15:0, cpu_nr, Number of logical processors at this level type
238       0xB,    0,  ECX,   15:8, lvl_type, 0-Invalid 1-SMT 2-Core
239       0xB,    0,  EDX,   31:0, x2apic_id, x2APIC ID the current logical processor
240
241
242# Leaf 0DH
243# Processor Extended State
244
245       0xD,    0,  EAX,      0, x87, X87 state
246       0xD,    0,  EAX,      1, sse, SSE state
247       0xD,    0,  EAX,      2, avx, AVX state
248       0xD,    0,  EAX,    4:3, mpx, MPX state
249       0xD,    0,  EAX,    7:5, avx512, AVX-512 state
250       0xD,    0,  EAX,      9, pkru, PKRU state
251
252       0xD,    0,  EBX,   31:0, max_sz_xcr0, Maximum size (bytes) required by enabled features in XCR0
253       0xD,    0,  ECX,   31:0, max_sz_xsave, Maximum size (bytes) of the XSAVE/XRSTOR save area
254
255       0xD,    1,  EAX,      0, xsaveopt, XSAVEOPT available
256       0xD,    1,  EAX,      1, xsavec, XSAVEC and compacted form supported
257       0xD,    1,  EAX,      2, xgetbv, XGETBV supported
258       0xD,    1,  EAX,      3, xsaves, XSAVES/XRSTORS and IA32_XSS supported
259
260       0xD,    1,  EBX,   31:0, max_sz_xcr0, Maximum size (bytes) required by enabled features in XCR0
261       0xD,    1,  ECX,      8, pt, PT state
262       0xD,    1,  ECX,      11, cet_usr, CET user state
263       0xD,    1,  ECX,      12, cet_supv, CET supervisor state
264       0xD,    1,  ECX,      13, hdc, HDC state
265       0xD,    1,  ECX,      16, hwp, HWP state
266
267# Leaf 0FH
268# Intel RDT Monitoring
269
270       0xF,    0,  EBX,   31:0, rmid_range, Maximum range (zero-based) of RMID within this physical processor of all types
271       0xF,    0,  EDX,      1, l3c_rdt_mon, L3 Cache RDT Monitoring supported
272
273       0xF,    1,  ECX,   31:0, rmid_range, Maximum range (zero-based) of RMID of this types
274       0xF,    1,  EDX,      0, l3c_ocp_mon, L3 Cache occupancy Monitoring supported
275       0xF,    1,  EDX,      1, l3c_tbw_mon, L3 Cache Total Bandwidth Monitoring supported
276       0xF,    1,  EDX,      2, l3c_lbw_mon, L3 Cache Local Bandwidth Monitoring supported
277
278# Leaf 10H
279# Intel RDT Allocation
280
281      0x10,    0,  EBX,      1, l3c_rdt_alloc, L3 Cache Allocation supported
282      0x10,    0,  EBX,      2, l2c_rdt_alloc, L2 Cache Allocation supported
283      0x10,    0,  EBX,      3, mem_bw_alloc, Memory Bandwidth Allocation supported
284
285
286# Leaf 12H
287# SGX Capability
288#
289# Some detailed SGX features not added yet
290
291      0x12,    0,  EAX,      0, sgx1, L3 Cache Allocation supported
292      0x12,    1,  EAX,      0, sgx2, L3 Cache Allocation supported
293
294
295# Leaf 14H
296# Intel Processor Tracer
297#
298
299# Leaf 15H
300# Time Stamp Counter and Nominal Core Crystal Clock Information
301
302      0x15,    0,  EAX,   31:0, tsc_denominator, The denominator of the TSC/”core crystal clock” ratio
303      0x15,    0,  EBX,   31:0, tsc_numerator, The numerator of the TSC/”core crystal clock” ratio
304      0x15,    0,  ECX,   31:0, nom_freq, Nominal frequency of the core crystal clock in Hz
305
306# Leaf 16H
307# Processor Frequency Information
308
309      0x16,    0,  EAX,   15:0, cpu_base_freq, Processor Base Frequency in MHz
310      0x16,    0,  EBX,   15:0, cpu_max_freq, Maximum Frequency in MHz
311      0x16,    0,  ECX,   15:0, bus_freq, Bus (Reference) Frequency in MHz
312
313# Leaf 17H
314# System-On-Chip Vendor Attribute
315
316      0x17,    0,  EAX,   31:0, max_socid, Maximum input value of supported sub-leaf
317      0x17,    0,  EBX,   15:0, soc_vid, SOC Vendor ID
318      0x17,    0,  EBX,     16, std_vid, SOC Vendor ID is assigned via an industry standard scheme
319      0x17,    0,  ECX,   31:0, soc_pid, SOC Project ID assigned by vendor
320      0x17,    0,  EDX,   31:0, soc_sid, SOC Stepping ID
321
322# Leaf 18H
323# Deterministic Address Translation Parameters
324
325
326# Leaf 19H
327# Key Locker Leaf
328
329
330# Leaf 1AH
331# Hybrid Information
332
333      0x1A,    0,  EAX,  31:24, core_type, 20H-Intel_Atom 40H-Intel_Core
334
335
336# Leaf 1FH
337# V2 Extended Topology - A preferred superset to leaf 0BH
338
339
340# According to SDM
341# 40000000H - 4FFFFFFFH is invalid range
342
343
344# Leaf 80000001H
345# Extended Processor Signature and Feature Bits
346
3470x80000001,    0,  ECX,      0, lahf_lm, LAHF/SAHF available in 64-bit mode
3480x80000001,    0,  ECX,      5, lzcnt, LZCNT
3490x80000001,    0,  ECX,      8, prefetchw, PREFETCHW
350
3510x80000001,    0,  EDX,     11, sysret, SYSCALL/SYSRET supported
3520x80000001,    0,  EDX,     20, exec_dis, Execute Disable Bit available
3530x80000001,    0,  EDX,     26, 1gb_page, 1GB page supported
3540x80000001,    0,  EDX,     27, rdtscp, RDTSCP and IA32_TSC_AUX are available
355#0x80000001,    0,  EDX,     29, 64b, 64b Architecture supported
356
357# Leaf 80000002H/80000003H/80000004H
358# Processor Brand String
359
360# Leaf 80000005H
361# Reserved
362
363# Leaf 80000006H
364# Extended L2 Cache Features
365
3660x80000006,    0,  ECX,    7:0, clsize, Cache Line size in bytes
3670x80000006,    0,  ECX,  15:12, l2c_assoc, L2 Associativity
3680x80000006,    0,  ECX,  31:16, csize, Cache size in 1K units
369
370
371# Leaf 80000007H
372
3730x80000007,    0,  EDX,      8, nonstop_tsc, Invariant TSC available
374
375
376# Leaf 80000008H
377
3780x80000008,    0,  EAX,    7:0, phy_adr_bits, Physical Address Bits
3790x80000008,    0,  EAX,   15:8, lnr_adr_bits, Linear Address Bits
3800x80000007,    0,  EBX,      9, wbnoinvd, WBNOINVD
381
382# 0x8000001E
383# EAX: Extended APIC ID
3840x8000001E,	0, EAX,   31:0, extended_apic_id, Extended APIC ID
385# EBX: Core Identifiers
3860x8000001E,	0, EBX,    7:0, core_id, Identifies the logical core ID
3870x8000001E,	0, EBX,   15:8, threads_per_core, The number of threads per core is threads_per_core + 1
388# ECX: Node Identifiers
3890x8000001E,	0, ECX,    7:0, node_id, Node ID
3900x8000001E,	0, ECX,   10:8, nodes_per_processor, Nodes per processor { 0: 1 node, else reserved }
391
392# 8000001F: AMD Secure Encryption
3930x8000001F,	0, EAX,	     0, sme,	Secure Memory Encryption
3940x8000001F,	0, EAX,      1, sev,	Secure Encrypted Virtualization
3950x8000001F,	0, EAX,      2, vmpgflush, VM Page Flush MSR
3960x8000001F,	0, EAX,      3, seves, SEV Encrypted State
3970x8000001F,	0, EBX,    5:0, c-bit, Page table bit number used to enable memory encryption
3980x8000001F,	0, EBX,   11:6, mem_encrypt_physaddr_width, Reduction of physical address space in bits with SME enabled
3990x8000001F,	0, ECX,   31:0, num_encrypted_guests, Maximum ASID value that may be used for an SEV-enabled guest
4000x8000001F,	0, EDX,   31:0, minimum_sev_asid, Minimum ASID value that must be used for an SEV-enabled, SEV-ES-disabled guest
401