1[ 2 { 3 "BriefDescription": "Counts every 64B read request entering the Memory Controller 0 to DRAM (sum of all channels).", 4 "EventName": "UNC_MC0_RDCAS_COUNT_FREERUN", 5 "PerPkg": "1", 6 "PublicDescription": "Counts every 64B read request entering the Memory Controller 0 to DRAM (sum of all channels).", 7 "Unit": "iMC" 8 }, 9 { 10 "BriefDescription": "Counts every 64B write request entering the Memory Controller 0 to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.", 11 "EventName": "UNC_MC0_WRCAS_COUNT_FREERUN", 12 "PerPkg": "1", 13 "Unit": "iMC" 14 }, 15 { 16 "BriefDescription": "Counts every 64B read request entering the Memory Controller 1 to DRAM (sum of all channels).", 17 "EventName": "UNC_MC1_RDCAS_COUNT_FREERUN", 18 "PerPkg": "1", 19 "PublicDescription": "Counts every 64B read entering the Memory Controller 1 to DRAM (sum of all channels).", 20 "Unit": "iMC" 21 }, 22 { 23 "BriefDescription": "Counts every 64B write request entering the Memory Controller 1 to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.", 24 "EventName": "UNC_MC1_WRCAS_COUNT_FREERUN", 25 "PerPkg": "1", 26 "Unit": "iMC" 27 }, 28 { 29 "BriefDescription": "ACT command for a read request sent to DRAM", 30 "EventCode": "0x24", 31 "EventName": "UNC_M_ACT_COUNT_RD", 32 "PerPkg": "1", 33 "Unit": "iMC" 34 }, 35 { 36 "BriefDescription": "ACT command sent to DRAM", 37 "EventCode": "0x26", 38 "EventName": "UNC_M_ACT_COUNT_TOTAL", 39 "PerPkg": "1", 40 "Unit": "iMC" 41 }, 42 { 43 "BriefDescription": "ACT command for a write request sent to DRAM", 44 "EventCode": "0x25", 45 "EventName": "UNC_M_ACT_COUNT_WR", 46 "PerPkg": "1", 47 "Unit": "iMC" 48 }, 49 { 50 "BriefDescription": "Read CAS command sent to DRAM", 51 "EventCode": "0x22", 52 "EventName": "UNC_M_CAS_COUNT_RD", 53 "PerPkg": "1", 54 "Unit": "iMC" 55 }, 56 { 57 "BriefDescription": "Write CAS command sent to DRAM", 58 "EventCode": "0x23", 59 "EventName": "UNC_M_CAS_COUNT_WR", 60 "PerPkg": "1", 61 "Unit": "iMC" 62 }, 63 { 64 "BriefDescription": "Number of clocks", 65 "EventCode": "0x01", 66 "EventName": "UNC_M_CLOCKTICKS", 67 "PerPkg": "1", 68 "Unit": "iMC" 69 }, 70 { 71 "BriefDescription": "incoming read request page status is Page Empty", 72 "EventCode": "0x1D", 73 "EventName": "UNC_M_DRAM_PAGE_EMPTY_RD", 74 "PerPkg": "1", 75 "Unit": "iMC" 76 }, 77 { 78 "BriefDescription": "incoming write request page status is Page Empty", 79 "EventCode": "0x20", 80 "EventName": "UNC_M_DRAM_PAGE_EMPTY_WR", 81 "PerPkg": "1", 82 "Unit": "iMC" 83 }, 84 { 85 "BriefDescription": "incoming read request page status is Page Hit", 86 "EventCode": "0x1C", 87 "EventName": "UNC_M_DRAM_PAGE_HIT_RD", 88 "PerPkg": "1", 89 "Unit": "iMC" 90 }, 91 { 92 "BriefDescription": "incoming write request page status is Page Hit", 93 "EventCode": "0x1F", 94 "EventName": "UNC_M_DRAM_PAGE_HIT_WR", 95 "PerPkg": "1", 96 "Unit": "iMC" 97 }, 98 { 99 "BriefDescription": "incoming read request page status is Page Miss", 100 "EventCode": "0x1E", 101 "EventName": "UNC_M_DRAM_PAGE_MISS_RD", 102 "PerPkg": "1", 103 "Unit": "iMC" 104 }, 105 { 106 "BriefDescription": "incoming write request page status is Page Miss", 107 "EventCode": "0x21", 108 "EventName": "UNC_M_DRAM_PAGE_MISS_WR", 109 "PerPkg": "1", 110 "Unit": "iMC" 111 }, 112 { 113 "BriefDescription": "Any Rank at Hot state", 114 "EventCode": "0x19", 115 "EventName": "UNC_M_DRAM_THERMAL_HOT", 116 "PerPkg": "1", 117 "Unit": "iMC" 118 }, 119 { 120 "BriefDescription": "Any Rank at Warm state", 121 "EventCode": "0x1A", 122 "EventName": "UNC_M_DRAM_THERMAL_WARM", 123 "PerPkg": "1", 124 "Unit": "iMC" 125 }, 126 { 127 "BriefDescription": "Incoming read prefetch request from IA.", 128 "EventCode": "0x0A", 129 "EventName": "UNC_M_PREFETCH_RD", 130 "PerPkg": "1", 131 "Unit": "iMC" 132 }, 133 { 134 "BriefDescription": "PRE command sent to DRAM due to page table idle timer expiration", 135 "EventCode": "0x28", 136 "EventName": "UNC_M_PRE_COUNT_IDLE", 137 "PerPkg": "1", 138 "Unit": "iMC" 139 }, 140 { 141 "BriefDescription": "PRE command sent to DRAM for a read/write request", 142 "EventCode": "0x27", 143 "EventName": "UNC_M_PRE_COUNT_PAGE_MISS", 144 "PerPkg": "1", 145 "Unit": "iMC" 146 }, 147 { 148 "BriefDescription": "Incoming VC0 read request", 149 "EventCode": "0x02", 150 "EventName": "UNC_M_VC0_REQUESTS_RD", 151 "PerPkg": "1", 152 "Unit": "iMC" 153 }, 154 { 155 "BriefDescription": "Incoming VC0 write request", 156 "EventCode": "0x03", 157 "EventName": "UNC_M_VC0_REQUESTS_WR", 158 "PerPkg": "1", 159 "Unit": "iMC" 160 }, 161 { 162 "BriefDescription": "Incoming VC1 read request", 163 "EventCode": "0x04", 164 "EventName": "UNC_M_VC1_REQUESTS_RD", 165 "PerPkg": "1", 166 "Unit": "iMC" 167 }, 168 { 169 "BriefDescription": "Incoming VC1 write request", 170 "EventCode": "0x05", 171 "EventName": "UNC_M_VC1_REQUESTS_WR", 172 "PerPkg": "1", 173 "Unit": "iMC" 174 } 175] 176