1[
2  {
3    "EventName": "ls_bad_status2.stli_other",
4    "EventCode": "0x24",
5    "BriefDescription": "Non-forwardable conflict; used to reduce STLI's via software. All reasons. Store To Load Interlock (STLI) are loads that were unable to complete because of a possible match with an older store, and the older store could not do STLF for some reason.",
6    "PublicDescription" : "Store-to-load conflicts: A load was unable to complete due to a non-forwardable conflict with an older store. Most commonly, a load's address range partially but not completely overlaps with an uncompleted older store. Software can avoid this problem by using same-size and same-alignment loads and stores when accessing the same data. Vector/SIMD code is particularly susceptible to this problem; software should construct wide vector stores by manipulating vector elements in registers using shuffle/blend/swap instructions prior to storing to memory, instead of using narrow element-by-element stores.",
7    "UMask": "0x02"
8  },
9  {
10    "EventName": "ls_locks.spec_lock_hi_spec",
11    "EventCode": "0x25",
12    "BriefDescription": "Retired lock instructions. High speculative cacheable lock speculation succeeded.",
13    "UMask": "0x08"
14  },
15  {
16    "EventName": "ls_locks.spec_lock_lo_spec",
17    "EventCode": "0x25",
18    "BriefDescription": "Retired lock instructions. Low speculative cacheable lock speculation succeeded.",
19    "UMask": "0x04"
20  },
21  {
22    "EventName": "ls_locks.non_spec_lock",
23    "EventCode": "0x25",
24    "BriefDescription": "Retired lock instructions. Non-speculative lock succeeded.",
25    "UMask": "0x02"
26  },
27  {
28    "EventName": "ls_locks.bus_lock",
29    "EventCode": "0x25",
30    "BriefDescription": "Retired lock instructions. Comparable to legacy bus lock.",
31    "UMask": "0x01"
32  },
33  {
34    "EventName": "ls_ret_cl_flush",
35    "EventCode": "0x26",
36    "BriefDescription": "The number of retired CLFLUSH instructions. This is a non-speculative event."
37  },
38  {
39    "EventName": "ls_ret_cpuid",
40    "EventCode": "0x27",
41    "BriefDescription": "The number of CPUID instructions retired."
42  },
43  {
44    "EventName": "ls_dispatch.ld_st_dispatch",
45    "EventCode": "0x29",
46    "BriefDescription": "Load-op-Store Dispatch. Dispatch of a single op that performs a load from and store to the same memory address. Counts the number of operations dispatched to the LS unit. Unit Masks ADDed.",
47    "UMask": "0x04"
48  },
49  {
50    "EventName": "ls_dispatch.store_dispatch",
51    "EventCode": "0x29",
52    "BriefDescription": "Dispatch of a single op that performs a memory store. Counts the number of operations dispatched to the LS unit. Unit Masks ADDed.",
53    "UMask": "0x02"
54  },
55  {
56    "EventName": "ls_dispatch.ld_dispatch",
57    "EventCode": "0x29",
58    "BriefDescription": "Dispatch of a single op that performs a memory load. Counts the number of operations dispatched to the LS unit. Unit Masks ADDed.",
59    "UMask": "0x01"
60  },
61  {
62    "EventName": "ls_smi_rx",
63    "EventCode": "0x2b",
64    "BriefDescription": "Counts the number of SMIs received."
65  },
66  {
67    "EventName": "ls_int_taken",
68    "EventCode": "0x2c",
69    "BriefDescription": "Counts the number of interrupts taken."
70  },
71  {
72    "EventName": "ls_rdtsc",
73    "EventCode": "0x2d",
74    "BriefDescription": "Number of reads of the TSC (RDTSC instructions). The count is speculative."
75  },
76  {
77    "EventName": "ls_stlf",
78    "EventCode": "0x35",
79    "BriefDescription": "Number of STLF hits."
80  },
81  {
82    "EventName": "ls_st_commit_cancel2.st_commit_cancel_wcb_full",
83    "EventCode": "0x37",
84    "BriefDescription": "A non-cacheable store and the non-cacheable commit buffer is full.",
85    "UMask": "0x01"
86  },
87  {
88    "EventName": "ls_dc_accesses",
89    "EventCode": "0x40",
90    "BriefDescription": "Number of accesses to the dcache for load/store references.",
91    "PublicDescription": "The number of accesses to the data cache for load and store references. This may include certain microcode scratchpad accesses, although these are generally rare. Each increment represents an eight-byte access, although the instruction may only be accessing a portion of that. This event is a speculative event."
92  },
93  {
94    "EventName": "ls_mab_alloc.all_allocations",
95    "EventCode": "0x41",
96    "BriefDescription": "All Allocations. Counts when a LS pipe allocates a MAB entry.",
97    "UMask": "0x7f"
98  },
99  {
100    "EventName": "ls_mab_alloc.hardware_prefetcher_allocations",
101    "EventCode": "0x41",
102    "BriefDescription": "Hardware Prefetcher Allocations. Counts when a LS pipe allocates a MAB entry.",
103    "UMask": "0x40"
104  },
105  {
106    "EventName": "ls_mab_alloc.load_store_allocations",
107    "EventCode": "0x41",
108    "BriefDescription": "Load Store Allocations. Counts when a LS pipe allocates a MAB entry.",
109    "UMask": "0x3f"
110  },
111  {
112    "EventName": "ls_mab_alloc.dc_prefetcher",
113    "EventCode": "0x41",
114    "BriefDescription": "LS MAB Allocates by Type. DC prefetcher.",
115    "UMask": "0x08"
116  },
117  {
118    "EventName": "ls_mab_alloc.stores",
119    "EventCode": "0x41",
120    "BriefDescription": "LS MAB Allocates by Type. Stores.",
121    "UMask": "0x02"
122  },
123  {
124    "EventName": "ls_mab_alloc.loads",
125    "EventCode": "0x41",
126    "BriefDescription": "LS MAB Allocates by Type. Loads.",
127    "UMask": "0x01"
128  },
129  {
130    "EventName": "ls_dmnd_fills_from_sys.mem_io_remote",
131    "EventCode": "0x43",
132    "BriefDescription": "Demand Data Cache Fills by Data Source. From DRAM or IO connected in different Node.",
133    "UMask": "0x40"
134  },
135  {
136    "EventName": "ls_dmnd_fills_from_sys.ext_cache_remote",
137    "EventCode": "0x43",
138    "BriefDescription": "Demand Data Cache Fills by Data Source. From CCX Cache in different Node.",
139    "UMask": "0x10"
140  },
141  {
142    "EventName": "ls_dmnd_fills_from_sys.mem_io_local",
143    "EventCode": "0x43",
144    "BriefDescription": "Demand Data Cache Fills by Data Source. From DRAM or IO connected in same node.",
145    "UMask": "0x08"
146  },
147  {
148    "EventName": "ls_dmnd_fills_from_sys.ext_cache_local",
149    "EventCode": "0x43",
150    "BriefDescription": "Demand Data Cache Fills by Data Source. From cache of different CCX in same node.",
151    "UMask": "0x04"
152  },
153  {
154    "EventName": "ls_dmnd_fills_from_sys.int_cache",
155    "EventCode": "0x43",
156    "BriefDescription": "Demand Data Cache Fills by Data Source. From L3 or different L2 in same CCX.",
157    "UMask": "0x02"
158  },
159  {
160    "EventName": "ls_dmnd_fills_from_sys.lcl_l2",
161    "EventCode": "0x43",
162    "BriefDescription": "Demand Data Cache Fills by Data Source. From Local L2 to the core.",
163    "UMask": "0x01"
164  },
165  {
166    "EventName": "ls_any_fills_from_sys.mem_io_remote",
167    "EventCode": "0x44",
168    "BriefDescription": "Any Data Cache Fills by Data Source. From DRAM or IO connected in different Node.",
169    "UMask": "0x40"
170  },
171  {
172    "EventName": "ls_any_fills_from_sys.ext_cache_remote",
173    "EventCode": "0x44",
174    "BriefDescription": "Any Data Cache Fills by Data Source. From CCX Cache in different Node.",
175    "UMask": "0x10"
176  },
177  {
178    "EventName": "ls_any_fills_from_sys.mem_io_local",
179    "EventCode": "0x44",
180    "BriefDescription": "Any Data Cache Fills by Data Source. From DRAM or IO connected in same node.",
181    "UMask": "0x08"
182  },
183  {
184    "EventName": "ls_any_fills_from_sys.ext_cache_local",
185    "EventCode": "0x44",
186    "BriefDescription": "Any Data Cache Fills by Data Source. From cache of different CCX in same node.",
187    "UMask": "0x04"
188  },
189  {
190    "EventName": "ls_any_fills_from_sys.int_cache",
191    "EventCode": "0x44",
192    "BriefDescription": "Any Data Cache Fills by Data Source. From L3 or different L2 in same CCX.",
193    "UMask": "0x02"
194  },
195  {
196    "EventName": "ls_any_fills_from_sys.lcl_l2",
197    "EventCode": "0x44",
198    "BriefDescription": "Any Data Cache Fills by Data Source. From Local L2 to the core.",
199    "UMask": "0x01"
200  },
201  {
202    "EventName": "ls_l1_d_tlb_miss.all",
203    "EventCode": "0x45",
204    "BriefDescription": "All L1 DTLB Misses or Reloads. Use l1_dtlb_misses instead.",
205    "UMask": "0xff"
206  },
207  {
208    "EventName": "ls_l1_d_tlb_miss.tlb_reload_1g_l2_miss",
209    "EventCode": "0x45",
210    "BriefDescription": "L1 DTLB Miss. DTLB reload to a 1G page that also missed in the L2 TLB.",
211    "UMask": "0x80"
212  },
213  {
214    "EventName": "ls_l1_d_tlb_miss.tlb_reload_2m_l2_miss",
215    "EventCode": "0x45",
216    "BriefDescription": "L1 DTLB Miss. DTLB reload to a 2M page that also missed in the L2 TLB.",
217    "UMask": "0x40"
218  },
219  {
220    "EventName": "ls_l1_d_tlb_miss.tlb_reload_coalesced_page_miss",
221    "EventCode": "0x45",
222    "BriefDescription": "L1 DTLB Miss. DTLB reload coalesced page that also missed in the L2 TLB.",
223    "UMask": "0x20"
224  },
225  {
226    "EventName": "ls_l1_d_tlb_miss.tlb_reload_4k_l2_miss",
227    "EventCode": "0x45",
228    "BriefDescription": "L1 DTLB Miss. DTLB reload to a 4K page that missed the L2 TLB.",
229    "UMask": "0x10"
230  },
231  {
232    "EventName": "ls_l1_d_tlb_miss.tlb_reload_1g_l2_hit",
233    "EventCode": "0x45",
234    "BriefDescription": "L1 DTLB Miss. DTLB reload to a 1G page that hit in the L2 TLB.",
235    "UMask": "0x08"
236  },
237  {
238    "EventName": "ls_l1_d_tlb_miss.tlb_reload_2m_l2_hit",
239    "EventCode": "0x45",
240    "BriefDescription": "L1 DTLB Miss. DTLB reload to a 2M page that hit in the L2 TLB.",
241    "UMask": "0x04"
242  },
243  {
244    "EventName": "ls_l1_d_tlb_miss.tlb_reload_coalesced_page_hit",
245    "EventCode": "0x45",
246    "BriefDescription": "L1 DTLB Miss. DTLB reload to a coalesced page that hit in the L2 TLB.",
247    "UMask": "0x02"
248  },
249  {
250    "EventName": "ls_l1_d_tlb_miss.tlb_reload_4k_l2_hit",
251    "EventCode": "0x45",
252    "BriefDescription": "L1 DTLB Miss. DTLB reload to a 4K page that hit in the L2 TLB.",
253    "UMask": "0x01"
254  },
255  {
256    "EventName": "ls_tablewalker.iside",
257    "EventCode": "0x46",
258    "BriefDescription": "Total Page Table Walks on I-side.",
259    "UMask": "0x0c"
260  },
261  {
262    "EventName": "ls_tablewalker.ic_type1",
263    "EventCode": "0x46",
264    "BriefDescription": "Total Page Table Walks IC Type 1.",
265    "UMask": "0x08"
266  },
267  {
268    "EventName": "ls_tablewalker.ic_type0",
269    "EventCode": "0x46",
270    "BriefDescription": "Total Page Table Walks IC Type 0.",
271    "UMask": "0x04"
272  },
273  {
274    "EventName": "ls_tablewalker.dside",
275    "EventCode": "0x46",
276    "BriefDescription": "Total Page Table Walks on D-side.",
277    "UMask": "0x03"
278  },
279  {
280    "EventName": "ls_tablewalker.dc_type1",
281    "EventCode": "0x46",
282    "BriefDescription": "Total Page Table Walks DC Type 1.",
283    "UMask": "0x02"
284  },
285  {
286    "EventName": "ls_tablewalker.dc_type0",
287    "EventCode": "0x46",
288    "BriefDescription": "Total Page Table Walks DC Type 0.",
289    "UMask": "0x01"
290  },
291  {
292    "EventName": "ls_misal_loads.ma4k",
293    "EventCode": "0x47",
294    "BriefDescription": "The number of 4KB misaligned (i.e., page crossing) loads.",
295    "UMask": "0x02"
296  },
297  {
298    "EventName": "ls_misal_loads.ma64",
299    "EventCode": "0x47",
300    "BriefDescription": "The number of 64B misaligned (i.e., cacheline crossing) loads.",
301    "UMask": "0x01"
302  },
303  {
304    "EventName": "ls_pref_instr_disp",
305    "EventCode": "0x4b",
306    "BriefDescription": "Software Prefetch Instructions Dispatched (Speculative).",
307    "UMask": "0xff"
308  },
309  {
310    "EventName": "ls_pref_instr_disp.prefetch_nta",
311    "EventCode": "0x4b",
312    "BriefDescription": "Software Prefetch Instructions Dispatched (Speculative). PrefetchNTA instruction. See docAPM3 PREFETCHlevel.",
313    "UMask": "0x04"
314  },
315  {
316    "EventName": "ls_pref_instr_disp.prefetch_w",
317    "EventCode": "0x4b",
318    "BriefDescription": "Software Prefetch Instructions Dispatched (Speculative). PrefetchW instruction. See docAPM3 PREFETCHW.",
319    "UMask": "0x02"
320  },
321  {
322    "EventName": "ls_pref_instr_disp.prefetch",
323    "EventCode": "0x4b",
324    "BriefDescription": "Software Prefetch Instructions Dispatched (Speculative). PrefetchT0, T1 and T2 instructions. See docAPM3 PREFETCHlevel.",
325    "UMask": "0x01"
326  },
327  {
328    "EventName": "ls_inef_sw_pref.mab_mch_cnt",
329    "EventCode": "0x52",
330    "BriefDescription": "The number of software prefetches that did not fetch data outside of the processor core. Software PREFETCH instruction saw a match on an already-allocated miss request buffer.",
331    "UMask": "0x02"
332  },
333  {
334    "EventName": "ls_inef_sw_pref.data_pipe_sw_pf_dc_hit",
335    "EventCode": "0x52",
336    "BriefDescription": "The number of software prefetches that did not fetch data outside of the processor core. Software PREFETCH instruction saw a DC hit.",
337    "UMask": "0x01"
338  },
339  {
340    "EventName": "ls_sw_pf_dc_fills.mem_io_remote",
341    "EventCode": "0x59",
342    "BriefDescription": "Software Prefetch Data Cache Fills by Data Source. From DRAM or IO connected in different Node.",
343    "UMask": "0x40"
344  },
345  {
346    "EventName": "ls_sw_pf_dc_fills.ext_cache_remote",
347    "EventCode": "0x59",
348    "BriefDescription": "Software Prefetch Data Cache Fills by Data Source. From CCX Cache in different Node.",
349    "UMask": "0x10"
350  },
351  {
352    "EventName": "ls_sw_pf_dc_fills.mem_io_local",
353    "EventCode": "0x59",
354    "BriefDescription": "Software Prefetch Data Cache Fills by Data Source. From DRAM or IO connected in same node.",
355    "UMask": "0x08"
356  },
357  {
358    "EventName": "ls_sw_pf_dc_fills.ext_cache_local",
359    "EventCode": "0x59",
360    "BriefDescription": "Software Prefetch Data Cache Fills by Data Source. From cache of different CCX in same node.",
361    "UMask": "0x04"
362  },
363  {
364    "EventName": "ls_sw_pf_dc_fills.int_cache",
365    "EventCode": "0x59",
366    "BriefDescription": "Software Prefetch Data Cache Fills by Data Source. From L3 or different L2 in same CCX.",
367    "UMask": "0x02"
368  },
369  {
370    "EventName": "ls_sw_pf_dc_fills.lcl_l2",
371    "EventCode": "0x59",
372    "BriefDescription": "Software Prefetch Data Cache Fills by Data Source. From Local L2 to the core.",
373    "UMask": "0x01"
374  },
375  {
376    "EventName": "ls_hw_pf_dc_fills.mem_io_remote",
377    "EventCode": "0x5a",
378    "BriefDescription": "Hardware Prefetch Data Cache Fills by Data Source. From DRAM or IO connected in different Node.",
379    "UMask": "0x40"
380  },
381  {
382    "EventName": "ls_hw_pf_dc_fills.ext_cache_remote",
383    "EventCode": "0x5a",
384    "BriefDescription": "Hardware Prefetch Data Cache Fills by Data Source. From CCX Cache in different Node.",
385    "UMask": "0x10"
386  },
387  {
388    "EventName": "ls_hw_pf_dc_fills.mem_io_local",
389    "EventCode": "0x5a",
390    "BriefDescription": "Hardware Prefetch Data Cache Fills by Data Source. From DRAM or IO connected in same node.",
391    "UMask": "0x08"
392  },
393  {
394    "EventName": "ls_hw_pf_dc_fills.ext_cache_local",
395    "EventCode": "0x5a",
396    "BriefDescription": "Hardware Prefetch Data Cache Fills by Data Source. From cache of different CCX in same node.",
397    "UMask": "0x04"
398  },
399  {
400    "EventName": "ls_hw_pf_dc_fills.int_cache",
401    "EventCode": "0x5a",
402    "BriefDescription": "Hardware Prefetch Data Cache Fills by Data Source. From L3 or different L2 in same CCX.",
403    "UMask": "0x02"
404  },
405  {
406    "EventName": "ls_hw_pf_dc_fills.lcl_l2",
407    "EventCode": "0x5a",
408    "BriefDescription": "Hardware Prefetch Data Cache Fills by Data Source. From Local L2 to the core.",
409    "UMask": "0x01"
410  },
411  {
412    "EventName": "ls_alloc_mab_count",
413    "EventCode": "0x5f",
414    "BriefDescription": "Count of Allocated Mabs",
415    "PublicDescription": "This event counts the in-flight L1 data cache misses (allocated Miss Address Buffers) divided by 4 and rounded down each cycle unless used with the MergeEvent functionality. If the MergeEvent is used, it counts the exact number of outstanding L1 data cache misses. See 2.1.17.3 [Large Increment per Cycle Events]."
416  },
417  {
418    "EventName": "ls_not_halted_cyc",
419    "EventCode": "0x76",
420    "BriefDescription": "Cycles not in Halt."
421  },
422  {
423    "EventName": "ls_tlb_flush.all_tlb_flushes",
424    "EventCode": "0x78",
425    "BriefDescription": "All TLB Flushes. Requires unit mask 0xFF to engage event for counting. Use all_tlbs_flushed instead",
426    "UMask": "0xff"
427  }
428]
429