1LOCAL_DIR := $(GET_LOCAL_DIR)
2
3MODULE := $(LOCAL_DIR)
4
5# can override this in local.mk
6ENABLE_THUMB?=true
7
8# default to the regular arm subarch
9SUBARCH := arm
10
11GLOBAL_DEFINES += \
12	ARM_CPU_$(ARM_CPU)=1
13
14# do set some options based on the cpu core
15HANDLED_CORE := false
16ifeq ($(ARM_CPU),cortex-m0)
17GLOBAL_DEFINES += \
18	ARM_CPU_CORTEX_M0=1 \
19	ARM_ISA_ARMV6M=1 \
20	ARM_WITH_THUMB=1 \
21	USE_BUILTIN_ATOMICS=0
22HANDLED_CORE := true
23ENABLE_THUMB := true
24SUBARCH := arm-m
25endif
26ifeq ($(ARM_CPU),cortex-m0plus)
27GLOBAL_DEFINES += \
28	ARM_CPU_CORTEX_M0_PLUS=1 \
29	ARM_ISA_ARMV6M=1 \
30	ARM_WITH_THUMB=1 \
31	USE_BUILTIN_ATOMICS=0
32HANDLED_CORE := true
33ENABLE_THUMB := true
34SUBARCH := arm-m
35endif
36ifeq ($(ARM_CPU),cortex-m3)
37GLOBAL_DEFINES += \
38	ARM_CPU_CORTEX_M3=1 \
39	ARM_ISA_ARMv7=1 \
40	ARM_ISA_ARMv7M=1 \
41	ARM_WITH_THUMB=1 \
42	ARM_WITH_THUMB2=1
43HANDLED_CORE := true
44ENABLE_THUMB := true
45SUBARCH := arm-m
46endif
47ifeq ($(ARM_CPU),cortex-m4)
48GLOBAL_DEFINES += \
49	ARM_CPU_CORTEX_M4=1 \
50	ARM_ISA_ARMv7=1 \
51	ARM_ISA_ARMv7M=1 \
52	ARM_WITH_THUMB=1 \
53	ARM_WITH_THUMB2=1
54HANDLED_CORE := true
55ENABLE_THUMB := true
56SUBARCH := arm-m
57endif
58ifeq ($(ARM_CPU),cortex-m4f)
59GLOBAL_DEFINES += \
60	ARM_CPU_CORTEX_M4=1 \
61	ARM_CPU_CORTEX_M4F=1 \
62	ARM_ISA_ARMv7=1 \
63	ARM_ISA_ARMv7M=1 \
64	ARM_WITH_THUMB=1 \
65	ARM_WITH_THUMB2=1 \
66	ARM_WITH_VFP=1 \
67	ARM_WITH_VFP_SP_ONLY=1
68HANDLED_CORE := true
69ENABLE_THUMB := true
70SUBARCH := arm-m
71endif
72ifeq ($(ARM_CPU),cortex-m7)
73GLOBAL_DEFINES += \
74	ARM_CPU_CORTEX_M7=1 \
75	ARM_ISA_ARMv7=1 \
76	ARM_ISA_ARMv7M=1 \
77	ARM_WITH_THUMB=1 \
78	ARM_WITH_THUMB2=1 \
79	ARM_WITH_CACHE=1
80HANDLED_CORE := true
81ENABLE_THUMB := true
82SUBARCH := arm-m
83endif
84ifeq ($(ARM_CPU),cortex-m7-fpu-sp-d16)
85GLOBAL_DEFINES += \
86	ARM_CPU_CORTEX_M7=1 \
87	ARM_ISA_ARMv7=1 \
88	ARM_ISA_ARMv7M=1 \
89	ARM_WITH_THUMB=1 \
90	ARM_WITH_THUMB2=1 \
91	ARM_WITH_CACHE=1 \
92	ARM_WITH_VFP=1 \
93	ARM_WITH_VFP_SP_ONLY=1
94HANDLED_CORE := true
95ENABLE_THUMB := true
96SUBARCH := arm-m
97endif
98ifeq ($(ARM_CPU),cortex-a7)
99GLOBAL_DEFINES += \
100	ARM_WITH_CP15=1 \
101	ARCH_HAS_MMU=1 \
102	ARM_ISA_ARMv7=1 \
103	ARM_ISA_ARMv7A=1 \
104	ARM_WITH_VFP=1 \
105	ARM_WITH_NEON=1 \
106	ARM_WITH_THUMB=1 \
107	ARM_WITH_THUMB2=1 \
108	ARM_WITH_CACHE=1 \
109	ARM_WITH_HYP=1
110HANDLED_CORE := true
111endif
112ifeq ($(ARM_CPU),cortex-a15)
113GLOBAL_DEFINES += \
114	ARM_WITH_CP15=1 \
115	ARCH_HAS_MMU=1 \
116	ARM_ISA_ARMv7=1 \
117	ARM_ISA_ARMv7A=1 \
118	ARM_WITH_THUMB=1 \
119	ARM_WITH_THUMB2=1 \
120	ARM_WITH_CACHE=1 \
121	ARM_WITH_L2=1
122ifneq ($(ARM_WITHOUT_VFP_NEON),true)
123GLOBAL_DEFINES += \
124	ARM_WITH_VFP=1 \
125	ARM_WITH_NEON=1
126endif
127HANDLED_CORE := true
128endif
129ifeq ($(ARM_CPU),cortex-a8)
130GLOBAL_DEFINES += \
131	ARM_WITH_CP15=1 \
132	ARCH_HAS_MMU=1 \
133	ARM_ISA_ARMv7=1 \
134	ARM_ISA_ARMv7A=1 \
135	ARM_WITH_VFP=1 \
136	ARM_WITH_NEON=1 \
137	ARM_WITH_THUMB=1 \
138	ARM_WITH_THUMB2=1 \
139	ARM_WITH_CACHE=1 \
140	ARM_WITH_L2=1
141HANDLED_CORE := true
142endif
143ifeq ($(ARM_CPU),cortex-a9)
144GLOBAL_DEFINES += \
145	ARM_WITH_CP15=1 \
146	ARCH_HAS_MMU=1 \
147	ARM_ISA_ARMv7=1 \
148	ARM_ISA_ARMv7A=1 \
149	ARM_WITH_THUMB=1 \
150	ARM_WITH_THUMB2=1 \
151	ARM_WITH_CACHE=1
152HANDLED_CORE := true
153endif
154ifeq ($(ARM_CPU),cortex-a9-neon)
155GLOBAL_DEFINES += \
156	ARM_CPU_CORTEX_A9=1 \
157	ARM_WITH_CP15=1 \
158	ARCH_HAS_MMU=1 \
159	ARM_ISA_ARMv7=1 \
160	ARM_ISA_ARMv7A=1 \
161	ARM_WITH_VFP=1 \
162	ARM_WITH_NEON=1 \
163	ARM_WITH_THUMB=1 \
164	ARM_WITH_THUMB2=1 \
165	ARM_WITH_CACHE=1
166HANDLED_CORE := true
167endif
168ifeq ($(ARM_CPU),arm1136j-s)
169GLOBAL_DEFINES += \
170	ARM_WITH_CP15=1 \
171	ARCH_HAS_MMU=1 \
172	ARM_ISA_ARMv6=1 \
173	ARM_WITH_THUMB=1 \
174	ARM_WITH_CACHE=1 \
175	ARM_CPU_ARM1136=1
176HANDLED_CORE := true
177endif
178ifeq ($(ARM_CPU),arm1176jzf-s)
179GLOBAL_DEFINES += \
180	ARM_WITH_CP15=1 \
181	ARCH_HAS_MMU=1 \
182	ARM_ISA_ARMv6=1 \
183	ARM_WITH_VFP=1 \
184	ARM_WITH_THUMB=1 \
185	ARM_WITH_CACHE=1 \
186	ARM_CPU_ARM1136=1
187HANDLED_CORE := true
188endif
189ifeq ($(ARM_CPU),cortex-r4f)
190GLOBAL_DEFINES += \
191	ARM_CPU_CORTEX_R4F=1 \
192	ARM_ISA_ARMv7=1 \
193	ARM_WITH_VFP=1 \
194	ARM_WITH_THUMB=1
195	ENABLE_THUMB := true
196	HANDLED_CORE := true
197endif
198ifeq ($(ARM_CPU),armemu)
199# flavor of emulated cpu by the armemu project
200GLOBAL_DEFINES += \
201	ARM_WITH_CP15=1 \
202	ARM_ISA_ARMv7=1 \
203	ARM_ISA_ARMv7A=1 \
204	ARM_WITH_CACHE=1
205HANDLED_CORE := true
206ENABLE_THUMB := false # armemu doesn't currently support thumb properly
207endif
208
209ifneq ($(HANDLED_CORE),true)
210$(error $(LOCAL_DIR)/rules.mk doesnt have logic for arm core $(ARM_CPU))
211endif
212
213THUMBCFLAGS :=
214THUMBINTERWORK :=
215ifeq ($(ENABLE_THUMB),true)
216THUMBCFLAGS := -mthumb -D__thumb__
217ifneq ($(SUBARCH),arm-m)
218# Only enable thumb interworking switch if we're compiling in a mixed
219# arm/thumb environment. Also possible this switch is not needed anymore.
220THUMBINTERWORK := -mthumb-interwork
221endif
222endif
223
224GLOBAL_INCLUDES += \
225	$(LOCAL_DIR)/$(SUBARCH)/include
226
227ifeq ($(SUBARCH),arm)
228MODULE_SRCS += \
229	$(LOCAL_DIR)/arm/start.S \
230	$(LOCAL_DIR)/arm/asm.S \
231	$(LOCAL_DIR)/arm/cache-ops.S \
232	$(LOCAL_DIR)/arm/cache.c \
233	$(LOCAL_DIR)/arm/debug.c \
234	$(LOCAL_DIR)/arm/ops.S \
235	$(LOCAL_DIR)/arm/exceptions.S \
236	$(LOCAL_DIR)/arm/faults.c \
237	$(LOCAL_DIR)/arm/fpu.c \
238	$(LOCAL_DIR)/arm/mmu.c \
239	$(LOCAL_DIR)/arm/thread.c
240
241MODULE_ARM_OVERRIDE_SRCS := \
242	$(LOCAL_DIR)/arm/arch.c
243
244GLOBAL_DEFINES += \
245	ARCH_DEFAULT_STACK_SIZE=4096
246
247ARCH_OPTFLAGS := -O2
248WITH_LINKER_GC ?= 1
249
250# use the numeric registers when disassembling code
251ARCH_OBJDUMP_FLAGS := -Mreg-names-raw
252
253# we have a mmu and want the vmm/pmm
254WITH_KERNEL_VM ?= 1
255
256# for arm, have the kernel occupy the entire top 3GB of virtual space,
257# but put the kernel itself at 0x80000000.
258# this leaves 0x40000000 - 0x80000000 open for kernel space to use.
259GLOBAL_DEFINES += \
260    KERNEL_ASPACE_BASE=0x40000000 \
261    KERNEL_ASPACE_SIZE=0xc0000000
262
263KERNEL_BASE ?= 0x80000000
264KERNEL_LOAD_OFFSET ?= 0
265
266GLOBAL_DEFINES += \
267    KERNEL_BASE=$(KERNEL_BASE) \
268    KERNEL_LOAD_OFFSET=$(KERNEL_LOAD_OFFSET)
269
270# if its requested we build with SMP, arm generically supports 4 cpus
271ifeq ($(WITH_SMP),1)
272SMP_MAX_CPUS ?= 4
273SMP_CPU_CLUSTER_SHIFT ?= 8
274SMP_CPU_ID_BITS ?= 24
275
276GLOBAL_DEFINES += \
277    WITH_SMP=1 \
278    SMP_MAX_CPUS=$(SMP_MAX_CPUS) \
279    SMP_CPU_CLUSTER_SHIFT=$(SMP_CPU_CLUSTER_SHIFT) \
280    SMP_CPU_ID_BITS=$(SMP_CPU_ID_BITS)
281
282MODULE_SRCS += \
283	$(LOCAL_DIR)/arm/mp.c
284else
285GLOBAL_DEFINES += \
286    SMP_MAX_CPUS=1
287endif
288
289ifeq (true,$(call TOBOOL,$(WITH_NS_MAPPING)))
290GLOBAL_DEFINES += \
291    WITH_ARCH_MMU_PICK_SPOT=1
292endif
293
294endif
295ifeq ($(SUBARCH),arm-m)
296MODULE_SRCS += \
297	$(LOCAL_DIR)/arm-m/arch.c \
298	$(LOCAL_DIR)/arm-m/cache.c \
299	$(LOCAL_DIR)/arm-m/exceptions.c \
300	$(LOCAL_DIR)/arm-m/start.c \
301	$(LOCAL_DIR)/arm-m/spin_cycles.c \
302	$(LOCAL_DIR)/arm-m/thread.c \
303	$(LOCAL_DIR)/arm-m/vectab.c
304
305# we're building for small binaries
306GLOBAL_DEFINES += \
307	ARM_ONLY_THUMB=1 \
308	ARCH_DEFAULT_STACK_SIZE=1024 \
309	SMP_MAX_CPUS=1
310
311MODULE_DEPS += \
312	arch/arm/arm-m/CMSIS
313
314ARCH_OPTFLAGS := -Os
315WITH_LINKER_GC ?= 1
316endif
317
318# try to find toolchain
319include $(LOCAL_DIR)/toolchain.mk
320TOOLCHAIN_PREFIX := $(ARCH_$(ARCH)_TOOLCHAIN_PREFIX)
321$(info TOOLCHAIN_PREFIX = $(TOOLCHAIN_PREFIX))
322
323ARCH_COMPILEFLAGS += $(ARCH_$(ARCH)_COMPILEFLAGS)
324
325GLOBAL_COMPILEFLAGS += $(THUMBINTERWORK)
326
327# set the max page size to something more reasonable (defaults to 64K or above)
328ARCH_LDFLAGS += -z max-page-size=4096
329
330# find the direct path to libgcc.a for our particular multilib variant
331LIBGCC := $(shell $(TOOLCHAIN_PREFIX)gcc $(GLOBAL_COMPILEFLAGS) $(ARCH_COMPILEFLAGS) $(THUMBCFLAGS) -print-libgcc-file-name)
332#$(info LIBGCC = $(LIBGCC))
333#$(info LIBGCC COMPILEFLAGS = $(GLOBAL_COMPILEFLAGS) $(ARCH_COMPILEFLAGS) $(THUMBCFLAGS))
334
335# make sure some bits were set up
336MEMVARS_SET := 0
337ifneq ($(MEMBASE),)
338MEMVARS_SET := 1
339endif
340ifneq ($(MEMSIZE),)
341MEMVARS_SET := 1
342endif
343ifeq ($(MEMVARS_SET),0)
344$(error missing MEMBASE or MEMSIZE variable, please set in target rules.mk)
345endif
346
347GLOBAL_DEFINES += \
348	MEMBASE=$(MEMBASE) \
349	MEMSIZE=$(MEMSIZE)
350
351# potentially generated files that should be cleaned out with clean make rule
352GENERATED += \
353	$(BUILDDIR)/system-onesegment.ld \
354	$(BUILDDIR)/system-twosegment.ld
355
356# rules for generating the linker scripts
357$(BUILDDIR)/system-onesegment.ld: $(LOCAL_DIR)/system-onesegment.ld $(wildcard arch/*.ld) linkerscript.phony
358	@echo generating $@
359	@$(MKDIR)
360	$(NOECHO)sed "s/%MEMBASE%/$(MEMBASE)/;s/%MEMSIZE%/$(MEMSIZE)/;s/%KERNEL_BASE%/$(KERNEL_BASE)/;s/%KERNEL_LOAD_OFFSET%/$(KERNEL_LOAD_OFFSET)/" < $< > $@.tmp
361	@$(call TESTANDREPLACEFILE,$@.tmp,$@)
362
363$(BUILDDIR)/system-twosegment.ld: $(LOCAL_DIR)/system-twosegment.ld $(wildcard arch/*.ld) linkerscript.phony
364	@echo generating $@
365	@$(MKDIR)
366	$(NOECHO)sed "s/%ROMBASE%/$(ROMBASE)/;s/%MEMBASE%/$(MEMBASE)/;s/%MEMSIZE%/$(MEMSIZE)/" < $< > $@.tmp
367	@$(call TESTANDREPLACEFILE,$@.tmp,$@)
368
369linkerscript.phony:
370.PHONY: linkerscript.phony
371
372# arm specific script to try to guess stack usage
373$(OUTELF).stack: LOCAL_DIR:=$(LOCAL_DIR)
374$(OUTELF).stack: $(OUTELF)
375	$(NOECHO)echo generating stack usage $@
376	$(NOECHO)$(OBJDUMP) $(ARCH_OBJDUMP_FLAGS) -d $< | $(LOCAL_DIR)/stackusage | $(CPPFILT) | sort -n -k 1 -r > $@
377
378EXTRA_BUILDDEPS += $(OUTELF).stack
379GENERATED += $(OUTELF).stack
380
381include make/module.mk
382