1 /****************************************************************************** 2 * Filename: hw_adi_2_refsys_h 3 * Revised: 2015-11-12 13:07:02 +0100 (Thu, 12 Nov 2015) 4 * Revision: 45056 5 * 6 * Copyright (c) 2015, Texas Instruments Incorporated 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions are met: 11 * 12 * 1) Redistributions of source code must retain the above copyright notice, 13 * this list of conditions and the following disclaimer. 14 * 15 * 2) Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 19 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may 20 * be used to endorse or promote products derived from this software without 21 * specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 * 35 ******************************************************************************/ 36 37 #ifndef __HW_ADI_2_REFSYS_H__ 38 #define __HW_ADI_2_REFSYS_H__ 39 40 //***************************************************************************** 41 // 42 // This section defines the register offsets of 43 // ADI_2_REFSYS component 44 // 45 //***************************************************************************** 46 // Internal 47 #define ADI_2_REFSYS_O_REFSYSCTL0 0x00000000 48 49 // Internal 50 #define ADI_2_REFSYS_O_SOCLDOCTL0 0x00000002 51 52 // Internal 53 #define ADI_2_REFSYS_O_SOCLDOCTL1 0x00000003 54 55 // Internal 56 #define ADI_2_REFSYS_O_SOCLDOCTL2 0x00000004 57 58 // Internal 59 #define ADI_2_REFSYS_O_SOCLDOCTL3 0x00000005 60 61 // Internal 62 #define ADI_2_REFSYS_O_SOCLDOCTL4 0x00000006 63 64 // Internal 65 #define ADI_2_REFSYS_O_SOCLDOCTL5 0x00000007 66 67 // HPOSC Control 0 68 #define ADI_2_REFSYS_O_HPOSCCTL0 0x0000000A 69 70 // HPOSC Control 1 71 #define ADI_2_REFSYS_O_HPOSCCTL1 0x0000000B 72 73 // HPOSC Control 2 74 #define ADI_2_REFSYS_O_HPOSCCTL2 0x0000000C 75 76 //***************************************************************************** 77 // 78 // Register: ADI_2_REFSYS_O_REFSYSCTL0 79 // 80 //***************************************************************************** 81 // Field: [4:0] TRIM_IREF 82 // 83 // Internal. Only to be used through TI provided API. 84 #define ADI_2_REFSYS_REFSYSCTL0_TRIM_IREF_W 5 85 #define ADI_2_REFSYS_REFSYSCTL0_TRIM_IREF_M 0x0000001F 86 #define ADI_2_REFSYS_REFSYSCTL0_TRIM_IREF_S 0 87 88 //***************************************************************************** 89 // 90 // Register: ADI_2_REFSYS_O_SOCLDOCTL0 91 // 92 //***************************************************************************** 93 // Field: [7:4] VTRIM_UDIG 94 // 95 // Internal. Only to be used through TI provided API. 96 #define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_UDIG_W 4 97 #define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_UDIG_M 0x000000F0 98 #define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_UDIG_S 4 99 100 // Field: [3:0] VTRIM_BOD 101 // 102 // Internal. Only to be used through TI provided API. 103 #define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_BOD_W 4 104 #define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_BOD_M 0x0000000F 105 #define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_BOD_S 0 106 107 //***************************************************************************** 108 // 109 // Register: ADI_2_REFSYS_O_SOCLDOCTL1 110 // 111 //***************************************************************************** 112 // Field: [7:4] VTRIM_COARSE 113 // 114 // Internal. Only to be used through TI provided API. 115 #define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_COARSE_W 4 116 #define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_COARSE_M 0x000000F0 117 #define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_COARSE_S 4 118 119 // Field: [3:0] VTRIM_DIG 120 // 121 // Internal. Only to be used through TI provided API. 122 #define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_DIG_W 4 123 #define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_DIG_M 0x0000000F 124 #define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_DIG_S 0 125 126 //***************************************************************************** 127 // 128 // Register: ADI_2_REFSYS_O_SOCLDOCTL2 129 // 130 //***************************************************************************** 131 // Field: [2:0] VTRIM_DELTA 132 // 133 // Internal. Only to be used through TI provided API. 134 #define ADI_2_REFSYS_SOCLDOCTL2_VTRIM_DELTA_W 3 135 #define ADI_2_REFSYS_SOCLDOCTL2_VTRIM_DELTA_M 0x00000007 136 #define ADI_2_REFSYS_SOCLDOCTL2_VTRIM_DELTA_S 0 137 138 //***************************************************************************** 139 // 140 // Register: ADI_2_REFSYS_O_SOCLDOCTL3 141 // 142 //***************************************************************************** 143 // Field: [7:6] ITRIM_DIGLDO_LOAD 144 // 145 // Internal. Only to be used through TI provided API. 146 #define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_LOAD_W 2 147 #define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_LOAD_M 0x000000C0 148 #define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_LOAD_S 6 149 150 // Field: [5:3] ITRIM_DIGLDO 151 // 152 // Internal. Only to be used through TI provided API. 153 // ENUMs: 154 // BIAS_120P Internal. Only to be used through TI provided API. 155 // BIAS_100P Internal. Only to be used through TI provided API. 156 // BIAS_80P Internal. Only to be used through TI provided API. 157 // BIAS_60P Internal. Only to be used through TI provided API. 158 #define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_W 3 159 #define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_M 0x00000038 160 #define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_S 3 161 #define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_BIAS_120P 0x00000038 162 #define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_BIAS_100P 0x00000028 163 #define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_BIAS_80P 0x00000018 164 #define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_BIAS_60P 0x00000000 165 166 // Field: [2:0] ITRIM_UDIGLDO 167 // 168 // Internal. Only to be used through TI provided API. 169 #define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_UDIGLDO_W 3 170 #define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_UDIGLDO_M 0x00000007 171 #define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_UDIGLDO_S 0 172 173 //***************************************************************************** 174 // 175 // Register: ADI_2_REFSYS_O_SOCLDOCTL4 176 // 177 //***************************************************************************** 178 // Field: [6:5] UDIG_ITEST_EN 179 // 180 // Internal. Only to be used through TI provided API. 181 #define ADI_2_REFSYS_SOCLDOCTL4_UDIG_ITEST_EN_W 2 182 #define ADI_2_REFSYS_SOCLDOCTL4_UDIG_ITEST_EN_M 0x00000060 183 #define ADI_2_REFSYS_SOCLDOCTL4_UDIG_ITEST_EN_S 5 184 185 // Field: [4:2] DIG_ITEST_EN 186 // 187 // Internal. Only to be used through TI provided API. 188 #define ADI_2_REFSYS_SOCLDOCTL4_DIG_ITEST_EN_W 3 189 #define ADI_2_REFSYS_SOCLDOCTL4_DIG_ITEST_EN_M 0x0000001C 190 #define ADI_2_REFSYS_SOCLDOCTL4_DIG_ITEST_EN_S 2 191 192 // Field: [1] BIAS_DIS 193 // 194 // Internal. Only to be used through TI provided API. 195 #define ADI_2_REFSYS_SOCLDOCTL4_BIAS_DIS 0x00000002 196 #define ADI_2_REFSYS_SOCLDOCTL4_BIAS_DIS_BITN 1 197 #define ADI_2_REFSYS_SOCLDOCTL4_BIAS_DIS_M 0x00000002 198 #define ADI_2_REFSYS_SOCLDOCTL4_BIAS_DIS_S 1 199 200 // Field: [0] UDIG_LDO_EN 201 // 202 // Internal. Only to be used through TI provided API. 203 // ENUMs: 204 // EN Internal. Only to be used through TI provided API. 205 // DIS Internal. Only to be used through TI provided API. 206 #define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN 0x00000001 207 #define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN_BITN 0 208 #define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN_M 0x00000001 209 #define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN_S 0 210 #define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN_EN 0x00000001 211 #define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN_DIS 0x00000000 212 213 //***************************************************************************** 214 // 215 // Register: ADI_2_REFSYS_O_SOCLDOCTL5 216 // 217 //***************************************************************************** 218 // Field: [3] IMON_ITEST_EN 219 // 220 // Internal. Only to be used through TI provided API. 221 #define ADI_2_REFSYS_SOCLDOCTL5_IMON_ITEST_EN 0x00000008 222 #define ADI_2_REFSYS_SOCLDOCTL5_IMON_ITEST_EN_BITN 3 223 #define ADI_2_REFSYS_SOCLDOCTL5_IMON_ITEST_EN_M 0x00000008 224 #define ADI_2_REFSYS_SOCLDOCTL5_IMON_ITEST_EN_S 3 225 226 // Field: [2:0] TESTSEL 227 // 228 // Internal. Only to be used through TI provided API. 229 // ENUMs: 230 // VDD_AON Internal. Only to be used through TI provided API. 231 // VREF_AMP Internal. Only to be used through TI provided API. 232 // ITEST Internal. Only to be used through TI provided API. 233 // NC Internal. Only to be used through TI provided API. 234 #define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_W 3 235 #define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_M 0x00000007 236 #define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_S 0 237 #define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_VDD_AON 0x00000004 238 #define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_VREF_AMP 0x00000002 239 #define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_ITEST 0x00000001 240 #define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_NC 0x00000000 241 242 //***************************************************************************** 243 // 244 // Register: ADI_2_REFSYS_O_HPOSCCTL0 245 // 246 //***************************************************************************** 247 // Field: [7] FILTER_EN 248 // 249 // Enable HPOSC Bias filter 250 // 251 // Enable 1 kHz low pass filter in the HPOSC bias. 252 #define ADI_2_REFSYS_HPOSCCTL0_FILTER_EN 0x00000080 253 #define ADI_2_REFSYS_HPOSCCTL0_FILTER_EN_BITN 7 254 #define ADI_2_REFSYS_HPOSCCTL0_FILTER_EN_M 0x00000080 255 #define ADI_2_REFSYS_HPOSCCTL0_FILTER_EN_S 7 256 257 // Field: [6:5] BIAS_RECHARGE_DLY 258 // 259 // When HPOSCCTL2.BIAS_HOLD_MODE_EN = 1, low-power sample and hold mode for 260 // HPOSC bias is enabled. This field sets the recharge delay for this sample 261 // and hold mode by counting number of 48 MHz clock edges. 262 // ENUMs: 263 // MIN_DLY_X8 5461 us 264 // MIN_DLY_X4 2731 us 265 // MIN_DLY_X2 1365 us 266 // MIN_DLY_X1 682 us 267 #define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_W 2 268 #define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_M 0x00000060 269 #define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_S 5 270 #define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_MIN_DLY_X8 0x00000060 271 #define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_MIN_DLY_X4 0x00000040 272 #define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_MIN_DLY_X2 0x00000020 273 #define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_MIN_DLY_X1 0x00000000 274 275 // Field: [4:3] TUNE_CAP 276 // 277 // Cap to shift HPOSC center frequency. 278 // ENUMs: 279 // SHIFT_M108 -108 ppm shift 280 // SHIFT_M70 -70 ppm shift 281 // SHIFT_M35 -35 ppm shift 282 // SHIFT_0 0 ppm shift 283 #define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_W 2 284 #define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_M 0x00000018 285 #define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_S 3 286 #define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT_M108 0x00000018 287 #define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT_M70 0x00000010 288 #define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT_M35 0x00000008 289 #define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT_0 0x00000000 290 291 // Field: [2:1] SERIES_CAP 292 // 293 // Cap to set HPOSC into proper mode. Set 1 time in factory. 294 // 295 // 00: 1.4 pF Cs1/Cs2 296 // 01: 1.1 pF Cs1/Cs2 297 // 10: 2.1 pF Cs1/Cs2 298 // 11: 1.8 pF Cs1/Cs2 299 #define ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP_W 2 300 #define ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP_M 0x00000006 301 #define ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP_S 1 302 303 // Field: [0] DIV3_BYPASS 304 // 305 // Bypass for divide by 3 in divider. 306 // ENUMs: 307 // HPOSC_2520MHZ Divide by 17.5 for use with 2520 MHz HPOSC 308 // HPOSC_840MHZ Divide by 52.5 for use with 840 MHz HPOSC 309 #define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS 0x00000001 310 #define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_BITN 0 311 #define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_M 0x00000001 312 #define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_S 0 313 #define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_HPOSC_2520MHZ 0x00000001 314 #define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_HPOSC_840MHZ 0x00000000 315 316 //***************************************************************************** 317 // 318 // Register: ADI_2_REFSYS_O_HPOSCCTL1 319 // 320 //***************************************************************************** 321 // Field: [5] BIAS_DIS 322 // 323 // Disable dummy bias current. 324 // 325 // 0: Dummy bias current on (Default) 326 // 1: Dummy bias current off 327 #define ADI_2_REFSYS_HPOSCCTL1_BIAS_DIS 0x00000020 328 #define ADI_2_REFSYS_HPOSCCTL1_BIAS_DIS_BITN 5 329 #define ADI_2_REFSYS_HPOSCCTL1_BIAS_DIS_M 0x00000020 330 #define ADI_2_REFSYS_HPOSCCTL1_BIAS_DIS_S 5 331 332 // Field: [4] PWRDET_EN 333 // 334 // Enable signal for HPOSC power detector. 335 // 336 // 0: HPOSC power detector disabled. 337 // 1: HPOSC power detector enabled. 338 // 339 // When enabled, Power detector VMAX and VMIN referred to in 340 // HPOSCCTL2.ATEST_SEL can be selected. 341 #define ADI_2_REFSYS_HPOSCCTL1_PWRDET_EN 0x00000010 342 #define ADI_2_REFSYS_HPOSCCTL1_PWRDET_EN_BITN 4 343 #define ADI_2_REFSYS_HPOSCCTL1_PWRDET_EN_M 0x00000010 344 #define ADI_2_REFSYS_HPOSCCTL1_PWRDET_EN_S 4 345 346 // Field: [3:0] BIAS_RES_SET 347 // 348 // Adjust the HPOSC bias resistor to set the current in the HPOSC core. Two's 349 // complement encoding. 350 // 351 // 0x8: Highest resistance, lowest current 352 // 0x0: Default 353 // 0x7: Lowest resistance, maximum current 354 #define ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET_W 4 355 #define ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET_M 0x0000000F 356 #define ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET_S 0 357 358 //***************************************************************************** 359 // 360 // Register: ADI_2_REFSYS_O_HPOSCCTL2 361 // 362 //***************************************************************************** 363 // Field: [7] BIAS_HOLD_MODE_EN 364 // 365 // Enable signal for bias sample and hold mode. Should give some power savings 366 // at expense of increased phase noise or spurs. 367 // 368 // 0: Disabled hold mode 369 // 1: Enabled hold mode 370 #define ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN 0x00000080 371 #define ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN_BITN 7 372 #define ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN_M 0x00000080 373 #define ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN_S 7 374 375 // Field: [6] TESTMUX_EN 376 // 377 // Enable signal for HPOSC test mux. 378 // 379 // 0: HPOSC test mux disabled. 380 // 1: HPOSC test mux enabled. 381 #define ADI_2_REFSYS_HPOSCCTL2_TESTMUX_EN 0x00000040 382 #define ADI_2_REFSYS_HPOSCCTL2_TESTMUX_EN_BITN 6 383 #define ADI_2_REFSYS_HPOSCCTL2_TESTMUX_EN_M 0x00000040 384 #define ADI_2_REFSYS_HPOSCCTL2_TESTMUX_EN_S 6 385 386 // Field: [5:4] ATEST_SEL 387 // 388 // ATEST Selection Control 389 // 390 // 00: Output test bias current 391 // 01: Former connction for HPOSC BGAP. Not currently used. 392 // 10: Power detector VMAX 393 // 11: Power detector VMIN 394 // 395 // Must also set TESTMUX_EN high to get test outputs. 396 #define ADI_2_REFSYS_HPOSCCTL2_ATEST_SEL_W 2 397 #define ADI_2_REFSYS_HPOSCCTL2_ATEST_SEL_M 0x00000030 398 #define ADI_2_REFSYS_HPOSCCTL2_ATEST_SEL_S 4 399 400 // Field: [3:0] CURRMIRR_RATIO 401 // 402 // Set current mirror ratio in HPOSC. Controls amount of current flowing in 403 // HPOSC oscillator core. May need to increase from nominal if nominal setting 404 // does not result in oscillation. Two's complement encoding. 405 // 406 // 0x8: Minimum current (~0 uA) 407 // 0x9: 50 uA 408 // 0x0: 400 uA 409 // 0x7: Maximum current (~750 uA) 410 #define ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_W 4 411 #define ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_M 0x0000000F 412 #define ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_S 0 413 414 415 #endif // __ADI_2_REFSYS__ 416