1 /****************************************************************************** 2 * Filename: hw_aux_anaif_h 3 * Revised: 2015-11-12 13:07:02 +0100 (Thu, 12 Nov 2015) 4 * Revision: 45056 5 * 6 * Copyright (c) 2015, Texas Instruments Incorporated 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions are met: 11 * 12 * 1) Redistributions of source code must retain the above copyright notice, 13 * this list of conditions and the following disclaimer. 14 * 15 * 2) Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 19 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may 20 * be used to endorse or promote products derived from this software without 21 * specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 * 35 ******************************************************************************/ 36 37 #ifndef __HW_AUX_ANAIF_H__ 38 #define __HW_AUX_ANAIF_H__ 39 40 //***************************************************************************** 41 // 42 // This section defines the register offsets of 43 // AUX_ANAIF component 44 // 45 //***************************************************************************** 46 // ADC Control 47 #define AUX_ANAIF_O_ADCCTL 0x00000010 48 49 // ADC FIFO Status 50 #define AUX_ANAIF_O_ADCFIFOSTAT 0x00000014 51 52 // ADC FIFO 53 #define AUX_ANAIF_O_ADCFIFO 0x00000018 54 55 // ADC Trigger 56 #define AUX_ANAIF_O_ADCTRIG 0x0000001C 57 58 // Current Source Control 59 #define AUX_ANAIF_O_ISRCCTL 0x00000020 60 61 //***************************************************************************** 62 // 63 // Register: AUX_ANAIF_O_ADCCTL 64 // 65 //***************************************************************************** 66 // Field: [13] START_POL 67 // 68 // Selected active edge for start event / Selected polarity for start event 69 // ENUMs: 70 // FALL Start on falling edge of event 71 // RISE Start on rising edge of event 72 #define AUX_ANAIF_ADCCTL_START_POL 0x00002000 73 #define AUX_ANAIF_ADCCTL_START_POL_BITN 13 74 #define AUX_ANAIF_ADCCTL_START_POL_M 0x00002000 75 #define AUX_ANAIF_ADCCTL_START_POL_S 13 76 #define AUX_ANAIF_ADCCTL_START_POL_FALL 0x00002000 77 #define AUX_ANAIF_ADCCTL_START_POL_RISE 0x00000000 78 79 // Field: [12:8] START_SRC 80 // 81 // Selected source for ADC conversion start event. The start source selected by 82 // this field is OR'ed with any trigger coming from writes to ADCTRIG.START. If 83 // it is desired to only trigger ADC conversions by writes to ADCTRIG.START one 84 // should select NO_EVENT<n> here 85 // ENUMs: 86 // ADC_IRQ Selects ADC_IRQ as start signal 87 // MCU_EV Selects MCU_EV as start signal 88 // ACLK_REF Selects ACLK_REF as start signal 89 // AUXIO15 Selects AUXIO15 as start signal 90 // AUXIO14 Selects AUXIO14 as start signal 91 // AUXIO13 Selects AUXIO13 as start signal 92 // AUXIO12 Selects AUXIO12 as start signal 93 // AUXIO11 Selects AUXIO11 as start signal 94 // AUXIO10 Selects AUXIO10 as start signal 95 // AUXIO9 Selects AUXIO9 as start signal 96 // AUXIO8 Selects AUXIO8 as start signal 97 // AUXIO7 Selects AUXIO7 as start signal 98 // AUXIO6 Selects AUXIO6 as start signal 99 // AUXIO5 Selects AUXIO5 as start signal 100 // AUXIO4 Selects AUXIO4 as start signal 101 // AUXIO3 Selects AUXIO3 as start signal 102 // AUXIO2 Selects AUXIO2 as start signal 103 // AUXIO1 Selects AUXIO1 as start signal 104 // AUXIO0 Selects AUXIO0 as start signal 105 // AON_PROG_WU Selects AON_PROG_WU as start signal 106 // AON_SW Selects AON_SW as start signal 107 // NO_EVENT1 No event selected 108 // NO_EVENT0 No event selected 109 // RESERVED1 Reserved do not use 110 // RESERVED0 Reserved do not use 111 // SMPH_AUTOTAKE_DONE Selects SMPH_AUTOTAKE_DONE as start signal 112 // TIMER1_EV Selects TIMER1_EV as start signal 113 // TIMER0_EV Selects TIMER0_EV as start signal 114 // TDC_DONE Selects TDC_DONE as start signal 115 // AUX_COMPB Selects AUX_COMPB as start signal 116 // AUX_COMPA Selects AUX_COMPA as start signal 117 // RTC_CH2_EV Selects RTC_CH2_EV as start signal 118 #define AUX_ANAIF_ADCCTL_START_SRC_W 5 119 #define AUX_ANAIF_ADCCTL_START_SRC_M 0x00001F00 120 #define AUX_ANAIF_ADCCTL_START_SRC_S 8 121 #define AUX_ANAIF_ADCCTL_START_SRC_ADC_IRQ 0x00001F00 122 #define AUX_ANAIF_ADCCTL_START_SRC_MCU_EV 0x00001E00 123 #define AUX_ANAIF_ADCCTL_START_SRC_ACLK_REF 0x00001D00 124 #define AUX_ANAIF_ADCCTL_START_SRC_AUXIO15 0x00001C00 125 #define AUX_ANAIF_ADCCTL_START_SRC_AUXIO14 0x00001B00 126 #define AUX_ANAIF_ADCCTL_START_SRC_AUXIO13 0x00001A00 127 #define AUX_ANAIF_ADCCTL_START_SRC_AUXIO12 0x00001900 128 #define AUX_ANAIF_ADCCTL_START_SRC_AUXIO11 0x00001800 129 #define AUX_ANAIF_ADCCTL_START_SRC_AUXIO10 0x00001700 130 #define AUX_ANAIF_ADCCTL_START_SRC_AUXIO9 0x00001600 131 #define AUX_ANAIF_ADCCTL_START_SRC_AUXIO8 0x00001500 132 #define AUX_ANAIF_ADCCTL_START_SRC_AUXIO7 0x00001400 133 #define AUX_ANAIF_ADCCTL_START_SRC_AUXIO6 0x00001300 134 #define AUX_ANAIF_ADCCTL_START_SRC_AUXIO5 0x00001200 135 #define AUX_ANAIF_ADCCTL_START_SRC_AUXIO4 0x00001100 136 #define AUX_ANAIF_ADCCTL_START_SRC_AUXIO3 0x00001000 137 #define AUX_ANAIF_ADCCTL_START_SRC_AUXIO2 0x00000F00 138 #define AUX_ANAIF_ADCCTL_START_SRC_AUXIO1 0x00000E00 139 #define AUX_ANAIF_ADCCTL_START_SRC_AUXIO0 0x00000D00 140 #define AUX_ANAIF_ADCCTL_START_SRC_AON_PROG_WU 0x00000C00 141 #define AUX_ANAIF_ADCCTL_START_SRC_AON_SW 0x00000B00 142 #define AUX_ANAIF_ADCCTL_START_SRC_NO_EVENT1 0x00000A00 143 #define AUX_ANAIF_ADCCTL_START_SRC_NO_EVENT0 0x00000900 144 #define AUX_ANAIF_ADCCTL_START_SRC_RESERVED1 0x00000800 145 #define AUX_ANAIF_ADCCTL_START_SRC_RESERVED0 0x00000700 146 #define AUX_ANAIF_ADCCTL_START_SRC_SMPH_AUTOTAKE_DONE 0x00000600 147 #define AUX_ANAIF_ADCCTL_START_SRC_TIMER1_EV 0x00000500 148 #define AUX_ANAIF_ADCCTL_START_SRC_TIMER0_EV 0x00000400 149 #define AUX_ANAIF_ADCCTL_START_SRC_TDC_DONE 0x00000300 150 #define AUX_ANAIF_ADCCTL_START_SRC_AUX_COMPB 0x00000200 151 #define AUX_ANAIF_ADCCTL_START_SRC_AUX_COMPA 0x00000100 152 #define AUX_ANAIF_ADCCTL_START_SRC_RTC_CH2_EV 0x00000000 153 154 // Field: [1:0] CMD 155 // 156 // ADC interface control command 157 // ENUMs: 158 // FLUSH ADC FIFO flush. Note that CMD needs to be set to 159 // 'EN' again for FIFO to be functional after a 160 // flush. A flush takes two clock periods on the 161 // AUX clock to finish. 162 // EN ADC interface enabled 163 // DIS ADC interface disabled 164 #define AUX_ANAIF_ADCCTL_CMD_W 2 165 #define AUX_ANAIF_ADCCTL_CMD_M 0x00000003 166 #define AUX_ANAIF_ADCCTL_CMD_S 0 167 #define AUX_ANAIF_ADCCTL_CMD_FLUSH 0x00000003 168 #define AUX_ANAIF_ADCCTL_CMD_EN 0x00000001 169 #define AUX_ANAIF_ADCCTL_CMD_DIS 0x00000000 170 171 //***************************************************************************** 172 // 173 // Register: AUX_ANAIF_O_ADCFIFOSTAT 174 // 175 //***************************************************************************** 176 // Field: [4] OVERFLOW 177 // 178 // FIFO overflow flag. 179 // 180 // 0: FIFO has not overflowed. 181 // 1: FIFO has overflowed, this flag is sticky until FIFO is flushed. 182 #define AUX_ANAIF_ADCFIFOSTAT_OVERFLOW 0x00000010 183 #define AUX_ANAIF_ADCFIFOSTAT_OVERFLOW_BITN 4 184 #define AUX_ANAIF_ADCFIFOSTAT_OVERFLOW_M 0x00000010 185 #define AUX_ANAIF_ADCFIFOSTAT_OVERFLOW_S 4 186 187 // Field: [3] UNDERFLOW 188 // 189 // FIFO underflow flag. 190 // 191 // 0: FIFO has not underflowed 192 // 1: FIFO has underflowed, this flag is sticky until the FIFO is flushed 193 #define AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW 0x00000008 194 #define AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW_BITN 3 195 #define AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW_M 0x00000008 196 #define AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW_S 3 197 198 // Field: [2] FULL 199 // 200 // FIFO full flag. 201 // 202 // 0: FIFO is not full, i.e. there is less than 4 samples in the FIFO. 203 // 1: FIFO is full, i.e. there are 4 samples in the FIFO 204 #define AUX_ANAIF_ADCFIFOSTAT_FULL 0x00000004 205 #define AUX_ANAIF_ADCFIFOSTAT_FULL_BITN 2 206 #define AUX_ANAIF_ADCFIFOSTAT_FULL_M 0x00000004 207 #define AUX_ANAIF_ADCFIFOSTAT_FULL_S 2 208 209 // Field: [1] ALMOST_FULL 210 // 211 // FIFO almost full flag. 212 // 213 // 0: There is less than 3 samples in the FIFO, or the FIFO is full in which 214 // case the FULL flag is asserted 215 // 1: There are 3 samples in the FIFO, i.e. there is room for one more sample 216 #define AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL 0x00000002 217 #define AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL_BITN 1 218 #define AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL_M 0x00000002 219 #define AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL_S 1 220 221 // Field: [0] EMPTY 222 // 223 // FIFO empty flag. 224 // 225 // 0: FIFO contains one or more samples 226 // 1: FIFO is empty 227 #define AUX_ANAIF_ADCFIFOSTAT_EMPTY 0x00000001 228 #define AUX_ANAIF_ADCFIFOSTAT_EMPTY_BITN 0 229 #define AUX_ANAIF_ADCFIFOSTAT_EMPTY_M 0x00000001 230 #define AUX_ANAIF_ADCFIFOSTAT_EMPTY_S 0 231 232 //***************************************************************************** 233 // 234 // Register: AUX_ANAIF_O_ADCFIFO 235 // 236 //***************************************************************************** 237 // Field: [11:0] DATA 238 // 239 // FIFO is popped when read. Data is pushed into FIFO when written. Writing is 240 // intended for debugging/code development purposes 241 #define AUX_ANAIF_ADCFIFO_DATA_W 12 242 #define AUX_ANAIF_ADCFIFO_DATA_M 0x00000FFF 243 #define AUX_ANAIF_ADCFIFO_DATA_S 0 244 245 //***************************************************************************** 246 // 247 // Register: AUX_ANAIF_O_ADCTRIG 248 // 249 //***************************************************************************** 250 // Field: [0] START 251 // 252 // Writing to this register will trigger an ADC conversion given that 253 // ADCCTL.START_SRC is set to NO_EVENT0 or NO_EVENT1. If other setting is used 254 // in ADCCTL.START_SRC behavior can be unpredictable 255 #define AUX_ANAIF_ADCTRIG_START 0x00000001 256 #define AUX_ANAIF_ADCTRIG_START_BITN 0 257 #define AUX_ANAIF_ADCTRIG_START_M 0x00000001 258 #define AUX_ANAIF_ADCTRIG_START_S 0 259 260 //***************************************************************************** 261 // 262 // Register: AUX_ANAIF_O_ISRCCTL 263 // 264 //***************************************************************************** 265 // Field: [0] RESET_N 266 // 267 // Current source control 268 // 269 // 0: Current source is clamped 270 // 1: Current source is active/charging 271 #define AUX_ANAIF_ISRCCTL_RESET_N 0x00000001 272 #define AUX_ANAIF_ISRCCTL_RESET_N_BITN 0 273 #define AUX_ANAIF_ISRCCTL_RESET_N_M 0x00000001 274 #define AUX_ANAIF_ISRCCTL_RESET_N_S 0 275 276 277 #endif // __AUX_ANAIF__ 278