1 /****************************************************************************** 2 * Filename: hw_aux_timer_h 3 * Revised: 2015-11-12 13:07:02 +0100 (Thu, 12 Nov 2015) 4 * Revision: 45056 5 * 6 * Copyright (c) 2015, Texas Instruments Incorporated 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions are met: 11 * 12 * 1) Redistributions of source code must retain the above copyright notice, 13 * this list of conditions and the following disclaimer. 14 * 15 * 2) Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 19 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may 20 * be used to endorse or promote products derived from this software without 21 * specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 * 35 ******************************************************************************/ 36 37 #ifndef __HW_AUX_TIMER_H__ 38 #define __HW_AUX_TIMER_H__ 39 40 //***************************************************************************** 41 // 42 // This section defines the register offsets of 43 // AUX_TIMER component 44 // 45 //***************************************************************************** 46 // Timer 0 Configuration 47 #define AUX_TIMER_O_T0CFG 0x00000000 48 49 // Timer 1 Configuration 50 #define AUX_TIMER_O_T1CFG 0x00000004 51 52 // Timer 0 Control 53 #define AUX_TIMER_O_T0CTL 0x00000008 54 55 // Timer 0 Target 56 #define AUX_TIMER_O_T0TARGET 0x0000000C 57 58 // Timer 1 Target 59 #define AUX_TIMER_O_T1TARGET 0x00000010 60 61 // Timer 1 Control 62 #define AUX_TIMER_O_T1CTL 0x00000014 63 64 //***************************************************************************** 65 // 66 // Register: AUX_TIMER_O_T0CFG 67 // 68 //***************************************************************************** 69 // Field: [13] TICK_SRC_POL 70 // 71 // Source count polarity for timer 0 72 // ENUMs: 73 // FALL Count on falling edges of TICK_SRC 74 // RISE Count on rising edges of TICK_SRC 75 #define AUX_TIMER_T0CFG_TICK_SRC_POL 0x00002000 76 #define AUX_TIMER_T0CFG_TICK_SRC_POL_BITN 13 77 #define AUX_TIMER_T0CFG_TICK_SRC_POL_M 0x00002000 78 #define AUX_TIMER_T0CFG_TICK_SRC_POL_S 13 79 #define AUX_TIMER_T0CFG_TICK_SRC_POL_FALL 0x00002000 80 #define AUX_TIMER_T0CFG_TICK_SRC_POL_RISE 0x00000000 81 82 // Field: [12:8] TICK_SRC 83 // 84 // Selected tick source for timer 0 85 // ENUMs: 86 // ADC_IRQ Selects ADC_IRQ 87 // MCU_EVENT Selects MCU_EV 88 // ACLK_REF Selects ACLK_REF 89 // AUXIO15 Selects AUXIO15 90 // AUXIO14 Selects AUXIO14 91 // AUXIO13 Selects AUXIO13 92 // AUXIO12 Selects AUXIO12 93 // AUXIO11 Selects AUXIO11 94 // AUXIO10 Selects AUXIO10 95 // AUXIO9 Selects AUXIO9 96 // AUXIO8 Selects AUXIO8 97 // AUXIO7 Selects AUXIO7 98 // AUXIO6 Selects AUXIO6 99 // AUXIO5 Selects AUXIO5 100 // AUXIO4 Selects AUXIO4 101 // AUXIO3 Selects AUXIO3 102 // AUXIO2 Selects AUXIO2 103 // AUXIO1 Selects AUXIO1 104 // AUXIO0 Selects AUXIO0 105 // AON_PROG_WU Selects AON_PROG_WU 106 // AON_SW Selects AON_SW 107 // OBSMUX1 Selects OBSMUX1 108 // OBSMUX0 Selects OBSMUX0 109 // RTC_4KHZ Selects RTC_4KHZ 110 // ADC_DONE Selects ADC_DONE 111 // SMPH_AUTOTAKE_DONE Selects SMPH_AUTOTAKE_DONE 112 // TIMER1_EV Selects TIMER1_EV 113 // TDC_DONE Selects TDC_DONE 114 // AUX_COMPB Selects AUX_COMPB 115 // AUX_COMPA Selects AUX_COMPA 116 // RTC_CH2_EV Selects RTC_CH2_EV 117 #define AUX_TIMER_T0CFG_TICK_SRC_W 5 118 #define AUX_TIMER_T0CFG_TICK_SRC_M 0x00001F00 119 #define AUX_TIMER_T0CFG_TICK_SRC_S 8 120 #define AUX_TIMER_T0CFG_TICK_SRC_ADC_IRQ 0x00001F00 121 #define AUX_TIMER_T0CFG_TICK_SRC_MCU_EVENT 0x00001E00 122 #define AUX_TIMER_T0CFG_TICK_SRC_ACLK_REF 0x00001D00 123 #define AUX_TIMER_T0CFG_TICK_SRC_AUXIO15 0x00001C00 124 #define AUX_TIMER_T0CFG_TICK_SRC_AUXIO14 0x00001B00 125 #define AUX_TIMER_T0CFG_TICK_SRC_AUXIO13 0x00001A00 126 #define AUX_TIMER_T0CFG_TICK_SRC_AUXIO12 0x00001900 127 #define AUX_TIMER_T0CFG_TICK_SRC_AUXIO11 0x00001800 128 #define AUX_TIMER_T0CFG_TICK_SRC_AUXIO10 0x00001700 129 #define AUX_TIMER_T0CFG_TICK_SRC_AUXIO9 0x00001600 130 #define AUX_TIMER_T0CFG_TICK_SRC_AUXIO8 0x00001500 131 #define AUX_TIMER_T0CFG_TICK_SRC_AUXIO7 0x00001400 132 #define AUX_TIMER_T0CFG_TICK_SRC_AUXIO6 0x00001300 133 #define AUX_TIMER_T0CFG_TICK_SRC_AUXIO5 0x00001200 134 #define AUX_TIMER_T0CFG_TICK_SRC_AUXIO4 0x00001100 135 #define AUX_TIMER_T0CFG_TICK_SRC_AUXIO3 0x00001000 136 #define AUX_TIMER_T0CFG_TICK_SRC_AUXIO2 0x00000F00 137 #define AUX_TIMER_T0CFG_TICK_SRC_AUXIO1 0x00000E00 138 #define AUX_TIMER_T0CFG_TICK_SRC_AUXIO0 0x00000D00 139 #define AUX_TIMER_T0CFG_TICK_SRC_AON_PROG_WU 0x00000C00 140 #define AUX_TIMER_T0CFG_TICK_SRC_AON_SW 0x00000B00 141 #define AUX_TIMER_T0CFG_TICK_SRC_OBSMUX1 0x00000A00 142 #define AUX_TIMER_T0CFG_TICK_SRC_OBSMUX0 0x00000900 143 #define AUX_TIMER_T0CFG_TICK_SRC_RTC_4KHZ 0x00000800 144 #define AUX_TIMER_T0CFG_TICK_SRC_ADC_DONE 0x00000700 145 #define AUX_TIMER_T0CFG_TICK_SRC_SMPH_AUTOTAKE_DONE 0x00000600 146 #define AUX_TIMER_T0CFG_TICK_SRC_TIMER1_EV 0x00000500 147 #define AUX_TIMER_T0CFG_TICK_SRC_TDC_DONE 0x00000300 148 #define AUX_TIMER_T0CFG_TICK_SRC_AUX_COMPB 0x00000200 149 #define AUX_TIMER_T0CFG_TICK_SRC_AUX_COMPA 0x00000100 150 #define AUX_TIMER_T0CFG_TICK_SRC_RTC_CH2_EV 0x00000000 151 152 // Field: [7:4] PRE 153 // 154 // Prescaler division ratio is 2^PRE 155 #define AUX_TIMER_T0CFG_PRE_W 4 156 #define AUX_TIMER_T0CFG_PRE_M 0x000000F0 157 #define AUX_TIMER_T0CFG_PRE_S 4 158 159 // Field: [1] MODE 160 // 161 // Timer 0 mode 162 // ENUMs: 163 // TICK Timer 0 counter increments only on edges of the 164 // event set by TICK_SRC. The events are divided 165 // by the PRE setting. 166 // CLK Timer 0 increments on every 2^PRE edges of AUX 167 // clock 168 #define AUX_TIMER_T0CFG_MODE 0x00000002 169 #define AUX_TIMER_T0CFG_MODE_BITN 1 170 #define AUX_TIMER_T0CFG_MODE_M 0x00000002 171 #define AUX_TIMER_T0CFG_MODE_S 1 172 #define AUX_TIMER_T0CFG_MODE_TICK 0x00000002 173 #define AUX_TIMER_T0CFG_MODE_CLK 0x00000000 174 175 // Field: [0] RELOAD 176 // 177 // Timer 0 reload setting 178 // ENUMs: 179 // CONT Timer is automatically restarted when target is 180 // reached 181 // MAN Timer has to be restarted manually 182 #define AUX_TIMER_T0CFG_RELOAD 0x00000001 183 #define AUX_TIMER_T0CFG_RELOAD_BITN 0 184 #define AUX_TIMER_T0CFG_RELOAD_M 0x00000001 185 #define AUX_TIMER_T0CFG_RELOAD_S 0 186 #define AUX_TIMER_T0CFG_RELOAD_CONT 0x00000001 187 #define AUX_TIMER_T0CFG_RELOAD_MAN 0x00000000 188 189 //***************************************************************************** 190 // 191 // Register: AUX_TIMER_O_T1CFG 192 // 193 //***************************************************************************** 194 // Field: [13] TICK_SRC_POL 195 // 196 // Source count polarity for timer 1 197 // ENUMs: 198 // FALL Count on falling edges of TICK_SRC 199 // RISE Count on rising edges of TICK_SRC 200 #define AUX_TIMER_T1CFG_TICK_SRC_POL 0x00002000 201 #define AUX_TIMER_T1CFG_TICK_SRC_POL_BITN 13 202 #define AUX_TIMER_T1CFG_TICK_SRC_POL_M 0x00002000 203 #define AUX_TIMER_T1CFG_TICK_SRC_POL_S 13 204 #define AUX_TIMER_T1CFG_TICK_SRC_POL_FALL 0x00002000 205 #define AUX_TIMER_T1CFG_TICK_SRC_POL_RISE 0x00000000 206 207 // Field: [12:8] TICK_SRC 208 // 209 // Selected tick source for timer 1 210 // ENUMs: 211 // ADC_IRQ Selects ADC_IRQ 212 // MCU_EVENT Selects MCU_EV 213 // ACLK_REF Selects ACLK_REF 214 // AUXIO15 Selects AUXIO15 215 // AUXIO14 Selects AUXIO14 216 // AUXIO13 Selects AUXIO13 217 // AUXIO12 Selects AUXIO12 218 // AUXIO11 Selects AUXIO11 219 // AUXIO10 Selects AUXIO10 220 // AUXIO9 Selects AUXIO9 221 // AUXIO8 Selects AUXIO8 222 // AUXIO7 Selects AUXIO7 223 // AUXIO6 Selects AUXIO6 224 // AUXIO5 Selects AUXIO5 225 // AUXIO4 Selects AUXIO4 226 // AUXIO3 Selects AUXIO3 227 // AUXIO2 Selects AUXIO2 228 // AUXIO1 Selects AUXIO1 229 // AUXIO0 Selects AUXIO0 230 // AON_PROG_WU Selects AON_PROG_WU 231 // AON_SW Selects AON_SW 232 // OBSMUX1 Selects OBSMUX1 233 // OBSMUX0 Selects OBSMUX0 234 // RTC_4KHZ Selects RTC_4KHZ 235 // ADC_DONE Selects ADC_DONE 236 // SMPH_AUTOTAKE_DONE Selects SMPH_AUTOTAKE_DONE 237 // TIMER0_EV Selects TIMER0_EV 238 // TDC_DONE Selects TDC_DONE 239 // AUX_COMPB Selects AUX_COMPB 240 // AUX_COMPA Selects AUX_COMPA 241 // RTC_CH2_EV Selects RTC_CH2_EV 242 #define AUX_TIMER_T1CFG_TICK_SRC_W 5 243 #define AUX_TIMER_T1CFG_TICK_SRC_M 0x00001F00 244 #define AUX_TIMER_T1CFG_TICK_SRC_S 8 245 #define AUX_TIMER_T1CFG_TICK_SRC_ADC_IRQ 0x00001F00 246 #define AUX_TIMER_T1CFG_TICK_SRC_MCU_EVENT 0x00001E00 247 #define AUX_TIMER_T1CFG_TICK_SRC_ACLK_REF 0x00001D00 248 #define AUX_TIMER_T1CFG_TICK_SRC_AUXIO15 0x00001C00 249 #define AUX_TIMER_T1CFG_TICK_SRC_AUXIO14 0x00001B00 250 #define AUX_TIMER_T1CFG_TICK_SRC_AUXIO13 0x00001A00 251 #define AUX_TIMER_T1CFG_TICK_SRC_AUXIO12 0x00001900 252 #define AUX_TIMER_T1CFG_TICK_SRC_AUXIO11 0x00001800 253 #define AUX_TIMER_T1CFG_TICK_SRC_AUXIO10 0x00001700 254 #define AUX_TIMER_T1CFG_TICK_SRC_AUXIO9 0x00001600 255 #define AUX_TIMER_T1CFG_TICK_SRC_AUXIO8 0x00001500 256 #define AUX_TIMER_T1CFG_TICK_SRC_AUXIO7 0x00001400 257 #define AUX_TIMER_T1CFG_TICK_SRC_AUXIO6 0x00001300 258 #define AUX_TIMER_T1CFG_TICK_SRC_AUXIO5 0x00001200 259 #define AUX_TIMER_T1CFG_TICK_SRC_AUXIO4 0x00001100 260 #define AUX_TIMER_T1CFG_TICK_SRC_AUXIO3 0x00001000 261 #define AUX_TIMER_T1CFG_TICK_SRC_AUXIO2 0x00000F00 262 #define AUX_TIMER_T1CFG_TICK_SRC_AUXIO1 0x00000E00 263 #define AUX_TIMER_T1CFG_TICK_SRC_AUXIO0 0x00000D00 264 #define AUX_TIMER_T1CFG_TICK_SRC_AON_PROG_WU 0x00000C00 265 #define AUX_TIMER_T1CFG_TICK_SRC_AON_SW 0x00000B00 266 #define AUX_TIMER_T1CFG_TICK_SRC_OBSMUX1 0x00000A00 267 #define AUX_TIMER_T1CFG_TICK_SRC_OBSMUX0 0x00000900 268 #define AUX_TIMER_T1CFG_TICK_SRC_RTC_4KHZ 0x00000800 269 #define AUX_TIMER_T1CFG_TICK_SRC_ADC_DONE 0x00000700 270 #define AUX_TIMER_T1CFG_TICK_SRC_SMPH_AUTOTAKE_DONE 0x00000600 271 #define AUX_TIMER_T1CFG_TICK_SRC_TIMER0_EV 0x00000400 272 #define AUX_TIMER_T1CFG_TICK_SRC_TDC_DONE 0x00000300 273 #define AUX_TIMER_T1CFG_TICK_SRC_AUX_COMPB 0x00000200 274 #define AUX_TIMER_T1CFG_TICK_SRC_AUX_COMPA 0x00000100 275 #define AUX_TIMER_T1CFG_TICK_SRC_RTC_CH2_EV 0x00000000 276 277 // Field: [7:4] PRE 278 // 279 // Prescaler division ratio is 2^PRE 280 #define AUX_TIMER_T1CFG_PRE_W 4 281 #define AUX_TIMER_T1CFG_PRE_M 0x000000F0 282 #define AUX_TIMER_T1CFG_PRE_S 4 283 284 // Field: [1] MODE 285 // 286 // Timer 1 mode 287 // ENUMs: 288 // TICK Timer 1 counter increments only on edges of the 289 // event set by TICK_SRC. The events are divided 290 // by the PRE setting. 291 // CLK Timer 1 increments on every 2^PRE edges of AUX 292 // clock 293 #define AUX_TIMER_T1CFG_MODE 0x00000002 294 #define AUX_TIMER_T1CFG_MODE_BITN 1 295 #define AUX_TIMER_T1CFG_MODE_M 0x00000002 296 #define AUX_TIMER_T1CFG_MODE_S 1 297 #define AUX_TIMER_T1CFG_MODE_TICK 0x00000002 298 #define AUX_TIMER_T1CFG_MODE_CLK 0x00000000 299 300 // Field: [0] RELOAD 301 // 302 // Timer 1 reload setting 303 // ENUMs: 304 // CONT Timer is automatically restarted when target is 305 // reached 306 // MAN Timer has to be restarted manually 307 #define AUX_TIMER_T1CFG_RELOAD 0x00000001 308 #define AUX_TIMER_T1CFG_RELOAD_BITN 0 309 #define AUX_TIMER_T1CFG_RELOAD_M 0x00000001 310 #define AUX_TIMER_T1CFG_RELOAD_S 0 311 #define AUX_TIMER_T1CFG_RELOAD_CONT 0x00000001 312 #define AUX_TIMER_T1CFG_RELOAD_MAN 0x00000000 313 314 //***************************************************************************** 315 // 316 // Register: AUX_TIMER_O_T0CTL 317 // 318 //***************************************************************************** 319 // Field: [0] EN 320 // 321 // Timer 0 run enable control. The counter restarts when enabling the timer. If 322 // T0CFG.RELOAD = 0, the timer is automatically disabled when reaching 323 // T0TARGET.VALUE 324 // 325 // 0: Disable timer 0 326 // 1: Enable timer 0 327 #define AUX_TIMER_T0CTL_EN 0x00000001 328 #define AUX_TIMER_T0CTL_EN_BITN 0 329 #define AUX_TIMER_T0CTL_EN_M 0x00000001 330 #define AUX_TIMER_T0CTL_EN_S 0 331 332 //***************************************************************************** 333 // 334 // Register: AUX_TIMER_O_T0TARGET 335 // 336 //***************************************************************************** 337 // Field: [15:0] VALUE 338 // 339 // Timer 0 counts from 0 to VALUE. Then gives an event and restarts if 340 // configured to do to so in the T0CFG.RELOAD setting. If VALUE is changed 341 // while timer 0 is running so that the count becomes higher than VALUE timer 0 342 // will also restart if configured to do so. 343 // 344 // If T0CFG.MODE=0,no prescaler is used, and VALUE equals 1, the TIMER0_EV 345 // event line will be always set 346 #define AUX_TIMER_T0TARGET_VALUE_W 16 347 #define AUX_TIMER_T0TARGET_VALUE_M 0x0000FFFF 348 #define AUX_TIMER_T0TARGET_VALUE_S 0 349 350 //***************************************************************************** 351 // 352 // Register: AUX_TIMER_O_T1TARGET 353 // 354 //***************************************************************************** 355 // Field: [7:0] VALUE 356 // 357 // Timer 1 counts from 0 to VALUE. Then gives an event and restarts if 358 // configured to do to so in the T1CFG.RELOAD setting. If VALUE is changed 359 // while timer 1 is running so that the count becomes higher than VALUE timer 1 360 // will also restart if configured to do so. 361 // 362 // If T1CFG.MODE=0,no prescaler is used, and VALUE equals 1, the TIMER1_EV 363 // event line will be always set 364 #define AUX_TIMER_T1TARGET_VALUE_W 8 365 #define AUX_TIMER_T1TARGET_VALUE_M 0x000000FF 366 #define AUX_TIMER_T1TARGET_VALUE_S 0 367 368 //***************************************************************************** 369 // 370 // Register: AUX_TIMER_O_T1CTL 371 // 372 //***************************************************************************** 373 // Field: [0] EN 374 // 375 // Timer 1 run enable control. The counter restarts when enabling the timer. If 376 // T1CFG.RELOAD = 0, the timer is automatically disabled when reaching 377 // T1TARGET.VALUE 378 // 379 // 0: Disable timer 1 380 // 1: Enable timer 1 381 #define AUX_TIMER_T1CTL_EN 0x00000001 382 #define AUX_TIMER_T1CTL_EN_BITN 0 383 #define AUX_TIMER_T1CTL_EN_M 0x00000001 384 #define AUX_TIMER_T1CTL_EN_S 0 385 386 387 #endif // __AUX_TIMER__ 388