1 /****************************************************************************** 2 * Filename: hw_ccfg_h 3 * Revised: 2015-11-12 13:07:02 +0100 (Thu, 12 Nov 2015) 4 * Revision: 45056 5 * 6 * Copyright (c) 2015, Texas Instruments Incorporated 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions are met: 11 * 12 * 1) Redistributions of source code must retain the above copyright notice, 13 * this list of conditions and the following disclaimer. 14 * 15 * 2) Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 19 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may 20 * be used to endorse or promote products derived from this software without 21 * specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 * 35 ******************************************************************************/ 36 37 #ifndef __HW_CCFG_H__ 38 #define __HW_CCFG_H__ 39 40 //***************************************************************************** 41 // 42 // This section defines the register offsets of 43 // CCFG component 44 // 45 //***************************************************************************** 46 // Extern LF clock configuration 47 #define CCFG_O_EXT_LF_CLK 0x00000FA8 48 49 // Mode Configuration 1 50 #define CCFG_O_MODE_CONF_1 0x00000FAC 51 52 // CCFG Size and Disable Flags 53 #define CCFG_O_SIZE_AND_DIS_FLAGS 0x00000FB0 54 55 // Mode Configuration 0 56 #define CCFG_O_MODE_CONF 0x00000FB4 57 58 // Voltage Load 0 59 #define CCFG_O_VOLT_LOAD_0 0x00000FB8 60 61 // Voltage Load 1 62 #define CCFG_O_VOLT_LOAD_1 0x00000FBC 63 64 // Real Time Clock Offset 65 #define CCFG_O_RTC_OFFSET 0x00000FC0 66 67 // Frequency Offset 68 #define CCFG_O_FREQ_OFFSET 0x00000FC4 69 70 // IEEE MAC Address 0 71 #define CCFG_O_IEEE_MAC_0 0x00000FC8 72 73 // IEEE MAC Address 1 74 #define CCFG_O_IEEE_MAC_1 0x00000FCC 75 76 // IEEE BLE Address 0 77 #define CCFG_O_IEEE_BLE_0 0x00000FD0 78 79 // IEEE BLE Address 1 80 #define CCFG_O_IEEE_BLE_1 0x00000FD4 81 82 // Bootloader Configuration 83 #define CCFG_O_BL_CONFIG 0x00000FD8 84 85 // Erase Configuration 86 #define CCFG_O_ERASE_CONF 0x00000FDC 87 88 // TI Options 89 #define CCFG_O_CCFG_TI_OPTIONS 0x00000FE0 90 91 // Test Access Points Enable 0 92 #define CCFG_O_CCFG_TAP_DAP_0 0x00000FE4 93 94 // Test Access Points Enable 1 95 #define CCFG_O_CCFG_TAP_DAP_1 0x00000FE8 96 97 // Image Valid 98 #define CCFG_O_IMAGE_VALID_CONF 0x00000FEC 99 100 // Protect Sectors 0-31 101 #define CCFG_O_CCFG_PROT_31_0 0x00000FF0 102 103 // Protect Sectors 32-63 104 #define CCFG_O_CCFG_PROT_63_32 0x00000FF4 105 106 // Protect Sectors 64-95 107 #define CCFG_O_CCFG_PROT_95_64 0x00000FF8 108 109 // Protect Sectors 96-127 110 #define CCFG_O_CCFG_PROT_127_96 0x00000FFC 111 112 //***************************************************************************** 113 // 114 // Register: CCFG_O_EXT_LF_CLK 115 // 116 //***************************************************************************** 117 // Field: [31:24] DIO 118 // 119 // Unsigned integer, selecting the DIO to supply external 32kHz clock as 120 // SCLK_LF when MODE_CONF.SCLK_LF_OPTION is set to EXTERNAL. The selected DIO 121 // will be marked as reserved by the pin driver (TI-RTOS environment) and hence 122 // not selectable for other usage. 123 #define CCFG_EXT_LF_CLK_DIO_W 8 124 #define CCFG_EXT_LF_CLK_DIO_M 0xFF000000 125 #define CCFG_EXT_LF_CLK_DIO_S 24 126 127 // Field: [23:0] RTC_INCREMENT 128 // 129 // Unsigned integer, defining the input frequency of the external clock and is 130 // written to AON_RTC:SUBSECINC.VALUEINC. Defined as follows: 131 // EXT_LF_CLK.RTC_INCREMENT = 2^38/InputClockFrequency in Hertz (e.g.: 132 // RTC_INCREMENT=0x800000 for InputClockFrequency=32768 Hz) 133 #define CCFG_EXT_LF_CLK_RTC_INCREMENT_W 24 134 #define CCFG_EXT_LF_CLK_RTC_INCREMENT_M 0x00FFFFFF 135 #define CCFG_EXT_LF_CLK_RTC_INCREMENT_S 0 136 137 //***************************************************************************** 138 // 139 // Register: CCFG_O_MODE_CONF_1 140 // 141 //***************************************************************************** 142 // Field: [23:20] ALT_DCDC_VMIN 143 // 144 // Minimum voltage for when DC/DC should be used if alternate DC/DC setting is 145 // enabled (SIZE_AND_DIS_FLAGS.DIS_ALT_DCDC_SETTING=0). 146 // Voltage = (28 + ALT_DCDC_VMIN) / 16. 147 // 0: 1.75V 148 // 1: 1.8125V 149 // ... 150 // 14: 2.625V 151 // 15: 2.6875V 152 // 153 // NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must 154 // be called regularly to apply this field (handled automatically if using TI 155 // RTOS!). 156 #define CCFG_MODE_CONF_1_ALT_DCDC_VMIN_W 4 157 #define CCFG_MODE_CONF_1_ALT_DCDC_VMIN_M 0x00F00000 158 #define CCFG_MODE_CONF_1_ALT_DCDC_VMIN_S 20 159 160 // Field: [19] ALT_DCDC_DITHER_EN 161 // 162 // Enable DC/DC dithering if alternate DC/DC setting is enabled 163 // (SIZE_AND_DIS_FLAGS.DIS_ALT_DCDC_SETTING=0). 164 // 0: Dither disable 165 // 1: Dither enable 166 #define CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN 0x00080000 167 #define CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_BITN 19 168 #define CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_M 0x00080000 169 #define CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_S 19 170 171 // Field: [18:16] ALT_DCDC_IPEAK 172 // 173 // Inductor peak current if alternate DC/DC setting is enabled 174 // (SIZE_AND_DIS_FLAGS.DIS_ALT_DCDC_SETTING=0). Assuming 10uH external 175 // inductor! 176 // Peak current = 31 + ( 4 * ALT_DCDC_IPEAK ) : 177 // 0: 31mA (min) 178 // ... 179 // 4: 47mA 180 // ... 181 // 7: 59mA (max) 182 #define CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_W 3 183 #define CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_M 0x00070000 184 #define CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_S 16 185 186 // Field: [15:12] DELTA_IBIAS_INIT 187 // 188 // Signed delta value for IBIAS_INIT. Delta value only applies if 189 // SIZE_AND_DIS_FLAGS.DIS_XOSC_OVR=0. 190 // See FCFG1:AMPCOMP_CTRL1.IBIAS_INIT 191 #define CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_W 4 192 #define CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_M 0x0000F000 193 #define CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_S 12 194 195 // Field: [11:8] DELTA_IBIAS_OFFSET 196 // 197 // Signed delta value for IBIAS_OFFSET. Delta value only applies if 198 // SIZE_AND_DIS_FLAGS.DIS_XOSC_OVR=0. 199 // See FCFG1:AMPCOMP_CTRL1.IBIAS_OFFSET 200 #define CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_W 4 201 #define CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_M 0x00000F00 202 #define CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_S 8 203 204 // Field: [7:0] XOSC_MAX_START 205 // 206 // Unsigned value of maximum XOSC startup time (worst case) in units of 100us. 207 // Value only applies if SIZE_AND_DIS_FLAGS.DIS_XOSC_OVR=0. 208 #define CCFG_MODE_CONF_1_XOSC_MAX_START_W 8 209 #define CCFG_MODE_CONF_1_XOSC_MAX_START_M 0x000000FF 210 #define CCFG_MODE_CONF_1_XOSC_MAX_START_S 0 211 212 //***************************************************************************** 213 // 214 // Register: CCFG_O_SIZE_AND_DIS_FLAGS 215 // 216 //***************************************************************************** 217 // Field: [31:16] SIZE_OF_CCFG 218 // 219 // Total size of CCFG in bytes. 220 #define CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_W 16 221 #define CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_M 0xFFFF0000 222 #define CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_S 16 223 224 // Field: [15:3] DISABLE_FLAGS 225 // 226 // Reserved for future use. Software should not rely on the value of a 227 // reserved. Writing any other value than the reset/default value may result in 228 // undefined behavior. 229 #define CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_W 13 230 #define CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_M 0x0000FFF8 231 #define CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_S 3 232 233 // Field: [2] DIS_GPRAM 234 // 235 // Disable GPRAM (or use the 8K VIMS RAM as CACHE RAM). 236 // 0: GPRAM is enabled and hence CACHE disabled. 237 // 1: GPRAM is disabled and instead CACHE is enabled (default). 238 // Notes: 239 // - Disabling CACHE will reduce CPU execution speed (up to 60%). 240 // - GPRAM is 8 K-bytes in size and located at 0x11000000-0x11001FFF if 241 // enabled. 242 // See: 243 // VIMS:CTL.MODE 244 #define CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM 0x00000004 245 #define CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_BITN 2 246 #define CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_M 0x00000004 247 #define CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_S 2 248 249 // Field: [1] DIS_ALT_DCDC_SETTING 250 // 251 // Disable alternate DC/DC settings. 252 // 0: Enable alternate DC/DC settings. 253 // 1: Disable alternate DC/DC settings. 254 // See: 255 // MODE_CONF_1.ALT_DCDC_VMIN 256 // MODE_CONF_1.ALT_DCDC_DITHER_EN 257 // MODE_CONF_1.ALT_DCDC_IPEAK 258 // 259 // NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must 260 // be called regularly to apply this field (handled automatically if using TI 261 // RTOS!). 262 #define CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING 0x00000002 263 #define CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_BITN 1 264 #define CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_M 0x00000002 265 #define CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_S 1 266 267 // Field: [0] DIS_XOSC_OVR 268 // 269 // Disable XOSC override functionality. 270 // 0: Enable XOSC override functionality. 271 // 1: Disable XOSC override functionality. 272 // See: 273 // MODE_CONF_1.DELTA_IBIAS_INIT 274 // MODE_CONF_1.DELTA_IBIAS_OFFSET 275 // MODE_CONF_1.XOSC_MAX_START 276 #define CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR 0x00000001 277 #define CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_BITN 0 278 #define CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_M 0x00000001 279 #define CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_S 0 280 281 //***************************************************************************** 282 // 283 // Register: CCFG_O_MODE_CONF 284 // 285 //***************************************************************************** 286 // Field: [31:28] VDDR_TRIM_SLEEP_DELTA 287 // 288 // Signed delta value to apply to the 289 // VDDR_TRIM_SLEEP target, minus one. See FCFG1:VOLT_TRIM.VDDR_TRIM_SLEEP_H. 290 // 0x8 (-8) : Delta = -7 291 // ... 292 // 0xF (-1) : Delta = 0 293 // 0x0 (0) : Delta = +1 294 // ... 295 // 0x7 (7) : Delta = +8 296 #define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_W 4 297 #define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_M 0xF0000000 298 #define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_S 28 299 300 // Field: [27] DCDC_RECHARGE 301 // 302 // DC/DC during recharge in powerdown. 303 // 0: Use the DC/DC during recharge in powerdown. 304 // 1: Do not use the DC/DC during recharge in powerdown (default). 305 // 306 // NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must 307 // be called regularly to apply this field (handled automatically if using TI 308 // RTOS!). 309 #define CCFG_MODE_CONF_DCDC_RECHARGE 0x08000000 310 #define CCFG_MODE_CONF_DCDC_RECHARGE_BITN 27 311 #define CCFG_MODE_CONF_DCDC_RECHARGE_M 0x08000000 312 #define CCFG_MODE_CONF_DCDC_RECHARGE_S 27 313 314 // Field: [26] DCDC_ACTIVE 315 // 316 // DC/DC in active mode. 317 // 0: Use the DC/DC during active mode. 318 // 1: Do not use the DC/DC during active mode (default). 319 // 320 // NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must 321 // be called regularly to apply this field (handled automatically if using TI 322 // RTOS!). 323 #define CCFG_MODE_CONF_DCDC_ACTIVE 0x04000000 324 #define CCFG_MODE_CONF_DCDC_ACTIVE_BITN 26 325 #define CCFG_MODE_CONF_DCDC_ACTIVE_M 0x04000000 326 #define CCFG_MODE_CONF_DCDC_ACTIVE_S 26 327 328 // Field: [25] VDDR_EXT_LOAD 329 // 330 // Reserved for future use. Software should not rely on the value of a 331 // reserved. Writing any other value than the reset/default value may result in 332 // undefined behavior. 333 #define CCFG_MODE_CONF_VDDR_EXT_LOAD 0x02000000 334 #define CCFG_MODE_CONF_VDDR_EXT_LOAD_BITN 25 335 #define CCFG_MODE_CONF_VDDR_EXT_LOAD_M 0x02000000 336 #define CCFG_MODE_CONF_VDDR_EXT_LOAD_S 25 337 338 // Field: [24] VDDS_BOD_LEVEL 339 // 340 // VDDS BOD level. 341 // 0: VDDS BOD level is 2.0V (necessary for external load mode, or for maximum 342 // PA output power on CC13xx). 343 // 1: VDDS BOD level is 1.8V (or 1.65V for external regulator mode) (default). 344 #define CCFG_MODE_CONF_VDDS_BOD_LEVEL 0x01000000 345 #define CCFG_MODE_CONF_VDDS_BOD_LEVEL_BITN 24 346 #define CCFG_MODE_CONF_VDDS_BOD_LEVEL_M 0x01000000 347 #define CCFG_MODE_CONF_VDDS_BOD_LEVEL_S 24 348 349 // Field: [23:22] SCLK_LF_OPTION 350 // 351 // Select source for SCLK_LF. 352 // 0: XOSC_HF_DLF. 353 // 31.25kHz clock derived from 24MHz XOSC. Requires user to reconfigure RTC 354 // tick speed for correct timing. Standby power mode is not supported when 355 // using this clock source. 356 // 1: EXTERNAL. 357 // External low frequency clock on DIO defined in EXT_LF_CLK.DIO. The RTC tick 358 // speed AON_RTC.SUBSECINC is updated to EXT_LF_CLK.RTC_INCREMENT. External 359 // clock must always be running when the chip is in standby for VDDR recharge 360 // timing. 361 // 2: XOSC_LF. 362 // 32.768kHz low frequency XOSC 363 // 3: RCOSC_LF. 364 // Low frequency RCOSC (default) 365 #define CCFG_MODE_CONF_SCLK_LF_OPTION_W 2 366 #define CCFG_MODE_CONF_SCLK_LF_OPTION_M 0x00C00000 367 #define CCFG_MODE_CONF_SCLK_LF_OPTION_S 22 368 369 // Field: [21] VDDR_TRIM_SLEEP_TC 370 // 371 // 0x1: VDDR_TRIM_SLEEP_DELTA is not temperature compensated 372 // 0x0: RTOS/driver temperature compensates VDDR_TRIM_SLEEP_DELTA every time 373 // standby mode is entered. This improves low-temperature RCOSC_LF frequency 374 // stability in standby mode. 375 // 376 // When temperature compensation is performed, the delta is calculates this 377 // way: 378 // Delta = max (delta, min(8, floor(62-temp)/8)) 379 // Here, delta is given by VDDR_TRIM_SLEEP_DELTA, and temp is the current 380 // temperature in degrees C. 381 #define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC 0x00200000 382 #define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_BITN 21 383 #define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_M 0x00200000 384 #define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_S 21 385 386 // Field: [20] RTC_COMP 387 // 388 // Reserved for future use. Software should not rely on the value of a 389 // reserved. Writing any other value than the reset/default value may result in 390 // undefined behavior. 391 #define CCFG_MODE_CONF_RTC_COMP 0x00100000 392 #define CCFG_MODE_CONF_RTC_COMP_BITN 20 393 #define CCFG_MODE_CONF_RTC_COMP_M 0x00100000 394 #define CCFG_MODE_CONF_RTC_COMP_S 20 395 396 // Field: [19:18] XOSC_FREQ 397 // 398 // Reserved for future use. Software should not rely on the value of a 399 // reserved. Writing any other value than the reset/default value may result in 400 // undefined behavior. 401 #define CCFG_MODE_CONF_XOSC_FREQ_W 2 402 #define CCFG_MODE_CONF_XOSC_FREQ_M 0x000C0000 403 #define CCFG_MODE_CONF_XOSC_FREQ_S 18 404 405 // Field: [17] XOSC_CAP_MOD 406 // 407 // Enable modification (delta) to XOSC cap-array. Value specified in 408 // XOSC_CAPARRAY_DELTA. 409 // 0: Apply cap-array delta 410 // 1: Do not apply cap-array delta (default) 411 #define CCFG_MODE_CONF_XOSC_CAP_MOD 0x00020000 412 #define CCFG_MODE_CONF_XOSC_CAP_MOD_BITN 17 413 #define CCFG_MODE_CONF_XOSC_CAP_MOD_M 0x00020000 414 #define CCFG_MODE_CONF_XOSC_CAP_MOD_S 17 415 416 // Field: [16] HF_COMP 417 // 418 // Reserved for future use. Software should not rely on the value of a 419 // reserved. Writing any other value than the reset/default value may result in 420 // undefined behavior. 421 #define CCFG_MODE_CONF_HF_COMP 0x00010000 422 #define CCFG_MODE_CONF_HF_COMP_BITN 16 423 #define CCFG_MODE_CONF_HF_COMP_M 0x00010000 424 #define CCFG_MODE_CONF_HF_COMP_S 16 425 426 // Field: [15:8] XOSC_CAPARRAY_DELTA 427 // 428 // Signed 8-bit value, directly modifying trimmed XOSC cap-array step value. 429 // Enabled by XOSC_CAP_MOD. 430 #define CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_W 8 431 #define CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_M 0x0000FF00 432 #define CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_S 8 433 434 // Field: [7:0] VDDR_CAP 435 // 436 // Unsigned 8-bit integer, representing the minimum decoupling capacitance 437 // (worst case) on VDDR, in units of 100nF. This should take into account 438 // capacitor tolerance and voltage dependent capacitance variation. This bit 439 // affects the recharge period calculation when going into powerdown or 440 // standby. 441 // 442 // NOTE! If using the following functions this field must be configured (used 443 // by TI RTOS): 444 // SysCtrlSetRechargeBeforePowerDown() SysCtrlAdjustRechargeAfterPowerDown() 445 #define CCFG_MODE_CONF_VDDR_CAP_W 8 446 #define CCFG_MODE_CONF_VDDR_CAP_M 0x000000FF 447 #define CCFG_MODE_CONF_VDDR_CAP_S 0 448 449 //***************************************************************************** 450 // 451 // Register: CCFG_O_VOLT_LOAD_0 452 // 453 //***************************************************************************** 454 // Field: [31:24] VDDR_EXT_TP45 455 // 456 // Reserved for future use. Software should not rely on the value of a 457 // reserved. Writing any other value than the reset/default value may result in 458 // undefined behavior. 459 #define CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_W 8 460 #define CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_M 0xFF000000 461 #define CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_S 24 462 463 // Field: [23:16] VDDR_EXT_TP25 464 // 465 // Reserved for future use. Software should not rely on the value of a 466 // reserved. Writing any other value than the reset/default value may result in 467 // undefined behavior. 468 #define CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_W 8 469 #define CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_M 0x00FF0000 470 #define CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_S 16 471 472 // Field: [15:8] VDDR_EXT_TP5 473 // 474 // Reserved for future use. Software should not rely on the value of a 475 // reserved. Writing any other value than the reset/default value may result in 476 // undefined behavior. 477 #define CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_W 8 478 #define CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_M 0x0000FF00 479 #define CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_S 8 480 481 // Field: [7:0] VDDR_EXT_TM15 482 // 483 // Reserved for future use. Software should not rely on the value of a 484 // reserved. Writing any other value than the reset/default value may result in 485 // undefined behavior. 486 #define CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_W 8 487 #define CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_M 0x000000FF 488 #define CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_S 0 489 490 //***************************************************************************** 491 // 492 // Register: CCFG_O_VOLT_LOAD_1 493 // 494 //***************************************************************************** 495 // Field: [31:24] VDDR_EXT_TP125 496 // 497 // Reserved for future use. Software should not rely on the value of a 498 // reserved. Writing any other value than the reset/default value may result in 499 // undefined behavior. 500 #define CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_W 8 501 #define CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_M 0xFF000000 502 #define CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_S 24 503 504 // Field: [23:16] VDDR_EXT_TP105 505 // 506 // Reserved for future use. Software should not rely on the value of a 507 // reserved. Writing any other value than the reset/default value may result in 508 // undefined behavior. 509 #define CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_W 8 510 #define CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_M 0x00FF0000 511 #define CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_S 16 512 513 // Field: [15:8] VDDR_EXT_TP85 514 // 515 // Reserved for future use. Software should not rely on the value of a 516 // reserved. Writing any other value than the reset/default value may result in 517 // undefined behavior. 518 #define CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_W 8 519 #define CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_M 0x0000FF00 520 #define CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_S 8 521 522 // Field: [7:0] VDDR_EXT_TP65 523 // 524 // Reserved for future use. Software should not rely on the value of a 525 // reserved. Writing any other value than the reset/default value may result in 526 // undefined behavior. 527 #define CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_W 8 528 #define CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_M 0x000000FF 529 #define CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_S 0 530 531 //***************************************************************************** 532 // 533 // Register: CCFG_O_RTC_OFFSET 534 // 535 //***************************************************************************** 536 // Field: [31:16] RTC_COMP_P0 537 // 538 // Reserved for future use. Software should not rely on the value of a 539 // reserved. Writing any other value than the reset/default value may result in 540 // undefined behavior. 541 #define CCFG_RTC_OFFSET_RTC_COMP_P0_W 16 542 #define CCFG_RTC_OFFSET_RTC_COMP_P0_M 0xFFFF0000 543 #define CCFG_RTC_OFFSET_RTC_COMP_P0_S 16 544 545 // Field: [15:8] RTC_COMP_P1 546 // 547 // Reserved for future use. Software should not rely on the value of a 548 // reserved. Writing any other value than the reset/default value may result in 549 // undefined behavior. 550 #define CCFG_RTC_OFFSET_RTC_COMP_P1_W 8 551 #define CCFG_RTC_OFFSET_RTC_COMP_P1_M 0x0000FF00 552 #define CCFG_RTC_OFFSET_RTC_COMP_P1_S 8 553 554 // Field: [7:0] RTC_COMP_P2 555 // 556 // Reserved for future use. Software should not rely on the value of a 557 // reserved. Writing any other value than the reset/default value may result in 558 // undefined behavior. 559 #define CCFG_RTC_OFFSET_RTC_COMP_P2_W 8 560 #define CCFG_RTC_OFFSET_RTC_COMP_P2_M 0x000000FF 561 #define CCFG_RTC_OFFSET_RTC_COMP_P2_S 0 562 563 //***************************************************************************** 564 // 565 // Register: CCFG_O_FREQ_OFFSET 566 // 567 //***************************************************************************** 568 // Field: [31:16] HF_COMP_P0 569 // 570 // Reserved for future use. Software should not rely on the value of a 571 // reserved. Writing any other value than the reset/default value may result in 572 // undefined behavior. 573 #define CCFG_FREQ_OFFSET_HF_COMP_P0_W 16 574 #define CCFG_FREQ_OFFSET_HF_COMP_P0_M 0xFFFF0000 575 #define CCFG_FREQ_OFFSET_HF_COMP_P0_S 16 576 577 // Field: [15:8] HF_COMP_P1 578 // 579 // Reserved for future use. Software should not rely on the value of a 580 // reserved. Writing any other value than the reset/default value may result in 581 // undefined behavior. 582 #define CCFG_FREQ_OFFSET_HF_COMP_P1_W 8 583 #define CCFG_FREQ_OFFSET_HF_COMP_P1_M 0x0000FF00 584 #define CCFG_FREQ_OFFSET_HF_COMP_P1_S 8 585 586 // Field: [7:0] HF_COMP_P2 587 // 588 // Reserved for future use. Software should not rely on the value of a 589 // reserved. Writing any other value than the reset/default value may result in 590 // undefined behavior. 591 #define CCFG_FREQ_OFFSET_HF_COMP_P2_W 8 592 #define CCFG_FREQ_OFFSET_HF_COMP_P2_M 0x000000FF 593 #define CCFG_FREQ_OFFSET_HF_COMP_P2_S 0 594 595 //***************************************************************************** 596 // 597 // Register: CCFG_O_IEEE_MAC_0 598 // 599 //***************************************************************************** 600 // Field: [31:0] ADDR 601 // 602 // Bits[31:0] of the 64-bits custom IEEE MAC address. 603 // If different from 0xFFFFFFFF then the value of this field is applied; 604 // otherwise use value from FCFG. 605 #define CCFG_IEEE_MAC_0_ADDR_W 32 606 #define CCFG_IEEE_MAC_0_ADDR_M 0xFFFFFFFF 607 #define CCFG_IEEE_MAC_0_ADDR_S 0 608 609 //***************************************************************************** 610 // 611 // Register: CCFG_O_IEEE_MAC_1 612 // 613 //***************************************************************************** 614 // Field: [31:0] ADDR 615 // 616 // Bits[63:32] of the 64-bits custom IEEE MAC address. 617 // If different from 0xFFFFFFFF then the value of this field is applied; 618 // otherwise use value from FCFG. 619 #define CCFG_IEEE_MAC_1_ADDR_W 32 620 #define CCFG_IEEE_MAC_1_ADDR_M 0xFFFFFFFF 621 #define CCFG_IEEE_MAC_1_ADDR_S 0 622 623 //***************************************************************************** 624 // 625 // Register: CCFG_O_IEEE_BLE_0 626 // 627 //***************************************************************************** 628 // Field: [31:0] ADDR 629 // 630 // Bits[31:0] of the 64-bits custom IEEE BLE address. 631 // If different from 0xFFFFFFFF then the value of this field is applied; 632 // otherwise use value from FCFG. 633 #define CCFG_IEEE_BLE_0_ADDR_W 32 634 #define CCFG_IEEE_BLE_0_ADDR_M 0xFFFFFFFF 635 #define CCFG_IEEE_BLE_0_ADDR_S 0 636 637 //***************************************************************************** 638 // 639 // Register: CCFG_O_IEEE_BLE_1 640 // 641 //***************************************************************************** 642 // Field: [31:0] ADDR 643 // 644 // Bits[63:32] of the 64-bits custom IEEE BLE address. 645 // If different from 0xFFFFFFFF then the value of this field is applied; 646 // otherwise use value from FCFG. 647 #define CCFG_IEEE_BLE_1_ADDR_W 32 648 #define CCFG_IEEE_BLE_1_ADDR_M 0xFFFFFFFF 649 #define CCFG_IEEE_BLE_1_ADDR_S 0 650 651 //***************************************************************************** 652 // 653 // Register: CCFG_O_BL_CONFIG 654 // 655 //***************************************************************************** 656 // Field: [31:24] BOOTLOADER_ENABLE 657 // 658 // Bootloader enable. Boot loader can be accessed if 659 // IMAGE_VALID_CONF.IMAGE_VALID is non-zero or BL_ENABLE is enabled (and 660 // conditions for boot loader backdoor are met). 661 // 0xC5: Boot loader is enabled. 662 // Any other value: Boot loader is disabled. 663 #define CCFG_BL_CONFIG_BOOTLOADER_ENABLE_W 8 664 #define CCFG_BL_CONFIG_BOOTLOADER_ENABLE_M 0xFF000000 665 #define CCFG_BL_CONFIG_BOOTLOADER_ENABLE_S 24 666 667 // Field: [16] BL_LEVEL 668 // 669 // Sets the active level of the selected DIO number BL_PIN_NUMBER if boot 670 // loader backdoor is enabled by the BL_ENABLE field. 671 // 0: Active low. 672 // 1: Active high. 673 #define CCFG_BL_CONFIG_BL_LEVEL 0x00010000 674 #define CCFG_BL_CONFIG_BL_LEVEL_BITN 16 675 #define CCFG_BL_CONFIG_BL_LEVEL_M 0x00010000 676 #define CCFG_BL_CONFIG_BL_LEVEL_S 16 677 678 // Field: [15:8] BL_PIN_NUMBER 679 // 680 // DIO number that is level checked if the boot loader backdoor is enabled by 681 // the BL_ENABLE field. 682 #define CCFG_BL_CONFIG_BL_PIN_NUMBER_W 8 683 #define CCFG_BL_CONFIG_BL_PIN_NUMBER_M 0x0000FF00 684 #define CCFG_BL_CONFIG_BL_PIN_NUMBER_S 8 685 686 // Field: [7:0] BL_ENABLE 687 // 688 // Enables the boot loader backdoor. 689 // 0xC5: Boot loader backdoor is enabled. 690 // Any other value: Boot loader backdoor is disabled. 691 // 692 // NOTE! Boot loader must be enabled (see BOOTLOADER_ENABLE) if boot loader 693 // backdoor is enabled. 694 #define CCFG_BL_CONFIG_BL_ENABLE_W 8 695 #define CCFG_BL_CONFIG_BL_ENABLE_M 0x000000FF 696 #define CCFG_BL_CONFIG_BL_ENABLE_S 0 697 698 //***************************************************************************** 699 // 700 // Register: CCFG_O_ERASE_CONF 701 // 702 //***************************************************************************** 703 // Field: [8] CHIP_ERASE_DIS_N 704 // 705 // Chip erase. 706 // This bit controls if a chip erase requested through the JTAG WUC TAP will be 707 // ignored in a following boot caused by a reset of the MCU VD. 708 // A successful chip erase operation will force the content of the flash main 709 // bank back to the state as it was when delivered by TI. 710 // 0: Disable. Any chip erase request detected during boot will be ignored. 711 // 1: Enable. Any chip erase request detected during boot will be performed by 712 // the boot FW. 713 #define CCFG_ERASE_CONF_CHIP_ERASE_DIS_N 0x00000100 714 #define CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_BITN 8 715 #define CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_M 0x00000100 716 #define CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_S 8 717 718 // Field: [0] BANK_ERASE_DIS_N 719 // 720 // Bank erase. 721 // This bit controls if the ROM serial boot loader will accept a received Bank 722 // Erase command (COMMAND_BANK_ERASE). 723 // A successful Bank Erase operation will erase all main bank sectors not 724 // protected by write protect configuration bits in CCFG. 725 // 0: Disable the boot loader bank erase function. 726 // 1: Enable the boot loader bank erase function. 727 #define CCFG_ERASE_CONF_BANK_ERASE_DIS_N 0x00000001 728 #define CCFG_ERASE_CONF_BANK_ERASE_DIS_N_BITN 0 729 #define CCFG_ERASE_CONF_BANK_ERASE_DIS_N_M 0x00000001 730 #define CCFG_ERASE_CONF_BANK_ERASE_DIS_N_S 0 731 732 //***************************************************************************** 733 // 734 // Register: CCFG_O_CCFG_TI_OPTIONS 735 // 736 //***************************************************************************** 737 // Field: [7:0] TI_FA_ENABLE 738 // 739 // TI Failure Analysis. 740 // 0xC5: Enable the functionality of unlocking the TI FA (TI Failure Analysis) 741 // option with the unlock code. 742 // All other values: Disable the functionality of unlocking the TI FA option 743 // with the unlock code. 744 #define CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_W 8 745 #define CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_M 0x000000FF 746 #define CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_S 0 747 748 //***************************************************************************** 749 // 750 // Register: CCFG_O_CCFG_TAP_DAP_0 751 // 752 //***************************************************************************** 753 // Field: [23:16] CPU_DAP_ENABLE 754 // 755 // Enable CPU DAP. 756 // 0xC5: Main CPU DAP access is enabled during power-up/system-reset by ROM 757 // boot FW. 758 // Any other value: Main CPU DAP access will remain disabled out of 759 // power-up/system-reset. 760 #define CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_W 8 761 #define CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_M 0x00FF0000 762 #define CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_S 16 763 764 // Field: [15:8] PRCM_TAP_ENABLE 765 // 766 // Enable PRCM TAP. 767 // 0xC5: PRCM TAP access is enabled during power-up/system-reset by ROM boot FW 768 // if enabled by corresponding configuration value in FCFG1 defined by TI. 769 // Any other value: PRCM TAP access will remain disabled out of 770 // power-up/system-reset. 771 #define CCFG_CCFG_TAP_DAP_0_PRCM_TAP_ENABLE_W 8 772 #define CCFG_CCFG_TAP_DAP_0_PRCM_TAP_ENABLE_M 0x0000FF00 773 #define CCFG_CCFG_TAP_DAP_0_PRCM_TAP_ENABLE_S 8 774 775 // Field: [7:0] TEST_TAP_ENABLE 776 // 777 // Enable Test TAP. 778 // 0xC5: TEST TAP access is enabled during power-up/system-reset by ROM boot FW 779 // if enabled by corresponding configuration value in FCFG1 defined by TI. 780 // Any other value: TEST TAP access will remain disabled out of 781 // power-up/system-reset. 782 #define CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_W 8 783 #define CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_M 0x000000FF 784 #define CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_S 0 785 786 //***************************************************************************** 787 // 788 // Register: CCFG_O_CCFG_TAP_DAP_1 789 // 790 //***************************************************************************** 791 // Field: [23:16] PBIST2_TAP_ENABLE 792 // 793 // Enable PBIST2 TAP. 794 // 0xC5: PBIST2 TAP access is enabled during power-up/system-reset by ROM boot 795 // FW if enabled by corresponding configuration value in FCFG1 defined by TI. 796 // Any other value: PBIST2 TAP access will remain disabled out of 797 // power-up/system-reset. 798 #define CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_W 8 799 #define CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_M 0x00FF0000 800 #define CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_S 16 801 802 // Field: [15:8] PBIST1_TAP_ENABLE 803 // 804 // Enable PBIST1 TAP. 805 // 0xC5: PBIST1 TAP access is enabled during power-up/system-reset by ROM boot 806 // FW if enabled by corresponding configuration value in FCFG1 defined by TI. 807 // Any other value: PBIST1 TAP access will remain disabled out of 808 // power-up/system-reset. 809 #define CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_W 8 810 #define CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_M 0x0000FF00 811 #define CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_S 8 812 813 // Field: [7:0] WUC_TAP_ENABLE 814 // 815 // Enable WUC TAP 816 // 0xC5: WUC TAP access is enabled during power-up/system-reset by ROM boot FW 817 // if enabled by corresponding configuration value in FCFG1 defined by TI. 818 // Any other value: WUC TAP access will remain disabled out of 819 // power-up/system-reset. 820 #define CCFG_CCFG_TAP_DAP_1_WUC_TAP_ENABLE_W 8 821 #define CCFG_CCFG_TAP_DAP_1_WUC_TAP_ENABLE_M 0x000000FF 822 #define CCFG_CCFG_TAP_DAP_1_WUC_TAP_ENABLE_S 0 823 824 //***************************************************************************** 825 // 826 // Register: CCFG_O_IMAGE_VALID_CONF 827 // 828 //***************************************************************************** 829 // Field: [31:0] IMAGE_VALID 830 // 831 // This field must have a value of 0x00000000 in order for enabling the boot 832 // sequence to transfer control to a flash image. 833 // A non-zero value forces the boot sequence to call the boot loader. 834 #define CCFG_IMAGE_VALID_CONF_IMAGE_VALID_W 32 835 #define CCFG_IMAGE_VALID_CONF_IMAGE_VALID_M 0xFFFFFFFF 836 #define CCFG_IMAGE_VALID_CONF_IMAGE_VALID_S 0 837 838 //***************************************************************************** 839 // 840 // Register: CCFG_O_CCFG_PROT_31_0 841 // 842 //***************************************************************************** 843 // Field: [31] WRT_PROT_SEC_31 844 // 845 // 0: Sector protected 846 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_31 0x80000000 847 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_31_BITN 31 848 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_31_M 0x80000000 849 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_31_S 31 850 851 // Field: [30] WRT_PROT_SEC_30 852 // 853 // 0: Sector protected 854 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_30 0x40000000 855 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_30_BITN 30 856 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_30_M 0x40000000 857 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_30_S 30 858 859 // Field: [29] WRT_PROT_SEC_29 860 // 861 // 0: Sector protected 862 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_29 0x20000000 863 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_29_BITN 29 864 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_29_M 0x20000000 865 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_29_S 29 866 867 // Field: [28] WRT_PROT_SEC_28 868 // 869 // 0: Sector protected 870 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_28 0x10000000 871 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_28_BITN 28 872 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_28_M 0x10000000 873 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_28_S 28 874 875 // Field: [27] WRT_PROT_SEC_27 876 // 877 // 0: Sector protected 878 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_27 0x08000000 879 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_27_BITN 27 880 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_27_M 0x08000000 881 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_27_S 27 882 883 // Field: [26] WRT_PROT_SEC_26 884 // 885 // 0: Sector protected 886 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_26 0x04000000 887 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_26_BITN 26 888 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_26_M 0x04000000 889 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_26_S 26 890 891 // Field: [25] WRT_PROT_SEC_25 892 // 893 // 0: Sector protected 894 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_25 0x02000000 895 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_25_BITN 25 896 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_25_M 0x02000000 897 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_25_S 25 898 899 // Field: [24] WRT_PROT_SEC_24 900 // 901 // 0: Sector protected 902 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_24 0x01000000 903 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_24_BITN 24 904 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_24_M 0x01000000 905 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_24_S 24 906 907 // Field: [23] WRT_PROT_SEC_23 908 // 909 // 0: Sector protected 910 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_23 0x00800000 911 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_23_BITN 23 912 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_23_M 0x00800000 913 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_23_S 23 914 915 // Field: [22] WRT_PROT_SEC_22 916 // 917 // 0: Sector protected 918 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_22 0x00400000 919 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_22_BITN 22 920 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_22_M 0x00400000 921 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_22_S 22 922 923 // Field: [21] WRT_PROT_SEC_21 924 // 925 // 0: Sector protected 926 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_21 0x00200000 927 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_21_BITN 21 928 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_21_M 0x00200000 929 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_21_S 21 930 931 // Field: [20] WRT_PROT_SEC_20 932 // 933 // 0: Sector protected 934 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_20 0x00100000 935 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_20_BITN 20 936 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_20_M 0x00100000 937 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_20_S 20 938 939 // Field: [19] WRT_PROT_SEC_19 940 // 941 // 0: Sector protected 942 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_19 0x00080000 943 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_19_BITN 19 944 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_19_M 0x00080000 945 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_19_S 19 946 947 // Field: [18] WRT_PROT_SEC_18 948 // 949 // 0: Sector protected 950 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_18 0x00040000 951 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_18_BITN 18 952 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_18_M 0x00040000 953 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_18_S 18 954 955 // Field: [17] WRT_PROT_SEC_17 956 // 957 // 0: Sector protected 958 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_17 0x00020000 959 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_17_BITN 17 960 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_17_M 0x00020000 961 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_17_S 17 962 963 // Field: [16] WRT_PROT_SEC_16 964 // 965 // 0: Sector protected 966 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_16 0x00010000 967 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_16_BITN 16 968 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_16_M 0x00010000 969 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_16_S 16 970 971 // Field: [15] WRT_PROT_SEC_15 972 // 973 // 0: Sector protected 974 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_15 0x00008000 975 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_15_BITN 15 976 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_15_M 0x00008000 977 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_15_S 15 978 979 // Field: [14] WRT_PROT_SEC_14 980 // 981 // 0: Sector protected 982 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_14 0x00004000 983 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_14_BITN 14 984 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_14_M 0x00004000 985 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_14_S 14 986 987 // Field: [13] WRT_PROT_SEC_13 988 // 989 // 0: Sector protected 990 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_13 0x00002000 991 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_13_BITN 13 992 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_13_M 0x00002000 993 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_13_S 13 994 995 // Field: [12] WRT_PROT_SEC_12 996 // 997 // 0: Sector protected 998 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_12 0x00001000 999 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_12_BITN 12 1000 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_12_M 0x00001000 1001 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_12_S 12 1002 1003 // Field: [11] WRT_PROT_SEC_11 1004 // 1005 // 0: Sector protected 1006 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_11 0x00000800 1007 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_11_BITN 11 1008 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_11_M 0x00000800 1009 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_11_S 11 1010 1011 // Field: [10] WRT_PROT_SEC_10 1012 // 1013 // 0: Sector protected 1014 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_10 0x00000400 1015 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_10_BITN 10 1016 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_10_M 0x00000400 1017 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_10_S 10 1018 1019 // Field: [9] WRT_PROT_SEC_9 1020 // 1021 // 0: Sector protected 1022 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_9 0x00000200 1023 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_9_BITN 9 1024 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_9_M 0x00000200 1025 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_9_S 9 1026 1027 // Field: [8] WRT_PROT_SEC_8 1028 // 1029 // 0: Sector protected 1030 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_8 0x00000100 1031 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_8_BITN 8 1032 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_8_M 0x00000100 1033 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_8_S 8 1034 1035 // Field: [7] WRT_PROT_SEC_7 1036 // 1037 // 0: Sector protected 1038 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_7 0x00000080 1039 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_7_BITN 7 1040 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_7_M 0x00000080 1041 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_7_S 7 1042 1043 // Field: [6] WRT_PROT_SEC_6 1044 // 1045 // 0: Sector protected 1046 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_6 0x00000040 1047 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_6_BITN 6 1048 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_6_M 0x00000040 1049 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_6_S 6 1050 1051 // Field: [5] WRT_PROT_SEC_5 1052 // 1053 // 0: Sector protected 1054 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_5 0x00000020 1055 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_5_BITN 5 1056 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_5_M 0x00000020 1057 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_5_S 5 1058 1059 // Field: [4] WRT_PROT_SEC_4 1060 // 1061 // 0: Sector protected 1062 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_4 0x00000010 1063 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_4_BITN 4 1064 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_4_M 0x00000010 1065 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_4_S 4 1066 1067 // Field: [3] WRT_PROT_SEC_3 1068 // 1069 // 0: Sector protected 1070 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_3 0x00000008 1071 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_3_BITN 3 1072 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_3_M 0x00000008 1073 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_3_S 3 1074 1075 // Field: [2] WRT_PROT_SEC_2 1076 // 1077 // 0: Sector protected 1078 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_2 0x00000004 1079 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_2_BITN 2 1080 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_2_M 0x00000004 1081 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_2_S 2 1082 1083 // Field: [1] WRT_PROT_SEC_1 1084 // 1085 // 0: Sector protected 1086 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_1 0x00000002 1087 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_1_BITN 1 1088 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_1_M 0x00000002 1089 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_1_S 1 1090 1091 // Field: [0] WRT_PROT_SEC_0 1092 // 1093 // 0: Sector protected 1094 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_0 0x00000001 1095 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_0_BITN 0 1096 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_0_M 0x00000001 1097 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_0_S 0 1098 1099 //***************************************************************************** 1100 // 1101 // Register: CCFG_O_CCFG_PROT_63_32 1102 // 1103 //***************************************************************************** 1104 // Field: [31] WRT_PROT_SEC_63 1105 // 1106 // 0: Sector protected 1107 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_63 0x80000000 1108 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_63_BITN 31 1109 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_63_M 0x80000000 1110 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_63_S 31 1111 1112 // Field: [30] WRT_PROT_SEC_62 1113 // 1114 // 0: Sector protected 1115 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_62 0x40000000 1116 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_62_BITN 30 1117 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_62_M 0x40000000 1118 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_62_S 30 1119 1120 // Field: [29] WRT_PROT_SEC_61 1121 // 1122 // 0: Sector protected 1123 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_61 0x20000000 1124 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_61_BITN 29 1125 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_61_M 0x20000000 1126 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_61_S 29 1127 1128 // Field: [28] WRT_PROT_SEC_60 1129 // 1130 // 0: Sector protected 1131 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_60 0x10000000 1132 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_60_BITN 28 1133 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_60_M 0x10000000 1134 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_60_S 28 1135 1136 // Field: [27] WRT_PROT_SEC_59 1137 // 1138 // 0: Sector protected 1139 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_59 0x08000000 1140 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_59_BITN 27 1141 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_59_M 0x08000000 1142 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_59_S 27 1143 1144 // Field: [26] WRT_PROT_SEC_58 1145 // 1146 // 0: Sector protected 1147 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_58 0x04000000 1148 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_58_BITN 26 1149 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_58_M 0x04000000 1150 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_58_S 26 1151 1152 // Field: [25] WRT_PROT_SEC_57 1153 // 1154 // 0: Sector protected 1155 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_57 0x02000000 1156 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_57_BITN 25 1157 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_57_M 0x02000000 1158 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_57_S 25 1159 1160 // Field: [24] WRT_PROT_SEC_56 1161 // 1162 // 0: Sector protected 1163 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_56 0x01000000 1164 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_56_BITN 24 1165 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_56_M 0x01000000 1166 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_56_S 24 1167 1168 // Field: [23] WRT_PROT_SEC_55 1169 // 1170 // 0: Sector protected 1171 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_55 0x00800000 1172 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_55_BITN 23 1173 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_55_M 0x00800000 1174 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_55_S 23 1175 1176 // Field: [22] WRT_PROT_SEC_54 1177 // 1178 // 0: Sector protected 1179 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_54 0x00400000 1180 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_54_BITN 22 1181 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_54_M 0x00400000 1182 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_54_S 22 1183 1184 // Field: [21] WRT_PROT_SEC_53 1185 // 1186 // 0: Sector protected 1187 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_53 0x00200000 1188 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_53_BITN 21 1189 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_53_M 0x00200000 1190 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_53_S 21 1191 1192 // Field: [20] WRT_PROT_SEC_52 1193 // 1194 // 0: Sector protected 1195 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_52 0x00100000 1196 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_52_BITN 20 1197 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_52_M 0x00100000 1198 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_52_S 20 1199 1200 // Field: [19] WRT_PROT_SEC_51 1201 // 1202 // 0: Sector protected 1203 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_51 0x00080000 1204 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_51_BITN 19 1205 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_51_M 0x00080000 1206 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_51_S 19 1207 1208 // Field: [18] WRT_PROT_SEC_50 1209 // 1210 // 0: Sector protected 1211 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_50 0x00040000 1212 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_50_BITN 18 1213 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_50_M 0x00040000 1214 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_50_S 18 1215 1216 // Field: [17] WRT_PROT_SEC_49 1217 // 1218 // 0: Sector protected 1219 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_49 0x00020000 1220 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_49_BITN 17 1221 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_49_M 0x00020000 1222 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_49_S 17 1223 1224 // Field: [16] WRT_PROT_SEC_48 1225 // 1226 // 0: Sector protected 1227 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_48 0x00010000 1228 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_48_BITN 16 1229 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_48_M 0x00010000 1230 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_48_S 16 1231 1232 // Field: [15] WRT_PROT_SEC_47 1233 // 1234 // 0: Sector protected 1235 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_47 0x00008000 1236 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_47_BITN 15 1237 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_47_M 0x00008000 1238 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_47_S 15 1239 1240 // Field: [14] WRT_PROT_SEC_46 1241 // 1242 // 0: Sector protected 1243 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_46 0x00004000 1244 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_46_BITN 14 1245 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_46_M 0x00004000 1246 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_46_S 14 1247 1248 // Field: [13] WRT_PROT_SEC_45 1249 // 1250 // 0: Sector protected 1251 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_45 0x00002000 1252 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_45_BITN 13 1253 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_45_M 0x00002000 1254 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_45_S 13 1255 1256 // Field: [12] WRT_PROT_SEC_44 1257 // 1258 // 0: Sector protected 1259 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_44 0x00001000 1260 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_44_BITN 12 1261 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_44_M 0x00001000 1262 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_44_S 12 1263 1264 // Field: [11] WRT_PROT_SEC_43 1265 // 1266 // 0: Sector protected 1267 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_43 0x00000800 1268 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_43_BITN 11 1269 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_43_M 0x00000800 1270 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_43_S 11 1271 1272 // Field: [10] WRT_PROT_SEC_42 1273 // 1274 // 0: Sector protected 1275 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_42 0x00000400 1276 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_42_BITN 10 1277 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_42_M 0x00000400 1278 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_42_S 10 1279 1280 // Field: [9] WRT_PROT_SEC_41 1281 // 1282 // 0: Sector protected 1283 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_41 0x00000200 1284 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_41_BITN 9 1285 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_41_M 0x00000200 1286 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_41_S 9 1287 1288 // Field: [8] WRT_PROT_SEC_40 1289 // 1290 // 0: Sector protected 1291 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_40 0x00000100 1292 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_40_BITN 8 1293 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_40_M 0x00000100 1294 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_40_S 8 1295 1296 // Field: [7] WRT_PROT_SEC_39 1297 // 1298 // 0: Sector protected 1299 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_39 0x00000080 1300 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_39_BITN 7 1301 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_39_M 0x00000080 1302 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_39_S 7 1303 1304 // Field: [6] WRT_PROT_SEC_38 1305 // 1306 // 0: Sector protected 1307 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_38 0x00000040 1308 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_38_BITN 6 1309 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_38_M 0x00000040 1310 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_38_S 6 1311 1312 // Field: [5] WRT_PROT_SEC_37 1313 // 1314 // 0: Sector protected 1315 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_37 0x00000020 1316 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_37_BITN 5 1317 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_37_M 0x00000020 1318 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_37_S 5 1319 1320 // Field: [4] WRT_PROT_SEC_36 1321 // 1322 // 0: Sector protected 1323 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_36 0x00000010 1324 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_36_BITN 4 1325 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_36_M 0x00000010 1326 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_36_S 4 1327 1328 // Field: [3] WRT_PROT_SEC_35 1329 // 1330 // 0: Sector protected 1331 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_35 0x00000008 1332 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_35_BITN 3 1333 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_35_M 0x00000008 1334 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_35_S 3 1335 1336 // Field: [2] WRT_PROT_SEC_34 1337 // 1338 // 0: Sector protected 1339 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_34 0x00000004 1340 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_34_BITN 2 1341 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_34_M 0x00000004 1342 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_34_S 2 1343 1344 // Field: [1] WRT_PROT_SEC_33 1345 // 1346 // 0: Sector protected 1347 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_33 0x00000002 1348 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_33_BITN 1 1349 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_33_M 0x00000002 1350 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_33_S 1 1351 1352 // Field: [0] WRT_PROT_SEC_32 1353 // 1354 // 0: Sector protected 1355 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_32 0x00000001 1356 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_32_BITN 0 1357 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_32_M 0x00000001 1358 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_32_S 0 1359 1360 //***************************************************************************** 1361 // 1362 // Register: CCFG_O_CCFG_PROT_95_64 1363 // 1364 //***************************************************************************** 1365 // Field: [31] WRT_PROT_SEC_95 1366 // 1367 // 0: Sector protected 1368 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_95 0x80000000 1369 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_95_BITN 31 1370 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_95_M 0x80000000 1371 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_95_S 31 1372 1373 // Field: [30] WRT_PROT_SEC_94 1374 // 1375 // 0: Sector protected 1376 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_94 0x40000000 1377 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_94_BITN 30 1378 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_94_M 0x40000000 1379 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_94_S 30 1380 1381 // Field: [29] WRT_PROT_SEC_93 1382 // 1383 // 0: Sector protected 1384 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_93 0x20000000 1385 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_93_BITN 29 1386 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_93_M 0x20000000 1387 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_93_S 29 1388 1389 // Field: [28] WRT_PROT_SEC_92 1390 // 1391 // 0: Sector protected 1392 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_92 0x10000000 1393 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_92_BITN 28 1394 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_92_M 0x10000000 1395 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_92_S 28 1396 1397 // Field: [27] WRT_PROT_SEC_91 1398 // 1399 // 0: Sector protected 1400 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_91 0x08000000 1401 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_91_BITN 27 1402 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_91_M 0x08000000 1403 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_91_S 27 1404 1405 // Field: [26] WRT_PROT_SEC_90 1406 // 1407 // 0: Sector protected 1408 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_90 0x04000000 1409 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_90_BITN 26 1410 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_90_M 0x04000000 1411 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_90_S 26 1412 1413 // Field: [25] WRT_PROT_SEC_89 1414 // 1415 // 0: Sector protected 1416 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_89 0x02000000 1417 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_89_BITN 25 1418 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_89_M 0x02000000 1419 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_89_S 25 1420 1421 // Field: [24] WRT_PROT_SEC_88 1422 // 1423 // 0: Sector protected 1424 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_88 0x01000000 1425 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_88_BITN 24 1426 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_88_M 0x01000000 1427 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_88_S 24 1428 1429 // Field: [23] WRT_PROT_SEC_87 1430 // 1431 // 0: Sector protected 1432 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_87 0x00800000 1433 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_87_BITN 23 1434 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_87_M 0x00800000 1435 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_87_S 23 1436 1437 // Field: [22] WRT_PROT_SEC_86 1438 // 1439 // 0: Sector protected 1440 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_86 0x00400000 1441 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_86_BITN 22 1442 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_86_M 0x00400000 1443 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_86_S 22 1444 1445 // Field: [21] WRT_PROT_SEC_85 1446 // 1447 // 0: Sector protected 1448 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_85 0x00200000 1449 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_85_BITN 21 1450 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_85_M 0x00200000 1451 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_85_S 21 1452 1453 // Field: [20] WRT_PROT_SEC_84 1454 // 1455 // 0: Sector protected 1456 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_84 0x00100000 1457 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_84_BITN 20 1458 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_84_M 0x00100000 1459 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_84_S 20 1460 1461 // Field: [19] WRT_PROT_SEC_83 1462 // 1463 // 0: Sector protected 1464 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_83 0x00080000 1465 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_83_BITN 19 1466 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_83_M 0x00080000 1467 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_83_S 19 1468 1469 // Field: [18] WRT_PROT_SEC_82 1470 // 1471 // 0: Sector protected 1472 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_82 0x00040000 1473 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_82_BITN 18 1474 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_82_M 0x00040000 1475 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_82_S 18 1476 1477 // Field: [17] WRT_PROT_SEC_81 1478 // 1479 // 0: Sector protected 1480 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_81 0x00020000 1481 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_81_BITN 17 1482 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_81_M 0x00020000 1483 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_81_S 17 1484 1485 // Field: [16] WRT_PROT_SEC_80 1486 // 1487 // 0: Sector protected 1488 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_80 0x00010000 1489 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_80_BITN 16 1490 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_80_M 0x00010000 1491 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_80_S 16 1492 1493 // Field: [15] WRT_PROT_SEC_79 1494 // 1495 // 0: Sector protected 1496 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_79 0x00008000 1497 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_79_BITN 15 1498 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_79_M 0x00008000 1499 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_79_S 15 1500 1501 // Field: [14] WRT_PROT_SEC_78 1502 // 1503 // 0: Sector protected 1504 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_78 0x00004000 1505 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_78_BITN 14 1506 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_78_M 0x00004000 1507 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_78_S 14 1508 1509 // Field: [13] WRT_PROT_SEC_77 1510 // 1511 // 0: Sector protected 1512 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_77 0x00002000 1513 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_77_BITN 13 1514 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_77_M 0x00002000 1515 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_77_S 13 1516 1517 // Field: [12] WRT_PROT_SEC_76 1518 // 1519 // 0: Sector protected 1520 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_76 0x00001000 1521 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_76_BITN 12 1522 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_76_M 0x00001000 1523 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_76_S 12 1524 1525 // Field: [11] WRT_PROT_SEC_75 1526 // 1527 // 0: Sector protected 1528 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_75 0x00000800 1529 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_75_BITN 11 1530 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_75_M 0x00000800 1531 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_75_S 11 1532 1533 // Field: [10] WRT_PROT_SEC_74 1534 // 1535 // 0: Sector protected 1536 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_74 0x00000400 1537 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_74_BITN 10 1538 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_74_M 0x00000400 1539 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_74_S 10 1540 1541 // Field: [9] WRT_PROT_SEC_73 1542 // 1543 // 0: Sector protected 1544 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_73 0x00000200 1545 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_73_BITN 9 1546 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_73_M 0x00000200 1547 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_73_S 9 1548 1549 // Field: [8] WRT_PROT_SEC_72 1550 // 1551 // 0: Sector protected 1552 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_72 0x00000100 1553 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_72_BITN 8 1554 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_72_M 0x00000100 1555 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_72_S 8 1556 1557 // Field: [7] WRT_PROT_SEC_71 1558 // 1559 // 0: Sector protected 1560 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_71 0x00000080 1561 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_71_BITN 7 1562 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_71_M 0x00000080 1563 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_71_S 7 1564 1565 // Field: [6] WRT_PROT_SEC_70 1566 // 1567 // 0: Sector protected 1568 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_70 0x00000040 1569 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_70_BITN 6 1570 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_70_M 0x00000040 1571 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_70_S 6 1572 1573 // Field: [5] WRT_PROT_SEC_69 1574 // 1575 // 0: Sector protected 1576 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_69 0x00000020 1577 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_69_BITN 5 1578 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_69_M 0x00000020 1579 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_69_S 5 1580 1581 // Field: [4] WRT_PROT_SEC_68 1582 // 1583 // 0: Sector protected 1584 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_68 0x00000010 1585 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_68_BITN 4 1586 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_68_M 0x00000010 1587 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_68_S 4 1588 1589 // Field: [3] WRT_PROT_SEC_67 1590 // 1591 // 0: Sector protected 1592 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_67 0x00000008 1593 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_67_BITN 3 1594 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_67_M 0x00000008 1595 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_67_S 3 1596 1597 // Field: [2] WRT_PROT_SEC_66 1598 // 1599 // 0: Sector protected 1600 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_66 0x00000004 1601 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_66_BITN 2 1602 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_66_M 0x00000004 1603 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_66_S 2 1604 1605 // Field: [1] WRT_PROT_SEC_65 1606 // 1607 // 0: Sector protected 1608 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_65 0x00000002 1609 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_65_BITN 1 1610 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_65_M 0x00000002 1611 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_65_S 1 1612 1613 // Field: [0] WRT_PROT_SEC_64 1614 // 1615 // 0: Sector protected 1616 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_64 0x00000001 1617 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_64_BITN 0 1618 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_64_M 0x00000001 1619 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_64_S 0 1620 1621 //***************************************************************************** 1622 // 1623 // Register: CCFG_O_CCFG_PROT_127_96 1624 // 1625 //***************************************************************************** 1626 // Field: [31] WRT_PROT_SEC_127 1627 // 1628 // 0: Sector protected 1629 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_127 0x80000000 1630 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_127_BITN 31 1631 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_127_M 0x80000000 1632 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_127_S 31 1633 1634 // Field: [30] WRT_PROT_SEC_126 1635 // 1636 // 0: Sector protected 1637 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_126 0x40000000 1638 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_126_BITN 30 1639 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_126_M 0x40000000 1640 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_126_S 30 1641 1642 // Field: [29] WRT_PROT_SEC_125 1643 // 1644 // 0: Sector protected 1645 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_125 0x20000000 1646 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_125_BITN 29 1647 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_125_M 0x20000000 1648 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_125_S 29 1649 1650 // Field: [28] WRT_PROT_SEC_124 1651 // 1652 // 0: Sector protected 1653 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_124 0x10000000 1654 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_124_BITN 28 1655 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_124_M 0x10000000 1656 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_124_S 28 1657 1658 // Field: [27] WRT_PROT_SEC_123 1659 // 1660 // 0: Sector protected 1661 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_123 0x08000000 1662 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_123_BITN 27 1663 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_123_M 0x08000000 1664 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_123_S 27 1665 1666 // Field: [26] WRT_PROT_SEC_122 1667 // 1668 // 0: Sector protected 1669 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_122 0x04000000 1670 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_122_BITN 26 1671 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_122_M 0x04000000 1672 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_122_S 26 1673 1674 // Field: [25] WRT_PROT_SEC_121 1675 // 1676 // 0: Sector protected 1677 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_121 0x02000000 1678 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_121_BITN 25 1679 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_121_M 0x02000000 1680 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_121_S 25 1681 1682 // Field: [24] WRT_PROT_SEC_120 1683 // 1684 // 0: Sector protected 1685 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_120 0x01000000 1686 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_120_BITN 24 1687 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_120_M 0x01000000 1688 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_120_S 24 1689 1690 // Field: [23] WRT_PROT_SEC_119 1691 // 1692 // 0: Sector protected 1693 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_119 0x00800000 1694 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_119_BITN 23 1695 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_119_M 0x00800000 1696 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_119_S 23 1697 1698 // Field: [22] WRT_PROT_SEC_118 1699 // 1700 // 0: Sector protected 1701 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_118 0x00400000 1702 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_118_BITN 22 1703 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_118_M 0x00400000 1704 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_118_S 22 1705 1706 // Field: [21] WRT_PROT_SEC_117 1707 // 1708 // 0: Sector protected 1709 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_117 0x00200000 1710 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_117_BITN 21 1711 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_117_M 0x00200000 1712 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_117_S 21 1713 1714 // Field: [20] WRT_PROT_SEC_116 1715 // 1716 // 0: Sector protected 1717 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_116 0x00100000 1718 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_116_BITN 20 1719 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_116_M 0x00100000 1720 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_116_S 20 1721 1722 // Field: [19] WRT_PROT_SEC_115 1723 // 1724 // 0: Sector protected 1725 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_115 0x00080000 1726 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_115_BITN 19 1727 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_115_M 0x00080000 1728 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_115_S 19 1729 1730 // Field: [18] WRT_PROT_SEC_114 1731 // 1732 // 0: Sector protected 1733 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_114 0x00040000 1734 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_114_BITN 18 1735 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_114_M 0x00040000 1736 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_114_S 18 1737 1738 // Field: [17] WRT_PROT_SEC_113 1739 // 1740 // 0: Sector protected 1741 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_113 0x00020000 1742 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_113_BITN 17 1743 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_113_M 0x00020000 1744 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_113_S 17 1745 1746 // Field: [16] WRT_PROT_SEC_112 1747 // 1748 // 0: Sector protected 1749 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_112 0x00010000 1750 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_112_BITN 16 1751 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_112_M 0x00010000 1752 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_112_S 16 1753 1754 // Field: [15] WRT_PROT_SEC_111 1755 // 1756 // 0: Sector protected 1757 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_111 0x00008000 1758 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_111_BITN 15 1759 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_111_M 0x00008000 1760 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_111_S 15 1761 1762 // Field: [14] WRT_PROT_SEC_110 1763 // 1764 // 0: Sector protected 1765 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_110 0x00004000 1766 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_110_BITN 14 1767 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_110_M 0x00004000 1768 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_110_S 14 1769 1770 // Field: [13] WRT_PROT_SEC_109 1771 // 1772 // 0: Sector protected 1773 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_109 0x00002000 1774 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_109_BITN 13 1775 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_109_M 0x00002000 1776 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_109_S 13 1777 1778 // Field: [12] WRT_PROT_SEC_108 1779 // 1780 // 0: Sector protected 1781 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_108 0x00001000 1782 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_108_BITN 12 1783 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_108_M 0x00001000 1784 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_108_S 12 1785 1786 // Field: [11] WRT_PROT_SEC_107 1787 // 1788 // 0: Sector protected 1789 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_107 0x00000800 1790 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_107_BITN 11 1791 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_107_M 0x00000800 1792 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_107_S 11 1793 1794 // Field: [10] WRT_PROT_SEC_106 1795 // 1796 // 0: Sector protected 1797 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_106 0x00000400 1798 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_106_BITN 10 1799 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_106_M 0x00000400 1800 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_106_S 10 1801 1802 // Field: [9] WRT_PROT_SEC_105 1803 // 1804 // 0: Sector protected 1805 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_105 0x00000200 1806 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_105_BITN 9 1807 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_105_M 0x00000200 1808 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_105_S 9 1809 1810 // Field: [8] WRT_PROT_SEC_104 1811 // 1812 // 0: Sector protected 1813 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_104 0x00000100 1814 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_104_BITN 8 1815 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_104_M 0x00000100 1816 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_104_S 8 1817 1818 // Field: [7] WRT_PROT_SEC_103 1819 // 1820 // 0: Sector protected 1821 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_103 0x00000080 1822 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_103_BITN 7 1823 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_103_M 0x00000080 1824 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_103_S 7 1825 1826 // Field: [6] WRT_PROT_SEC_102 1827 // 1828 // 0: Sector protected 1829 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_102 0x00000040 1830 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_102_BITN 6 1831 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_102_M 0x00000040 1832 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_102_S 6 1833 1834 // Field: [5] WRT_PROT_SEC_101 1835 // 1836 // 0: Sector protected 1837 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_101 0x00000020 1838 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_101_BITN 5 1839 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_101_M 0x00000020 1840 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_101_S 5 1841 1842 // Field: [4] WRT_PROT_SEC_100 1843 // 1844 // 0: Sector protected 1845 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_100 0x00000010 1846 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_100_BITN 4 1847 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_100_M 0x00000010 1848 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_100_S 4 1849 1850 // Field: [3] WRT_PROT_SEC_99 1851 // 1852 // 0: Sector protected 1853 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_99 0x00000008 1854 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_99_BITN 3 1855 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_99_M 0x00000008 1856 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_99_S 3 1857 1858 // Field: [2] WRT_PROT_SEC_98 1859 // 1860 // 0: Sector protected 1861 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_98 0x00000004 1862 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_98_BITN 2 1863 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_98_M 0x00000004 1864 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_98_S 2 1865 1866 // Field: [1] WRT_PROT_SEC_97 1867 // 1868 // 0: Sector protected 1869 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_97 0x00000002 1870 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_97_BITN 1 1871 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_97_M 0x00000002 1872 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_97_S 1 1873 1874 // Field: [0] WRT_PROT_SEC_96 1875 // 1876 // 0: Sector protected 1877 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_96 0x00000001 1878 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_96_BITN 0 1879 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_96_M 0x00000001 1880 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_96_S 0 1881 1882 1883 #endif // __CCFG__ 1884