1 /****************************************************************************** 2 * Filename: hw_cpu_fpb_h 3 * Revised: 2015-11-12 13:07:02 +0100 (Thu, 12 Nov 2015) 4 * Revision: 45056 5 * 6 * Copyright (c) 2015, Texas Instruments Incorporated 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions are met: 11 * 12 * 1) Redistributions of source code must retain the above copyright notice, 13 * this list of conditions and the following disclaimer. 14 * 15 * 2) Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 19 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may 20 * be used to endorse or promote products derived from this software without 21 * specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 * 35 ******************************************************************************/ 36 37 #ifndef __HW_CPU_FPB_H__ 38 #define __HW_CPU_FPB_H__ 39 40 //***************************************************************************** 41 // 42 // This section defines the register offsets of 43 // CPU_FPB component 44 // 45 //***************************************************************************** 46 // Control 47 #define CPU_FPB_O_CTRL 0x00000000 48 49 // Remap 50 #define CPU_FPB_O_REMAP 0x00000004 51 52 // Comparator 0 53 #define CPU_FPB_O_COMP0 0x00000008 54 55 // Comparator 1 56 #define CPU_FPB_O_COMP1 0x0000000C 57 58 // Comparator 2 59 #define CPU_FPB_O_COMP2 0x00000010 60 61 // Comparator 3 62 #define CPU_FPB_O_COMP3 0x00000014 63 64 // Comparator 4 65 #define CPU_FPB_O_COMP4 0x00000018 66 67 // Comparator 5 68 #define CPU_FPB_O_COMP5 0x0000001C 69 70 // Comparator 6 71 #define CPU_FPB_O_COMP6 0x00000020 72 73 // Comparator 7 74 #define CPU_FPB_O_COMP7 0x00000024 75 76 //***************************************************************************** 77 // 78 // Register: CPU_FPB_O_CTRL 79 // 80 //***************************************************************************** 81 // Field: [13:12] NUM_CODE2 82 // 83 // Number of full banks of code comparators, sixteen comparators per bank. 84 // Where less than sixteen code comparators are provided, the bank count is 85 // zero, and the number present indicated by NUM_CODE1. This read only field 86 // contains 3'b000 to indicate 0 banks for Cortex-M processor. 87 #define CPU_FPB_CTRL_NUM_CODE2_W 2 88 #define CPU_FPB_CTRL_NUM_CODE2_M 0x00003000 89 #define CPU_FPB_CTRL_NUM_CODE2_S 12 90 91 // Field: [11:8] NUM_LIT 92 // 93 // Number of literal slots field. 94 // 95 // 0x0: No literal slots 96 // 0x2: Two literal slots 97 #define CPU_FPB_CTRL_NUM_LIT_W 4 98 #define CPU_FPB_CTRL_NUM_LIT_M 0x00000F00 99 #define CPU_FPB_CTRL_NUM_LIT_S 8 100 101 // Field: [7:4] NUM_CODE1 102 // 103 // Number of code slots field. 104 // 105 // 0x0: No code slots 106 // 0x2: Two code slots 107 // 0x6: Six code slots 108 #define CPU_FPB_CTRL_NUM_CODE1_W 4 109 #define CPU_FPB_CTRL_NUM_CODE1_M 0x000000F0 110 #define CPU_FPB_CTRL_NUM_CODE1_S 4 111 112 // Field: [1] KEY 113 // 114 // Key field. In order to write to this register, this bit-field must be 115 // written to '1'. This bit always reads 0. 116 #define CPU_FPB_CTRL_KEY 0x00000002 117 #define CPU_FPB_CTRL_KEY_BITN 1 118 #define CPU_FPB_CTRL_KEY_M 0x00000002 119 #define CPU_FPB_CTRL_KEY_S 1 120 121 // Field: [0] ENABLE 122 // 123 // Flash patch unit enable bit 124 // 125 // 0x0: Flash patch unit disabled 126 // 0x1: Flash patch unit enabled 127 #define CPU_FPB_CTRL_ENABLE 0x00000001 128 #define CPU_FPB_CTRL_ENABLE_BITN 0 129 #define CPU_FPB_CTRL_ENABLE_M 0x00000001 130 #define CPU_FPB_CTRL_ENABLE_S 0 131 132 //***************************************************************************** 133 // 134 // Register: CPU_FPB_O_REMAP 135 // 136 //***************************************************************************** 137 // Field: [28:5] REMAP 138 // 139 // Remap base address field. 140 #define CPU_FPB_REMAP_REMAP_W 24 141 #define CPU_FPB_REMAP_REMAP_M 0x1FFFFFE0 142 #define CPU_FPB_REMAP_REMAP_S 5 143 144 //***************************************************************************** 145 // 146 // Register: CPU_FPB_O_COMP0 147 // 148 //***************************************************************************** 149 // Field: [31:30] REPLACE 150 // 151 // This selects what happens when the COMP address is matched. Address 152 // remapping only takes place for the 0x0 setting. 153 // 154 // 0x0: Remap to remap address. See REMAP.REMAP 155 // 0x1: Set BKPT on lower halfword, upper is unaffected 156 // 0x2: Set BKPT on upper halfword, lower is unaffected 157 // 0x3: Set BKPT on both lower and upper halfwords. 158 #define CPU_FPB_COMP0_REPLACE_W 2 159 #define CPU_FPB_COMP0_REPLACE_M 0xC0000000 160 #define CPU_FPB_COMP0_REPLACE_S 30 161 162 // Field: [28:2] COMP 163 // 164 // Comparison address. 165 #define CPU_FPB_COMP0_COMP_W 27 166 #define CPU_FPB_COMP0_COMP_M 0x1FFFFFFC 167 #define CPU_FPB_COMP0_COMP_S 2 168 169 // Field: [0] ENABLE 170 // 171 // Compare and remap enable comparator 0. CTRL.ENABLE must also be set to 172 // enable comparisons. 173 // 174 // 0x0: Compare and remap for comparator 0 disabled 175 // 0x1: Compare and remap for comparator 0 enabled 176 #define CPU_FPB_COMP0_ENABLE 0x00000001 177 #define CPU_FPB_COMP0_ENABLE_BITN 0 178 #define CPU_FPB_COMP0_ENABLE_M 0x00000001 179 #define CPU_FPB_COMP0_ENABLE_S 0 180 181 //***************************************************************************** 182 // 183 // Register: CPU_FPB_O_COMP1 184 // 185 //***************************************************************************** 186 // Field: [31:30] REPLACE 187 // 188 // This selects what happens when the COMP address is matched. Address 189 // remapping only takes place for the 0x0 setting. 190 // 191 // 0x0: Remap to remap address. See REMAP.REMAP 192 // 0x1: Set BKPT on lower halfword, upper is unaffected 193 // 0x2: Set BKPT on upper halfword, lower is unaffected 194 // 0x3: Set BKPT on both lower and upper halfwords. 195 #define CPU_FPB_COMP1_REPLACE_W 2 196 #define CPU_FPB_COMP1_REPLACE_M 0xC0000000 197 #define CPU_FPB_COMP1_REPLACE_S 30 198 199 // Field: [28:2] COMP 200 // 201 // Comparison address. 202 #define CPU_FPB_COMP1_COMP_W 27 203 #define CPU_FPB_COMP1_COMP_M 0x1FFFFFFC 204 #define CPU_FPB_COMP1_COMP_S 2 205 206 // Field: [0] ENABLE 207 // 208 // Compare and remap enable comparator 1. CTRL.ENABLE must also be set to 209 // enable comparisons. 210 // 211 // 0x0: Compare and remap for comparator 1 disabled 212 // 0x1: Compare and remap for comparator 1 enabled 213 #define CPU_FPB_COMP1_ENABLE 0x00000001 214 #define CPU_FPB_COMP1_ENABLE_BITN 0 215 #define CPU_FPB_COMP1_ENABLE_M 0x00000001 216 #define CPU_FPB_COMP1_ENABLE_S 0 217 218 //***************************************************************************** 219 // 220 // Register: CPU_FPB_O_COMP2 221 // 222 //***************************************************************************** 223 // Field: [31:30] REPLACE 224 // 225 // This selects what happens when the COMP address is matched. Address 226 // remapping only takes place for the 0x0 setting. 227 // 228 // 0x0: Remap to remap address. See REMAP.REMAP 229 // 0x1: Set BKPT on lower halfword, upper is unaffected 230 // 0x2: Set BKPT on upper halfword, lower is unaffected 231 // 0x3: Set BKPT on both lower and upper halfwords. 232 #define CPU_FPB_COMP2_REPLACE_W 2 233 #define CPU_FPB_COMP2_REPLACE_M 0xC0000000 234 #define CPU_FPB_COMP2_REPLACE_S 30 235 236 // Field: [28:2] COMP 237 // 238 // Comparison address. 239 #define CPU_FPB_COMP2_COMP_W 27 240 #define CPU_FPB_COMP2_COMP_M 0x1FFFFFFC 241 #define CPU_FPB_COMP2_COMP_S 2 242 243 // Field: [0] ENABLE 244 // 245 // Compare and remap enable comparator 2. CTRL.ENABLE must also be set to 246 // enable comparisons. 247 // 248 // 0x0: Compare and remap for comparator 2 disabled 249 // 0x1: Compare and remap for comparator 2 enabled 250 #define CPU_FPB_COMP2_ENABLE 0x00000001 251 #define CPU_FPB_COMP2_ENABLE_BITN 0 252 #define CPU_FPB_COMP2_ENABLE_M 0x00000001 253 #define CPU_FPB_COMP2_ENABLE_S 0 254 255 //***************************************************************************** 256 // 257 // Register: CPU_FPB_O_COMP3 258 // 259 //***************************************************************************** 260 // Field: [31:30] REPLACE 261 // 262 // This selects what happens when the COMP address is matched. Address 263 // remapping only takes place for the 0x0 setting. 264 // 265 // 0x0: Remap to remap address. See REMAP.REMAP 266 // 0x1: Set BKPT on lower halfword, upper is unaffected 267 // 0x2: Set BKPT on upper halfword, lower is unaffected 268 // 0x3: Set BKPT on both lower and upper halfwords. 269 #define CPU_FPB_COMP3_REPLACE_W 2 270 #define CPU_FPB_COMP3_REPLACE_M 0xC0000000 271 #define CPU_FPB_COMP3_REPLACE_S 30 272 273 // Field: [28:2] COMP 274 // 275 // Comparison address. 276 #define CPU_FPB_COMP3_COMP_W 27 277 #define CPU_FPB_COMP3_COMP_M 0x1FFFFFFC 278 #define CPU_FPB_COMP3_COMP_S 2 279 280 // Field: [0] ENABLE 281 // 282 // Compare and remap enable comparator 3. CTRL.ENABLE must also be set to 283 // enable comparisons. 284 // 285 // 0x0: Compare and remap for comparator 3 disabled 286 // 0x1: Compare and remap for comparator 3 enabled 287 #define CPU_FPB_COMP3_ENABLE 0x00000001 288 #define CPU_FPB_COMP3_ENABLE_BITN 0 289 #define CPU_FPB_COMP3_ENABLE_M 0x00000001 290 #define CPU_FPB_COMP3_ENABLE_S 0 291 292 //***************************************************************************** 293 // 294 // Register: CPU_FPB_O_COMP4 295 // 296 //***************************************************************************** 297 // Field: [31:30] REPLACE 298 // 299 // This selects what happens when the COMP address is matched. Address 300 // remapping only takes place for the 0x0 setting. 301 // 302 // 0x0: Remap to remap address. See REMAP.REMAP 303 // 0x1: Set BKPT on lower halfword, upper is unaffected 304 // 0x2: Set BKPT on upper halfword, lower is unaffected 305 // 0x3: Set BKPT on both lower and upper halfwords. 306 #define CPU_FPB_COMP4_REPLACE_W 2 307 #define CPU_FPB_COMP4_REPLACE_M 0xC0000000 308 #define CPU_FPB_COMP4_REPLACE_S 30 309 310 // Field: [28:2] COMP 311 // 312 // Comparison address. 313 #define CPU_FPB_COMP4_COMP_W 27 314 #define CPU_FPB_COMP4_COMP_M 0x1FFFFFFC 315 #define CPU_FPB_COMP4_COMP_S 2 316 317 // Field: [0] ENABLE 318 // 319 // Compare and remap enable comparator 4. CTRL.ENABLE must also be set to 320 // enable comparisons. 321 // 322 // 0x0: Compare and remap for comparator 4 disabled 323 // 0x1: Compare and remap for comparator 4 enabled 324 #define CPU_FPB_COMP4_ENABLE 0x00000001 325 #define CPU_FPB_COMP4_ENABLE_BITN 0 326 #define CPU_FPB_COMP4_ENABLE_M 0x00000001 327 #define CPU_FPB_COMP4_ENABLE_S 0 328 329 //***************************************************************************** 330 // 331 // Register: CPU_FPB_O_COMP5 332 // 333 //***************************************************************************** 334 // Field: [31:30] REPLACE 335 // 336 // This selects what happens when the COMP address is matched. Address 337 // remapping only takes place for the 0x0 setting. 338 // 339 // 0x0: Remap to remap address. See REMAP.REMAP 340 // 0x1: Set BKPT on lower halfword, upper is unaffected 341 // 0x2: Set BKPT on upper halfword, lower is unaffected 342 // 0x3: Set BKPT on both lower and upper halfwords. 343 #define CPU_FPB_COMP5_REPLACE_W 2 344 #define CPU_FPB_COMP5_REPLACE_M 0xC0000000 345 #define CPU_FPB_COMP5_REPLACE_S 30 346 347 // Field: [28:2] COMP 348 // 349 // Comparison address. 350 #define CPU_FPB_COMP5_COMP_W 27 351 #define CPU_FPB_COMP5_COMP_M 0x1FFFFFFC 352 #define CPU_FPB_COMP5_COMP_S 2 353 354 // Field: [0] ENABLE 355 // 356 // Compare and remap enable comparator 5. CTRL.ENABLE must also be set to 357 // enable comparisons. 358 // 359 // 0x0: Compare and remap for comparator 5 disabled 360 // 0x1: Compare and remap for comparator 5 enabled 361 #define CPU_FPB_COMP5_ENABLE 0x00000001 362 #define CPU_FPB_COMP5_ENABLE_BITN 0 363 #define CPU_FPB_COMP5_ENABLE_M 0x00000001 364 #define CPU_FPB_COMP5_ENABLE_S 0 365 366 //***************************************************************************** 367 // 368 // Register: CPU_FPB_O_COMP6 369 // 370 //***************************************************************************** 371 // Field: [31:30] REPLACE 372 // 373 // This selects what happens when the COMP address is matched. Comparator 6 is 374 // a literal comparator and the only supported setting is 0x0. Other settings 375 // will be ignored. 376 // 377 // 0x0: Remap to remap address. See REMAP.REMAP 378 // 0x1: Set BKPT on lower halfword, upper is unaffected 379 // 0x2: Set BKPT on upper halfword, lower is unaffected 380 // 0x3: Set BKPT on both lower and upper halfwords. 381 #define CPU_FPB_COMP6_REPLACE_W 2 382 #define CPU_FPB_COMP6_REPLACE_M 0xC0000000 383 #define CPU_FPB_COMP6_REPLACE_S 30 384 385 // Field: [28:2] COMP 386 // 387 // Comparison address. 388 #define CPU_FPB_COMP6_COMP_W 27 389 #define CPU_FPB_COMP6_COMP_M 0x1FFFFFFC 390 #define CPU_FPB_COMP6_COMP_S 2 391 392 // Field: [0] ENABLE 393 // 394 // Compare and remap enable comparator 6. CTRL.ENABLE must also be set to 395 // enable comparisons. 396 // 397 // 0x0: Compare and remap for comparator 6 disabled 398 // 0x1: Compare and remap for comparator 6 enabled 399 #define CPU_FPB_COMP6_ENABLE 0x00000001 400 #define CPU_FPB_COMP6_ENABLE_BITN 0 401 #define CPU_FPB_COMP6_ENABLE_M 0x00000001 402 #define CPU_FPB_COMP6_ENABLE_S 0 403 404 //***************************************************************************** 405 // 406 // Register: CPU_FPB_O_COMP7 407 // 408 //***************************************************************************** 409 // Field: [31:30] REPLACE 410 // 411 // This selects what happens when the COMP address is matched. Comparator 7 is 412 // a literal comparator and the only supported setting is 0x0. Other settings 413 // will be ignored. 414 // 415 // 0x0: Remap to remap address. See REMAP.REMAP 416 // 0x1: Set BKPT on lower halfword, upper is unaffected 417 // 0x2: Set BKPT on upper halfword, lower is unaffected 418 // 0x3: Set BKPT on both lower and upper halfwords. 419 #define CPU_FPB_COMP7_REPLACE_W 2 420 #define CPU_FPB_COMP7_REPLACE_M 0xC0000000 421 #define CPU_FPB_COMP7_REPLACE_S 30 422 423 // Field: [28:2] COMP 424 // 425 // Comparison address. 426 #define CPU_FPB_COMP7_COMP_W 27 427 #define CPU_FPB_COMP7_COMP_M 0x1FFFFFFC 428 #define CPU_FPB_COMP7_COMP_S 2 429 430 // Field: [0] ENABLE 431 // 432 // Compare and remap enable comparator 7. CTRL.ENABLE must also be set to 433 // enable comparisons. 434 // 435 // 0x0: Compare and remap for comparator 7 disabled 436 // 0x1: Compare and remap for comparator 7 enabled 437 #define CPU_FPB_COMP7_ENABLE 0x00000001 438 #define CPU_FPB_COMP7_ENABLE_BITN 0 439 #define CPU_FPB_COMP7_ENABLE_M 0x00000001 440 #define CPU_FPB_COMP7_ENABLE_S 0 441 442 443 #endif // __CPU_FPB__ 444