1 /****************************************************************************** 2 * Filename: hw_cpu_rom_table_h 3 * Revised: 2015-11-12 13:07:02 +0100 (Thu, 12 Nov 2015) 4 * Revision: 45056 5 * 6 * Copyright (c) 2015, Texas Instruments Incorporated 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions are met: 11 * 12 * 1) Redistributions of source code must retain the above copyright notice, 13 * this list of conditions and the following disclaimer. 14 * 15 * 2) Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 19 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may 20 * be used to endorse or promote products derived from this software without 21 * specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 * 35 ******************************************************************************/ 36 37 #ifndef __HW_CPU_ROM_TABLE_H__ 38 #define __HW_CPU_ROM_TABLE_H__ 39 40 //***************************************************************************** 41 // 42 // This section defines the register offsets of 43 // CPU_ROM_TABLE component 44 // 45 //***************************************************************************** 46 // System Control Space Component 47 #define CPU_ROM_TABLE_O_SCS 0x00000000 48 49 // Data Watchpoint and Trace Component 50 #define CPU_ROM_TABLE_O_DWT 0x00000004 51 52 // Flash Patch and Breakpoint Component 53 #define CPU_ROM_TABLE_O_FPB 0x00000008 54 55 // Instrumentation Trace Component 56 #define CPU_ROM_TABLE_O_ITM 0x0000000C 57 58 // Trace Port Interface Component 59 #define CPU_ROM_TABLE_O_TPIU 0x00000010 60 61 // Enhanced Trace Component 62 #define CPU_ROM_TABLE_O_ETM 0x00000014 63 64 // End Marker 65 #define CPU_ROM_TABLE_O_END 0x00000018 66 67 // System Memory Map Access for DAP 68 #define CPU_ROM_TABLE_O_SYSTEM_ACCESS 0x00000FCC 69 70 //***************************************************************************** 71 // 72 // Register: CPU_ROM_TABLE_O_SCS 73 // 74 //***************************************************************************** 75 // Field: [31:0] SCS 76 // 77 // Points to the SCS at 0xE000E000. 78 // (SCS + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE000E000. 79 #define CPU_ROM_TABLE_SCS_SCS_W 32 80 #define CPU_ROM_TABLE_SCS_SCS_M 0xFFFFFFFF 81 #define CPU_ROM_TABLE_SCS_SCS_S 0 82 83 //***************************************************************************** 84 // 85 // Register: CPU_ROM_TABLE_O_DWT 86 // 87 //***************************************************************************** 88 // Field: [31:1] DWT 89 // 90 // Points to the Data Watchpoint and Trace block at 0xE0001000. 91 // (2*DWT + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE0001000. 92 #define CPU_ROM_TABLE_DWT_DWT_W 31 93 #define CPU_ROM_TABLE_DWT_DWT_M 0xFFFFFFFE 94 #define CPU_ROM_TABLE_DWT_DWT_S 1 95 96 // Field: [0] DWT_PRESENT 97 // 98 // 0: DWT is not present 99 // 1: DWT is present. 100 #define CPU_ROM_TABLE_DWT_DWT_PRESENT 0x00000001 101 #define CPU_ROM_TABLE_DWT_DWT_PRESENT_BITN 0 102 #define CPU_ROM_TABLE_DWT_DWT_PRESENT_M 0x00000001 103 #define CPU_ROM_TABLE_DWT_DWT_PRESENT_S 0 104 105 //***************************************************************************** 106 // 107 // Register: CPU_ROM_TABLE_O_FPB 108 // 109 //***************************************************************************** 110 // Field: [31:1] FPB 111 // 112 // Points to the Flash Patch and Breakpoint block at 0xE0002000. 113 // (2*FPB + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE0002000. 114 #define CPU_ROM_TABLE_FPB_FPB_W 31 115 #define CPU_ROM_TABLE_FPB_FPB_M 0xFFFFFFFE 116 #define CPU_ROM_TABLE_FPB_FPB_S 1 117 118 // Field: [0] FPB_PRESENT 119 // 120 // 0: FPB is not present 121 // 1: FPB is present. 122 #define CPU_ROM_TABLE_FPB_FPB_PRESENT 0x00000001 123 #define CPU_ROM_TABLE_FPB_FPB_PRESENT_BITN 0 124 #define CPU_ROM_TABLE_FPB_FPB_PRESENT_M 0x00000001 125 #define CPU_ROM_TABLE_FPB_FPB_PRESENT_S 0 126 127 //***************************************************************************** 128 // 129 // Register: CPU_ROM_TABLE_O_ITM 130 // 131 //***************************************************************************** 132 // Field: [31:1] ITM 133 // 134 // Points to the Instrumentation Trace block at 0xE0000000. 135 // (2*ITM + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE0000000. 136 #define CPU_ROM_TABLE_ITM_ITM_W 31 137 #define CPU_ROM_TABLE_ITM_ITM_M 0xFFFFFFFE 138 #define CPU_ROM_TABLE_ITM_ITM_S 1 139 140 // Field: [0] ITM_PRESENT 141 // 142 // 0: ITM is not present 143 // 1: ITM is present. 144 #define CPU_ROM_TABLE_ITM_ITM_PRESENT 0x00000001 145 #define CPU_ROM_TABLE_ITM_ITM_PRESENT_BITN 0 146 #define CPU_ROM_TABLE_ITM_ITM_PRESENT_M 0x00000001 147 #define CPU_ROM_TABLE_ITM_ITM_PRESENT_S 0 148 149 //***************************************************************************** 150 // 151 // Register: CPU_ROM_TABLE_O_TPIU 152 // 153 //***************************************************************************** 154 // Field: [31:1] TPIU 155 // 156 // Points to the TPIU. TPIU is at 0xE0040000. 157 // (2*TPIU + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE0040000. 158 #define CPU_ROM_TABLE_TPIU_TPIU_W 31 159 #define CPU_ROM_TABLE_TPIU_TPIU_M 0xFFFFFFFE 160 #define CPU_ROM_TABLE_TPIU_TPIU_S 1 161 162 // Field: [0] TPIU_PRESENT 163 // 164 // 0: TPIU is not present 165 // 1: TPIU is present. 166 #define CPU_ROM_TABLE_TPIU_TPIU_PRESENT 0x00000001 167 #define CPU_ROM_TABLE_TPIU_TPIU_PRESENT_BITN 0 168 #define CPU_ROM_TABLE_TPIU_TPIU_PRESENT_M 0x00000001 169 #define CPU_ROM_TABLE_TPIU_TPIU_PRESENT_S 0 170 171 //***************************************************************************** 172 // 173 // Register: CPU_ROM_TABLE_O_ETM 174 // 175 //***************************************************************************** 176 // Field: [31:1] ETM 177 // 178 // Points to the ETM. ETM is at 0xE0041000. 179 // (2*ETM + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE0041000. 180 #define CPU_ROM_TABLE_ETM_ETM_W 31 181 #define CPU_ROM_TABLE_ETM_ETM_M 0xFFFFFFFE 182 #define CPU_ROM_TABLE_ETM_ETM_S 1 183 184 // Field: [0] ETM_PRESENT 185 // 186 // 0: ETM is not present 187 // 1: ETM is present. 188 #define CPU_ROM_TABLE_ETM_ETM_PRESENT 0x00000001 189 #define CPU_ROM_TABLE_ETM_ETM_PRESENT_BITN 0 190 #define CPU_ROM_TABLE_ETM_ETM_PRESENT_M 0x00000001 191 #define CPU_ROM_TABLE_ETM_ETM_PRESENT_S 0 192 193 //***************************************************************************** 194 // 195 // Register: CPU_ROM_TABLE_O_END 196 // 197 //***************************************************************************** 198 // Field: [31:0] END 199 // 200 // End of the ROM table 201 #define CPU_ROM_TABLE_END_END_W 32 202 #define CPU_ROM_TABLE_END_END_M 0xFFFFFFFF 203 #define CPU_ROM_TABLE_END_END_S 0 204 205 //***************************************************************************** 206 // 207 // Register: CPU_ROM_TABLE_O_SYSTEM_ACCESS 208 // 209 //***************************************************************************** 210 // Field: [0] SYSTEM_ACCESS 211 // 212 // 1: The system memory map is accessible using the DAP 213 // 0: Only debug resources are accessible using the DAP 214 #define CPU_ROM_TABLE_SYSTEM_ACCESS_SYSTEM_ACCESS 0x00000001 215 #define CPU_ROM_TABLE_SYSTEM_ACCESS_SYSTEM_ACCESS_BITN 0 216 #define CPU_ROM_TABLE_SYSTEM_ACCESS_SYSTEM_ACCESS_M 0x00000001 217 #define CPU_ROM_TABLE_SYSTEM_ACCESS_SYSTEM_ACCESS_S 0 218 219 220 #endif // __CPU_ROM_TABLE__ 221