1 /****************************************************************************** 2 * Filename: hw_cpu_scs_h 3 * Revised: 2015-11-12 13:07:02 +0100 (Thu, 12 Nov 2015) 4 * Revision: 45056 5 * 6 * Copyright (c) 2015, Texas Instruments Incorporated 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions are met: 11 * 12 * 1) Redistributions of source code must retain the above copyright notice, 13 * this list of conditions and the following disclaimer. 14 * 15 * 2) Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 19 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may 20 * be used to endorse or promote products derived from this software without 21 * specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 * 35 ******************************************************************************/ 36 37 #ifndef __HW_CPU_SCS_H__ 38 #define __HW_CPU_SCS_H__ 39 40 //***************************************************************************** 41 // 42 // This section defines the register offsets of 43 // CPU_SCS component 44 // 45 //***************************************************************************** 46 // Interrupt Control Type 47 #define CPU_SCS_O_ICTR 0x00000004 48 49 // Auxiliary Control 50 #define CPU_SCS_O_ACTLR 0x00000008 51 52 // SysTick Control and Status 53 #define CPU_SCS_O_STCSR 0x00000010 54 55 // SysTick Reload Value 56 #define CPU_SCS_O_STRVR 0x00000014 57 58 // SysTick Current Value 59 #define CPU_SCS_O_STCVR 0x00000018 60 61 // SysTick Calibration Value 62 #define CPU_SCS_O_STCR 0x0000001C 63 64 // Irq 0 to 31 Set Enable 65 #define CPU_SCS_O_NVIC_ISER0 0x00000100 66 67 // Irq 32 to 63 Set Enable 68 #define CPU_SCS_O_NVIC_ISER1 0x00000104 69 70 // Irq 0 to 31 Clear Enable 71 #define CPU_SCS_O_NVIC_ICER0 0x00000180 72 73 // Irq 32 to 63 Clear Enable 74 #define CPU_SCS_O_NVIC_ICER1 0x00000184 75 76 // Irq 0 to 31 Set Pending 77 #define CPU_SCS_O_NVIC_ISPR0 0x00000200 78 79 // Irq 32 to 63 Set Pending 80 #define CPU_SCS_O_NVIC_ISPR1 0x00000204 81 82 // Irq 0 to 31 Clear Pending 83 #define CPU_SCS_O_NVIC_ICPR0 0x00000280 84 85 // Irq 32 to 63 Clear Pending 86 #define CPU_SCS_O_NVIC_ICPR1 0x00000284 87 88 // Irq 0 to 31 Active Bit 89 #define CPU_SCS_O_NVIC_IABR0 0x00000300 90 91 // Irq 32 to 63 Active Bit 92 #define CPU_SCS_O_NVIC_IABR1 0x00000304 93 94 // Irq 0 to 3 Priority 95 #define CPU_SCS_O_NVIC_IPR0 0x00000400 96 97 // Irq 4 to 7 Priority 98 #define CPU_SCS_O_NVIC_IPR1 0x00000404 99 100 // Irq 8 to 11 Priority 101 #define CPU_SCS_O_NVIC_IPR2 0x00000408 102 103 // Irq 12 to 15 Priority 104 #define CPU_SCS_O_NVIC_IPR3 0x0000040C 105 106 // Irq 16 to 19 Priority 107 #define CPU_SCS_O_NVIC_IPR4 0x00000410 108 109 // Irq 20 to 23 Priority 110 #define CPU_SCS_O_NVIC_IPR5 0x00000414 111 112 // Irq 24 to 27 Priority 113 #define CPU_SCS_O_NVIC_IPR6 0x00000418 114 115 // Irq 28 to 31 Priority 116 #define CPU_SCS_O_NVIC_IPR7 0x0000041C 117 118 // Irq 32 to 35 Priority 119 #define CPU_SCS_O_NVIC_IPR8 0x00000420 120 121 // CPUID Base 122 #define CPU_SCS_O_CPUID 0x00000D00 123 124 // Interrupt Control State 125 #define CPU_SCS_O_ICSR 0x00000D04 126 127 // Vector Table Offset 128 #define CPU_SCS_O_VTOR 0x00000D08 129 130 // Application Interrupt/Reset Control 131 #define CPU_SCS_O_AIRCR 0x00000D0C 132 133 // System Control 134 #define CPU_SCS_O_SCR 0x00000D10 135 136 // Configuration Control 137 #define CPU_SCS_O_CCR 0x00000D14 138 139 // System Handlers 4-7 Priority 140 #define CPU_SCS_O_SHPR1 0x00000D18 141 142 // System Handlers 8-11 Priority 143 #define CPU_SCS_O_SHPR2 0x00000D1C 144 145 // System Handlers 12-15 Priority 146 #define CPU_SCS_O_SHPR3 0x00000D20 147 148 // System Handler Control and State 149 #define CPU_SCS_O_SHCSR 0x00000D24 150 151 // Configurable Fault Status 152 #define CPU_SCS_O_CFSR 0x00000D28 153 154 // Hard Fault Status 155 #define CPU_SCS_O_HFSR 0x00000D2C 156 157 // Debug Fault Status 158 #define CPU_SCS_O_DFSR 0x00000D30 159 160 // Mem Manage Fault Address 161 #define CPU_SCS_O_MMFAR 0x00000D34 162 163 // Bus Fault Address 164 #define CPU_SCS_O_BFAR 0x00000D38 165 166 // Auxiliary Fault Status 167 #define CPU_SCS_O_AFSR 0x00000D3C 168 169 // Processor Feature 0 170 #define CPU_SCS_O_ID_PFR0 0x00000D40 171 172 // Processor Feature 1 173 #define CPU_SCS_O_ID_PFR1 0x00000D44 174 175 // Debug Feature 0 176 #define CPU_SCS_O_ID_DFR0 0x00000D48 177 178 // Auxiliary Feature 0 179 #define CPU_SCS_O_ID_AFR0 0x00000D4C 180 181 // Memory Model Feature 0 182 #define CPU_SCS_O_ID_MMFR0 0x00000D50 183 184 // Memory Model Feature 1 185 #define CPU_SCS_O_ID_MMFR1 0x00000D54 186 187 // Memory Model Feature 2 188 #define CPU_SCS_O_ID_MMFR2 0x00000D58 189 190 // Memory Model Feature 3 191 #define CPU_SCS_O_ID_MMFR3 0x00000D5C 192 193 // ISA Feature 0 194 #define CPU_SCS_O_ID_ISAR0 0x00000D60 195 196 // ISA Feature 1 197 #define CPU_SCS_O_ID_ISAR1 0x00000D64 198 199 // ISA Feature 2 200 #define CPU_SCS_O_ID_ISAR2 0x00000D68 201 202 // ISA Feature 3 203 #define CPU_SCS_O_ID_ISAR3 0x00000D6C 204 205 // ISA Feature 4 206 #define CPU_SCS_O_ID_ISAR4 0x00000D70 207 208 // Coprocessor Access Control 209 #define CPU_SCS_O_CPACR 0x00000D88 210 211 // Debug Halting Control and Status 212 #define CPU_SCS_O_DHCSR 0x00000DF0 213 214 // Deubg Core Register Selector 215 #define CPU_SCS_O_DCRSR 0x00000DF4 216 217 // Debug Core Register Data 218 #define CPU_SCS_O_DCRDR 0x00000DF8 219 220 // Debug Exception and Monitor Control 221 #define CPU_SCS_O_DEMCR 0x00000DFC 222 223 // Software Trigger Interrupt 224 #define CPU_SCS_O_STIR 0x00000F00 225 226 //***************************************************************************** 227 // 228 // Register: CPU_SCS_O_ICTR 229 // 230 //***************************************************************************** 231 // Field: [2:0] INTLINESNUM 232 // 233 // Total number of interrupt lines in groups of 32. 234 // 235 // 0: 0...32 236 // 1: 33...64 237 // 2: 65...96 238 // 3: 97...128 239 // 4: 129...160 240 // 5: 161...192 241 // 6: 193...224 242 // 7: 225...256 243 #define CPU_SCS_ICTR_INTLINESNUM_W 3 244 #define CPU_SCS_ICTR_INTLINESNUM_M 0x00000007 245 #define CPU_SCS_ICTR_INTLINESNUM_S 0 246 247 //***************************************************************************** 248 // 249 // Register: CPU_SCS_O_ACTLR 250 // 251 //***************************************************************************** 252 // Field: [2] DISFOLD 253 // 254 // Disables folding of IT instruction. 255 #define CPU_SCS_ACTLR_DISFOLD 0x00000004 256 #define CPU_SCS_ACTLR_DISFOLD_BITN 2 257 #define CPU_SCS_ACTLR_DISFOLD_M 0x00000004 258 #define CPU_SCS_ACTLR_DISFOLD_S 2 259 260 // Field: [1] DISDEFWBUF 261 // 262 // Disables write buffer use during default memory map accesses. This causes 263 // all bus faults to be precise bus faults but decreases the performance of the 264 // processor because the stores to memory have to complete before the next 265 // instruction can be executed. 266 #define CPU_SCS_ACTLR_DISDEFWBUF 0x00000002 267 #define CPU_SCS_ACTLR_DISDEFWBUF_BITN 1 268 #define CPU_SCS_ACTLR_DISDEFWBUF_M 0x00000002 269 #define CPU_SCS_ACTLR_DISDEFWBUF_S 1 270 271 // Field: [0] DISMCYCINT 272 // 273 // Disables interruption of multi-cycle instructions. This increases the 274 // interrupt latency of the processor becuase LDM/STM completes before 275 // interrupt stacking occurs. 276 #define CPU_SCS_ACTLR_DISMCYCINT 0x00000001 277 #define CPU_SCS_ACTLR_DISMCYCINT_BITN 0 278 #define CPU_SCS_ACTLR_DISMCYCINT_M 0x00000001 279 #define CPU_SCS_ACTLR_DISMCYCINT_S 0 280 281 //***************************************************************************** 282 // 283 // Register: CPU_SCS_O_STCSR 284 // 285 //***************************************************************************** 286 // Field: [16] COUNTFLAG 287 // 288 // Returns 1 if timer counted to 0 since last time this was read. Clears on 289 // read by application of any part of the SysTick Control and Status Register. 290 // If read by the debugger using the DAP, this bit is cleared on read-only if 291 // the MasterType bit in the **AHB-AP** Control Register is set to 0. 292 // Otherwise, COUNTFLAG is not changed by the debugger read. 293 #define CPU_SCS_STCSR_COUNTFLAG 0x00010000 294 #define CPU_SCS_STCSR_COUNTFLAG_BITN 16 295 #define CPU_SCS_STCSR_COUNTFLAG_M 0x00010000 296 #define CPU_SCS_STCSR_COUNTFLAG_S 16 297 298 // Field: [2] CLKSOURCE 299 // 300 // Clock source: 301 // 302 // 0: External reference clock. 303 // 1: Core clock 304 // 305 // External clock is not available in this device. Writes to this field will be 306 // ignored. 307 #define CPU_SCS_STCSR_CLKSOURCE 0x00000004 308 #define CPU_SCS_STCSR_CLKSOURCE_BITN 2 309 #define CPU_SCS_STCSR_CLKSOURCE_M 0x00000004 310 #define CPU_SCS_STCSR_CLKSOURCE_S 2 311 312 // Field: [1] TICKINT 313 // 314 // 0: Counting down to zero does not pend the SysTick handler. Software can use 315 // COUNTFLAG to determine if the SysTick handler has ever counted to zero. 316 // 1: Counting down to zero pends the SysTick handler. 317 #define CPU_SCS_STCSR_TICKINT 0x00000002 318 #define CPU_SCS_STCSR_TICKINT_BITN 1 319 #define CPU_SCS_STCSR_TICKINT_M 0x00000002 320 #define CPU_SCS_STCSR_TICKINT_S 1 321 322 // Field: [0] ENABLE 323 // 324 // Enable SysTick counter 325 // 326 // 0: Counter disabled 327 // 1: Counter operates in a multi-shot way. That is, counter loads with the 328 // Reload value STRVR.RELOAD and then begins counting down. On reaching 0, it 329 // sets COUNTFLAG to 1 and optionally pends the SysTick handler, based on 330 // TICKINT. It then loads STRVR.RELOAD again, and begins counting. 331 #define CPU_SCS_STCSR_ENABLE 0x00000001 332 #define CPU_SCS_STCSR_ENABLE_BITN 0 333 #define CPU_SCS_STCSR_ENABLE_M 0x00000001 334 #define CPU_SCS_STCSR_ENABLE_S 0 335 336 //***************************************************************************** 337 // 338 // Register: CPU_SCS_O_STRVR 339 // 340 //***************************************************************************** 341 // Field: [23:0] RELOAD 342 // 343 // Value to load into the SysTick Current Value Register STCVR.CURRENT when the 344 // counter reaches 0. 345 #define CPU_SCS_STRVR_RELOAD_W 24 346 #define CPU_SCS_STRVR_RELOAD_M 0x00FFFFFF 347 #define CPU_SCS_STRVR_RELOAD_S 0 348 349 //***************************************************************************** 350 // 351 // Register: CPU_SCS_O_STCVR 352 // 353 //***************************************************************************** 354 // Field: [23:0] CURRENT 355 // 356 // Current value at the time the register is accessed. No read-modify-write 357 // protection is provided, so change with care. Writing to it with any value 358 // clears the register to 0. Clearing this register also clears 359 // STCSR.COUNTFLAG. 360 #define CPU_SCS_STCVR_CURRENT_W 24 361 #define CPU_SCS_STCVR_CURRENT_M 0x00FFFFFF 362 #define CPU_SCS_STCVR_CURRENT_S 0 363 364 //***************************************************************************** 365 // 366 // Register: CPU_SCS_O_STCR 367 // 368 //***************************************************************************** 369 // Field: [31] NOREF 370 // 371 // Reads as one. Indicates that no separate reference clock is provided. 372 #define CPU_SCS_STCR_NOREF 0x80000000 373 #define CPU_SCS_STCR_NOREF_BITN 31 374 #define CPU_SCS_STCR_NOREF_M 0x80000000 375 #define CPU_SCS_STCR_NOREF_S 31 376 377 // Field: [30] SKEW 378 // 379 // Reads as one. The calibration value is not exactly 10ms because of clock 380 // frequency. This could affect its suitability as a software real time clock. 381 #define CPU_SCS_STCR_SKEW 0x40000000 382 #define CPU_SCS_STCR_SKEW_BITN 30 383 #define CPU_SCS_STCR_SKEW_M 0x40000000 384 #define CPU_SCS_STCR_SKEW_S 30 385 386 // Field: [23:0] TENMS 387 // 388 // An optional Reload value to be used for 10ms (100Hz) timing, subject to 389 // system clock skew errors. The value read is valid only when core clock is at 390 // 48MHz. 391 #define CPU_SCS_STCR_TENMS_W 24 392 #define CPU_SCS_STCR_TENMS_M 0x00FFFFFF 393 #define CPU_SCS_STCR_TENMS_S 0 394 395 //***************************************************************************** 396 // 397 // Register: CPU_SCS_O_NVIC_ISER0 398 // 399 //***************************************************************************** 400 // Field: [31] SETENA31 401 // 402 // Writing 0 to this bit has no effect, writing 1 to this bit enables the 403 // interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details). Reading the bit 404 // returns its current enable state. 405 #define CPU_SCS_NVIC_ISER0_SETENA31 0x80000000 406 #define CPU_SCS_NVIC_ISER0_SETENA31_BITN 31 407 #define CPU_SCS_NVIC_ISER0_SETENA31_M 0x80000000 408 #define CPU_SCS_NVIC_ISER0_SETENA31_S 31 409 410 // Field: [30] SETENA30 411 // 412 // Writing 0 to this bit has no effect, writing 1 to this bit enables the 413 // interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details). Reading the bit 414 // returns its current enable state. 415 #define CPU_SCS_NVIC_ISER0_SETENA30 0x40000000 416 #define CPU_SCS_NVIC_ISER0_SETENA30_BITN 30 417 #define CPU_SCS_NVIC_ISER0_SETENA30_M 0x40000000 418 #define CPU_SCS_NVIC_ISER0_SETENA30_S 30 419 420 // Field: [29] SETENA29 421 // 422 // Writing 0 to this bit has no effect, writing 1 to this bit enables the 423 // interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details). Reading the bit 424 // returns its current enable state. 425 #define CPU_SCS_NVIC_ISER0_SETENA29 0x20000000 426 #define CPU_SCS_NVIC_ISER0_SETENA29_BITN 29 427 #define CPU_SCS_NVIC_ISER0_SETENA29_M 0x20000000 428 #define CPU_SCS_NVIC_ISER0_SETENA29_S 29 429 430 // Field: [28] SETENA28 431 // 432 // Writing 0 to this bit has no effect, writing 1 to this bit enables the 433 // interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details). Reading the bit 434 // returns its current enable state. 435 #define CPU_SCS_NVIC_ISER0_SETENA28 0x10000000 436 #define CPU_SCS_NVIC_ISER0_SETENA28_BITN 28 437 #define CPU_SCS_NVIC_ISER0_SETENA28_M 0x10000000 438 #define CPU_SCS_NVIC_ISER0_SETENA28_S 28 439 440 // Field: [27] SETENA27 441 // 442 // Writing 0 to this bit has no effect, writing 1 to this bit enables the 443 // interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details). Reading the bit 444 // returns its current enable state. 445 #define CPU_SCS_NVIC_ISER0_SETENA27 0x08000000 446 #define CPU_SCS_NVIC_ISER0_SETENA27_BITN 27 447 #define CPU_SCS_NVIC_ISER0_SETENA27_M 0x08000000 448 #define CPU_SCS_NVIC_ISER0_SETENA27_S 27 449 450 // Field: [26] SETENA26 451 // 452 // Writing 0 to this bit has no effect, writing 1 to this bit enables the 453 // interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details). Reading the bit 454 // returns its current enable state. 455 #define CPU_SCS_NVIC_ISER0_SETENA26 0x04000000 456 #define CPU_SCS_NVIC_ISER0_SETENA26_BITN 26 457 #define CPU_SCS_NVIC_ISER0_SETENA26_M 0x04000000 458 #define CPU_SCS_NVIC_ISER0_SETENA26_S 26 459 460 // Field: [25] SETENA25 461 // 462 // Writing 0 to this bit has no effect, writing 1 to this bit enables the 463 // interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details). Reading the bit 464 // returns its current enable state. 465 #define CPU_SCS_NVIC_ISER0_SETENA25 0x02000000 466 #define CPU_SCS_NVIC_ISER0_SETENA25_BITN 25 467 #define CPU_SCS_NVIC_ISER0_SETENA25_M 0x02000000 468 #define CPU_SCS_NVIC_ISER0_SETENA25_S 25 469 470 // Field: [24] SETENA24 471 // 472 // Writing 0 to this bit has no effect, writing 1 to this bit enables the 473 // interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details). Reading the bit 474 // returns its current enable state. 475 #define CPU_SCS_NVIC_ISER0_SETENA24 0x01000000 476 #define CPU_SCS_NVIC_ISER0_SETENA24_BITN 24 477 #define CPU_SCS_NVIC_ISER0_SETENA24_M 0x01000000 478 #define CPU_SCS_NVIC_ISER0_SETENA24_S 24 479 480 // Field: [23] SETENA23 481 // 482 // Writing 0 to this bit has no effect, writing 1 to this bit enables the 483 // interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details). Reading the bit 484 // returns its current enable state. 485 #define CPU_SCS_NVIC_ISER0_SETENA23 0x00800000 486 #define CPU_SCS_NVIC_ISER0_SETENA23_BITN 23 487 #define CPU_SCS_NVIC_ISER0_SETENA23_M 0x00800000 488 #define CPU_SCS_NVIC_ISER0_SETENA23_S 23 489 490 // Field: [22] SETENA22 491 // 492 // Writing 0 to this bit has no effect, writing 1 to this bit enables the 493 // interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details). Reading the bit 494 // returns its current enable state. 495 #define CPU_SCS_NVIC_ISER0_SETENA22 0x00400000 496 #define CPU_SCS_NVIC_ISER0_SETENA22_BITN 22 497 #define CPU_SCS_NVIC_ISER0_SETENA22_M 0x00400000 498 #define CPU_SCS_NVIC_ISER0_SETENA22_S 22 499 500 // Field: [21] SETENA21 501 // 502 // Writing 0 to this bit has no effect, writing 1 to this bit enables the 503 // interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit 504 // returns its current enable state. 505 #define CPU_SCS_NVIC_ISER0_SETENA21 0x00200000 506 #define CPU_SCS_NVIC_ISER0_SETENA21_BITN 21 507 #define CPU_SCS_NVIC_ISER0_SETENA21_M 0x00200000 508 #define CPU_SCS_NVIC_ISER0_SETENA21_S 21 509 510 // Field: [20] SETENA20 511 // 512 // Writing 0 to this bit has no effect, writing 1 to this bit enables the 513 // interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details). Reading the bit 514 // returns its current enable state. 515 #define CPU_SCS_NVIC_ISER0_SETENA20 0x00100000 516 #define CPU_SCS_NVIC_ISER0_SETENA20_BITN 20 517 #define CPU_SCS_NVIC_ISER0_SETENA20_M 0x00100000 518 #define CPU_SCS_NVIC_ISER0_SETENA20_S 20 519 520 // Field: [19] SETENA19 521 // 522 // Writing 0 to this bit has no effect, writing 1 to this bit enables the 523 // interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details). Reading the bit 524 // returns its current enable state. 525 #define CPU_SCS_NVIC_ISER0_SETENA19 0x00080000 526 #define CPU_SCS_NVIC_ISER0_SETENA19_BITN 19 527 #define CPU_SCS_NVIC_ISER0_SETENA19_M 0x00080000 528 #define CPU_SCS_NVIC_ISER0_SETENA19_S 19 529 530 // Field: [18] SETENA18 531 // 532 // Writing 0 to this bit has no effect, writing 1 to this bit enables the 533 // interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details). Reading the bit 534 // returns its current enable state. 535 #define CPU_SCS_NVIC_ISER0_SETENA18 0x00040000 536 #define CPU_SCS_NVIC_ISER0_SETENA18_BITN 18 537 #define CPU_SCS_NVIC_ISER0_SETENA18_M 0x00040000 538 #define CPU_SCS_NVIC_ISER0_SETENA18_S 18 539 540 // Field: [17] SETENA17 541 // 542 // Writing 0 to this bit has no effect, writing 1 to this bit enables the 543 // interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details). Reading the bit 544 // returns its current enable state. 545 #define CPU_SCS_NVIC_ISER0_SETENA17 0x00020000 546 #define CPU_SCS_NVIC_ISER0_SETENA17_BITN 17 547 #define CPU_SCS_NVIC_ISER0_SETENA17_M 0x00020000 548 #define CPU_SCS_NVIC_ISER0_SETENA17_S 17 549 550 // Field: [16] SETENA16 551 // 552 // Writing 0 to this bit has no effect, writing 1 to this bit enables the 553 // interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details). Reading the bit 554 // returns its current enable state. 555 #define CPU_SCS_NVIC_ISER0_SETENA16 0x00010000 556 #define CPU_SCS_NVIC_ISER0_SETENA16_BITN 16 557 #define CPU_SCS_NVIC_ISER0_SETENA16_M 0x00010000 558 #define CPU_SCS_NVIC_ISER0_SETENA16_S 16 559 560 // Field: [15] SETENA15 561 // 562 // Writing 0 to this bit has no effect, writing 1 to this bit enables the 563 // interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details). Reading the bit 564 // returns its current enable state. 565 #define CPU_SCS_NVIC_ISER0_SETENA15 0x00008000 566 #define CPU_SCS_NVIC_ISER0_SETENA15_BITN 15 567 #define CPU_SCS_NVIC_ISER0_SETENA15_M 0x00008000 568 #define CPU_SCS_NVIC_ISER0_SETENA15_S 15 569 570 // Field: [14] SETENA14 571 // 572 // Writing 0 to this bit has no effect, writing 1 to this bit enables the 573 // interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details). Reading the bit 574 // returns its current enable state. 575 #define CPU_SCS_NVIC_ISER0_SETENA14 0x00004000 576 #define CPU_SCS_NVIC_ISER0_SETENA14_BITN 14 577 #define CPU_SCS_NVIC_ISER0_SETENA14_M 0x00004000 578 #define CPU_SCS_NVIC_ISER0_SETENA14_S 14 579 580 // Field: [13] SETENA13 581 // 582 // Writing 0 to this bit has no effect, writing 1 to this bit enables the 583 // interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details). Reading the bit 584 // returns its current enable state. 585 #define CPU_SCS_NVIC_ISER0_SETENA13 0x00002000 586 #define CPU_SCS_NVIC_ISER0_SETENA13_BITN 13 587 #define CPU_SCS_NVIC_ISER0_SETENA13_M 0x00002000 588 #define CPU_SCS_NVIC_ISER0_SETENA13_S 13 589 590 // Field: [12] SETENA12 591 // 592 // Writing 0 to this bit has no effect, writing 1 to this bit enables the 593 // interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details). Reading the bit 594 // returns its current enable state. 595 #define CPU_SCS_NVIC_ISER0_SETENA12 0x00001000 596 #define CPU_SCS_NVIC_ISER0_SETENA12_BITN 12 597 #define CPU_SCS_NVIC_ISER0_SETENA12_M 0x00001000 598 #define CPU_SCS_NVIC_ISER0_SETENA12_S 12 599 600 // Field: [11] SETENA11 601 // 602 // Writing 0 to this bit has no effect, writing 1 to this bit enables the 603 // interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details). Reading the bit 604 // returns its current enable state. 605 #define CPU_SCS_NVIC_ISER0_SETENA11 0x00000800 606 #define CPU_SCS_NVIC_ISER0_SETENA11_BITN 11 607 #define CPU_SCS_NVIC_ISER0_SETENA11_M 0x00000800 608 #define CPU_SCS_NVIC_ISER0_SETENA11_S 11 609 610 // Field: [10] SETENA10 611 // 612 // Writing 0 to this bit has no effect, writing 1 to this bit enables the 613 // interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details). Reading the bit 614 // returns its current enable state. 615 #define CPU_SCS_NVIC_ISER0_SETENA10 0x00000400 616 #define CPU_SCS_NVIC_ISER0_SETENA10_BITN 10 617 #define CPU_SCS_NVIC_ISER0_SETENA10_M 0x00000400 618 #define CPU_SCS_NVIC_ISER0_SETENA10_S 10 619 620 // Field: [9] SETENA9 621 // 622 // Writing 0 to this bit has no effect, writing 1 to this bit enables the 623 // interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details). Reading the bit 624 // returns its current enable state. 625 #define CPU_SCS_NVIC_ISER0_SETENA9 0x00000200 626 #define CPU_SCS_NVIC_ISER0_SETENA9_BITN 9 627 #define CPU_SCS_NVIC_ISER0_SETENA9_M 0x00000200 628 #define CPU_SCS_NVIC_ISER0_SETENA9_S 9 629 630 // Field: [8] SETENA8 631 // 632 // Writing 0 to this bit has no effect, writing 1 to this bit enables the 633 // interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details). Reading the bit 634 // returns its current enable state. 635 #define CPU_SCS_NVIC_ISER0_SETENA8 0x00000100 636 #define CPU_SCS_NVIC_ISER0_SETENA8_BITN 8 637 #define CPU_SCS_NVIC_ISER0_SETENA8_M 0x00000100 638 #define CPU_SCS_NVIC_ISER0_SETENA8_S 8 639 640 // Field: [7] SETENA7 641 // 642 // Writing 0 to this bit has no effect, writing 1 to this bit enables the 643 // interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details). Reading the bit 644 // returns its current enable state. 645 #define CPU_SCS_NVIC_ISER0_SETENA7 0x00000080 646 #define CPU_SCS_NVIC_ISER0_SETENA7_BITN 7 647 #define CPU_SCS_NVIC_ISER0_SETENA7_M 0x00000080 648 #define CPU_SCS_NVIC_ISER0_SETENA7_S 7 649 650 // Field: [6] SETENA6 651 // 652 // Writing 0 to this bit has no effect, writing 1 to this bit enables the 653 // interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details). Reading the bit 654 // returns its current enable state. 655 #define CPU_SCS_NVIC_ISER0_SETENA6 0x00000040 656 #define CPU_SCS_NVIC_ISER0_SETENA6_BITN 6 657 #define CPU_SCS_NVIC_ISER0_SETENA6_M 0x00000040 658 #define CPU_SCS_NVIC_ISER0_SETENA6_S 6 659 660 // Field: [5] SETENA5 661 // 662 // Writing 0 to this bit has no effect, writing 1 to this bit enables the 663 // interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details). Reading the bit 664 // returns its current enable state. 665 #define CPU_SCS_NVIC_ISER0_SETENA5 0x00000020 666 #define CPU_SCS_NVIC_ISER0_SETENA5_BITN 5 667 #define CPU_SCS_NVIC_ISER0_SETENA5_M 0x00000020 668 #define CPU_SCS_NVIC_ISER0_SETENA5_S 5 669 670 // Field: [4] SETENA4 671 // 672 // Writing 0 to this bit has no effect, writing 1 to this bit enables the 673 // interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details). Reading the bit 674 // returns its current enable state. 675 #define CPU_SCS_NVIC_ISER0_SETENA4 0x00000010 676 #define CPU_SCS_NVIC_ISER0_SETENA4_BITN 4 677 #define CPU_SCS_NVIC_ISER0_SETENA4_M 0x00000010 678 #define CPU_SCS_NVIC_ISER0_SETENA4_S 4 679 680 // Field: [3] SETENA3 681 // 682 // Writing 0 to this bit has no effect, writing 1 to this bit enables the 683 // interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit 684 // returns its current enable state. 685 #define CPU_SCS_NVIC_ISER0_SETENA3 0x00000008 686 #define CPU_SCS_NVIC_ISER0_SETENA3_BITN 3 687 #define CPU_SCS_NVIC_ISER0_SETENA3_M 0x00000008 688 #define CPU_SCS_NVIC_ISER0_SETENA3_S 3 689 690 // Field: [2] SETENA2 691 // 692 // Writing 0 to this bit has no effect, writing 1 to this bit enables the 693 // interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details). Reading the bit 694 // returns its current enable state. 695 #define CPU_SCS_NVIC_ISER0_SETENA2 0x00000004 696 #define CPU_SCS_NVIC_ISER0_SETENA2_BITN 2 697 #define CPU_SCS_NVIC_ISER0_SETENA2_M 0x00000004 698 #define CPU_SCS_NVIC_ISER0_SETENA2_S 2 699 700 // Field: [1] SETENA1 701 // 702 // Writing 0 to this bit has no effect, writing 1 to this bit enables the 703 // interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details). Reading the bit 704 // returns its current enable state. 705 #define CPU_SCS_NVIC_ISER0_SETENA1 0x00000002 706 #define CPU_SCS_NVIC_ISER0_SETENA1_BITN 1 707 #define CPU_SCS_NVIC_ISER0_SETENA1_M 0x00000002 708 #define CPU_SCS_NVIC_ISER0_SETENA1_S 1 709 710 // Field: [0] SETENA0 711 // 712 // Writing 0 to this bit has no effect, writing 1 to this bit enables the 713 // interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit 714 // returns its current enable state. 715 #define CPU_SCS_NVIC_ISER0_SETENA0 0x00000001 716 #define CPU_SCS_NVIC_ISER0_SETENA0_BITN 0 717 #define CPU_SCS_NVIC_ISER0_SETENA0_M 0x00000001 718 #define CPU_SCS_NVIC_ISER0_SETENA0_S 0 719 720 //***************************************************************************** 721 // 722 // Register: CPU_SCS_O_NVIC_ISER1 723 // 724 //***************************************************************************** 725 // Field: [1] SETENA33 726 // 727 // Writing 0 to this bit has no effect, writing 1 to this bit enables the 728 // interrupt number 33 (See EVENT:CPUIRQSEL33.EV for details). Reading the bit 729 // returns its current enable state. 730 #define CPU_SCS_NVIC_ISER1_SETENA33 0x00000002 731 #define CPU_SCS_NVIC_ISER1_SETENA33_BITN 1 732 #define CPU_SCS_NVIC_ISER1_SETENA33_M 0x00000002 733 #define CPU_SCS_NVIC_ISER1_SETENA33_S 1 734 735 // Field: [0] SETENA32 736 // 737 // Writing 0 to this bit has no effect, writing 1 to this bit enables the 738 // interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details). Reading the bit 739 // returns its current enable state. 740 #define CPU_SCS_NVIC_ISER1_SETENA32 0x00000001 741 #define CPU_SCS_NVIC_ISER1_SETENA32_BITN 0 742 #define CPU_SCS_NVIC_ISER1_SETENA32_M 0x00000001 743 #define CPU_SCS_NVIC_ISER1_SETENA32_S 0 744 745 //***************************************************************************** 746 // 747 // Register: CPU_SCS_O_NVIC_ICER0 748 // 749 //***************************************************************************** 750 // Field: [31] CLRENA31 751 // 752 // Writing 0 to this bit has no effect, writing 1 to this bit disables the 753 // interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details). Reading the bit 754 // returns its current enable state. 755 #define CPU_SCS_NVIC_ICER0_CLRENA31 0x80000000 756 #define CPU_SCS_NVIC_ICER0_CLRENA31_BITN 31 757 #define CPU_SCS_NVIC_ICER0_CLRENA31_M 0x80000000 758 #define CPU_SCS_NVIC_ICER0_CLRENA31_S 31 759 760 // Field: [30] CLRENA30 761 // 762 // Writing 0 to this bit has no effect, writing 1 to this bit disables the 763 // interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details). Reading the bit 764 // returns its current enable state. 765 #define CPU_SCS_NVIC_ICER0_CLRENA30 0x40000000 766 #define CPU_SCS_NVIC_ICER0_CLRENA30_BITN 30 767 #define CPU_SCS_NVIC_ICER0_CLRENA30_M 0x40000000 768 #define CPU_SCS_NVIC_ICER0_CLRENA30_S 30 769 770 // Field: [29] CLRENA29 771 // 772 // Writing 0 to this bit has no effect, writing 1 to this bit disables the 773 // interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details). Reading the bit 774 // returns its current enable state. 775 #define CPU_SCS_NVIC_ICER0_CLRENA29 0x20000000 776 #define CPU_SCS_NVIC_ICER0_CLRENA29_BITN 29 777 #define CPU_SCS_NVIC_ICER0_CLRENA29_M 0x20000000 778 #define CPU_SCS_NVIC_ICER0_CLRENA29_S 29 779 780 // Field: [28] CLRENA28 781 // 782 // Writing 0 to this bit has no effect, writing 1 to this bit disables the 783 // interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details). Reading the bit 784 // returns its current enable state. 785 #define CPU_SCS_NVIC_ICER0_CLRENA28 0x10000000 786 #define CPU_SCS_NVIC_ICER0_CLRENA28_BITN 28 787 #define CPU_SCS_NVIC_ICER0_CLRENA28_M 0x10000000 788 #define CPU_SCS_NVIC_ICER0_CLRENA28_S 28 789 790 // Field: [27] CLRENA27 791 // 792 // Writing 0 to this bit has no effect, writing 1 to this bit disables the 793 // interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details). Reading the bit 794 // returns its current enable state. 795 #define CPU_SCS_NVIC_ICER0_CLRENA27 0x08000000 796 #define CPU_SCS_NVIC_ICER0_CLRENA27_BITN 27 797 #define CPU_SCS_NVIC_ICER0_CLRENA27_M 0x08000000 798 #define CPU_SCS_NVIC_ICER0_CLRENA27_S 27 799 800 // Field: [26] CLRENA26 801 // 802 // Writing 0 to this bit has no effect, writing 1 to this bit disables the 803 // interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details). Reading the bit 804 // returns its current enable state. 805 #define CPU_SCS_NVIC_ICER0_CLRENA26 0x04000000 806 #define CPU_SCS_NVIC_ICER0_CLRENA26_BITN 26 807 #define CPU_SCS_NVIC_ICER0_CLRENA26_M 0x04000000 808 #define CPU_SCS_NVIC_ICER0_CLRENA26_S 26 809 810 // Field: [25] CLRENA25 811 // 812 // Writing 0 to this bit has no effect, writing 1 to this bit disables the 813 // interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details). Reading the bit 814 // returns its current enable state. 815 #define CPU_SCS_NVIC_ICER0_CLRENA25 0x02000000 816 #define CPU_SCS_NVIC_ICER0_CLRENA25_BITN 25 817 #define CPU_SCS_NVIC_ICER0_CLRENA25_M 0x02000000 818 #define CPU_SCS_NVIC_ICER0_CLRENA25_S 25 819 820 // Field: [24] CLRENA24 821 // 822 // Writing 0 to this bit has no effect, writing 1 to this bit disables the 823 // interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details). Reading the bit 824 // returns its current enable state. 825 #define CPU_SCS_NVIC_ICER0_CLRENA24 0x01000000 826 #define CPU_SCS_NVIC_ICER0_CLRENA24_BITN 24 827 #define CPU_SCS_NVIC_ICER0_CLRENA24_M 0x01000000 828 #define CPU_SCS_NVIC_ICER0_CLRENA24_S 24 829 830 // Field: [23] CLRENA23 831 // 832 // Writing 0 to this bit has no effect, writing 1 to this bit disables the 833 // interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details). Reading the bit 834 // returns its current enable state. 835 #define CPU_SCS_NVIC_ICER0_CLRENA23 0x00800000 836 #define CPU_SCS_NVIC_ICER0_CLRENA23_BITN 23 837 #define CPU_SCS_NVIC_ICER0_CLRENA23_M 0x00800000 838 #define CPU_SCS_NVIC_ICER0_CLRENA23_S 23 839 840 // Field: [22] CLRENA22 841 // 842 // Writing 0 to this bit has no effect, writing 1 to this bit disables the 843 // interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details). Reading the bit 844 // returns its current enable state. 845 #define CPU_SCS_NVIC_ICER0_CLRENA22 0x00400000 846 #define CPU_SCS_NVIC_ICER0_CLRENA22_BITN 22 847 #define CPU_SCS_NVIC_ICER0_CLRENA22_M 0x00400000 848 #define CPU_SCS_NVIC_ICER0_CLRENA22_S 22 849 850 // Field: [21] CLRENA21 851 // 852 // Writing 0 to this bit has no effect, writing 1 to this bit disables the 853 // interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit 854 // returns its current enable state. 855 #define CPU_SCS_NVIC_ICER0_CLRENA21 0x00200000 856 #define CPU_SCS_NVIC_ICER0_CLRENA21_BITN 21 857 #define CPU_SCS_NVIC_ICER0_CLRENA21_M 0x00200000 858 #define CPU_SCS_NVIC_ICER0_CLRENA21_S 21 859 860 // Field: [20] CLRENA20 861 // 862 // Writing 0 to this bit has no effect, writing 1 to this bit disables the 863 // interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details). Reading the bit 864 // returns its current enable state. 865 #define CPU_SCS_NVIC_ICER0_CLRENA20 0x00100000 866 #define CPU_SCS_NVIC_ICER0_CLRENA20_BITN 20 867 #define CPU_SCS_NVIC_ICER0_CLRENA20_M 0x00100000 868 #define CPU_SCS_NVIC_ICER0_CLRENA20_S 20 869 870 // Field: [19] CLRENA19 871 // 872 // Writing 0 to this bit has no effect, writing 1 to this bit disables the 873 // interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details). Reading the bit 874 // returns its current enable state. 875 #define CPU_SCS_NVIC_ICER0_CLRENA19 0x00080000 876 #define CPU_SCS_NVIC_ICER0_CLRENA19_BITN 19 877 #define CPU_SCS_NVIC_ICER0_CLRENA19_M 0x00080000 878 #define CPU_SCS_NVIC_ICER0_CLRENA19_S 19 879 880 // Field: [18] CLRENA18 881 // 882 // Writing 0 to this bit has no effect, writing 1 to this bit disables the 883 // interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details). Reading the bit 884 // returns its current enable state. 885 #define CPU_SCS_NVIC_ICER0_CLRENA18 0x00040000 886 #define CPU_SCS_NVIC_ICER0_CLRENA18_BITN 18 887 #define CPU_SCS_NVIC_ICER0_CLRENA18_M 0x00040000 888 #define CPU_SCS_NVIC_ICER0_CLRENA18_S 18 889 890 // Field: [17] CLRENA17 891 // 892 // Writing 0 to this bit has no effect, writing 1 to this bit disables the 893 // interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details). Reading the bit 894 // returns its current enable state. 895 #define CPU_SCS_NVIC_ICER0_CLRENA17 0x00020000 896 #define CPU_SCS_NVIC_ICER0_CLRENA17_BITN 17 897 #define CPU_SCS_NVIC_ICER0_CLRENA17_M 0x00020000 898 #define CPU_SCS_NVIC_ICER0_CLRENA17_S 17 899 900 // Field: [16] CLRENA16 901 // 902 // Writing 0 to this bit has no effect, writing 1 to this bit disables the 903 // interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details). Reading the bit 904 // returns its current enable state. 905 #define CPU_SCS_NVIC_ICER0_CLRENA16 0x00010000 906 #define CPU_SCS_NVIC_ICER0_CLRENA16_BITN 16 907 #define CPU_SCS_NVIC_ICER0_CLRENA16_M 0x00010000 908 #define CPU_SCS_NVIC_ICER0_CLRENA16_S 16 909 910 // Field: [15] CLRENA15 911 // 912 // Writing 0 to this bit has no effect, writing 1 to this bit disables the 913 // interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details). Reading the bit 914 // returns its current enable state. 915 #define CPU_SCS_NVIC_ICER0_CLRENA15 0x00008000 916 #define CPU_SCS_NVIC_ICER0_CLRENA15_BITN 15 917 #define CPU_SCS_NVIC_ICER0_CLRENA15_M 0x00008000 918 #define CPU_SCS_NVIC_ICER0_CLRENA15_S 15 919 920 // Field: [14] CLRENA14 921 // 922 // Writing 0 to this bit has no effect, writing 1 to this bit disables the 923 // interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details). Reading the bit 924 // returns its current enable state. 925 #define CPU_SCS_NVIC_ICER0_CLRENA14 0x00004000 926 #define CPU_SCS_NVIC_ICER0_CLRENA14_BITN 14 927 #define CPU_SCS_NVIC_ICER0_CLRENA14_M 0x00004000 928 #define CPU_SCS_NVIC_ICER0_CLRENA14_S 14 929 930 // Field: [13] CLRENA13 931 // 932 // Writing 0 to this bit has no effect, writing 1 to this bit disables the 933 // interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details). Reading the bit 934 // returns its current enable state. 935 #define CPU_SCS_NVIC_ICER0_CLRENA13 0x00002000 936 #define CPU_SCS_NVIC_ICER0_CLRENA13_BITN 13 937 #define CPU_SCS_NVIC_ICER0_CLRENA13_M 0x00002000 938 #define CPU_SCS_NVIC_ICER0_CLRENA13_S 13 939 940 // Field: [12] CLRENA12 941 // 942 // Writing 0 to this bit has no effect, writing 1 to this bit disables the 943 // interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details). Reading the bit 944 // returns its current enable state. 945 #define CPU_SCS_NVIC_ICER0_CLRENA12 0x00001000 946 #define CPU_SCS_NVIC_ICER0_CLRENA12_BITN 12 947 #define CPU_SCS_NVIC_ICER0_CLRENA12_M 0x00001000 948 #define CPU_SCS_NVIC_ICER0_CLRENA12_S 12 949 950 // Field: [11] CLRENA11 951 // 952 // Writing 0 to this bit has no effect, writing 1 to this bit disables the 953 // interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details). Reading the bit 954 // returns its current enable state. 955 #define CPU_SCS_NVIC_ICER0_CLRENA11 0x00000800 956 #define CPU_SCS_NVIC_ICER0_CLRENA11_BITN 11 957 #define CPU_SCS_NVIC_ICER0_CLRENA11_M 0x00000800 958 #define CPU_SCS_NVIC_ICER0_CLRENA11_S 11 959 960 // Field: [10] CLRENA10 961 // 962 // Writing 0 to this bit has no effect, writing 1 to this bit disables the 963 // interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details). Reading the bit 964 // returns its current enable state. 965 #define CPU_SCS_NVIC_ICER0_CLRENA10 0x00000400 966 #define CPU_SCS_NVIC_ICER0_CLRENA10_BITN 10 967 #define CPU_SCS_NVIC_ICER0_CLRENA10_M 0x00000400 968 #define CPU_SCS_NVIC_ICER0_CLRENA10_S 10 969 970 // Field: [9] CLRENA9 971 // 972 // Writing 0 to this bit has no effect, writing 1 to this bit disables the 973 // interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details). Reading the bit 974 // returns its current enable state. 975 #define CPU_SCS_NVIC_ICER0_CLRENA9 0x00000200 976 #define CPU_SCS_NVIC_ICER0_CLRENA9_BITN 9 977 #define CPU_SCS_NVIC_ICER0_CLRENA9_M 0x00000200 978 #define CPU_SCS_NVIC_ICER0_CLRENA9_S 9 979 980 // Field: [8] CLRENA8 981 // 982 // Writing 0 to this bit has no effect, writing 1 to this bit disables the 983 // interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details). Reading the bit 984 // returns its current enable state. 985 #define CPU_SCS_NVIC_ICER0_CLRENA8 0x00000100 986 #define CPU_SCS_NVIC_ICER0_CLRENA8_BITN 8 987 #define CPU_SCS_NVIC_ICER0_CLRENA8_M 0x00000100 988 #define CPU_SCS_NVIC_ICER0_CLRENA8_S 8 989 990 // Field: [7] CLRENA7 991 // 992 // Writing 0 to this bit has no effect, writing 1 to this bit disables the 993 // interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details). Reading the bit 994 // returns its current enable state. 995 #define CPU_SCS_NVIC_ICER0_CLRENA7 0x00000080 996 #define CPU_SCS_NVIC_ICER0_CLRENA7_BITN 7 997 #define CPU_SCS_NVIC_ICER0_CLRENA7_M 0x00000080 998 #define CPU_SCS_NVIC_ICER0_CLRENA7_S 7 999 1000 // Field: [6] CLRENA6 1001 // 1002 // Writing 0 to this bit has no effect, writing 1 to this bit disables the 1003 // interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details). Reading the bit 1004 // returns its current enable state. 1005 #define CPU_SCS_NVIC_ICER0_CLRENA6 0x00000040 1006 #define CPU_SCS_NVIC_ICER0_CLRENA6_BITN 6 1007 #define CPU_SCS_NVIC_ICER0_CLRENA6_M 0x00000040 1008 #define CPU_SCS_NVIC_ICER0_CLRENA6_S 6 1009 1010 // Field: [5] CLRENA5 1011 // 1012 // Writing 0 to this bit has no effect, writing 1 to this bit disables the 1013 // interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details). Reading the bit 1014 // returns its current enable state. 1015 #define CPU_SCS_NVIC_ICER0_CLRENA5 0x00000020 1016 #define CPU_SCS_NVIC_ICER0_CLRENA5_BITN 5 1017 #define CPU_SCS_NVIC_ICER0_CLRENA5_M 0x00000020 1018 #define CPU_SCS_NVIC_ICER0_CLRENA5_S 5 1019 1020 // Field: [4] CLRENA4 1021 // 1022 // Writing 0 to this bit has no effect, writing 1 to this bit disables the 1023 // interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details). Reading the bit 1024 // returns its current enable state. 1025 #define CPU_SCS_NVIC_ICER0_CLRENA4 0x00000010 1026 #define CPU_SCS_NVIC_ICER0_CLRENA4_BITN 4 1027 #define CPU_SCS_NVIC_ICER0_CLRENA4_M 0x00000010 1028 #define CPU_SCS_NVIC_ICER0_CLRENA4_S 4 1029 1030 // Field: [3] CLRENA3 1031 // 1032 // Writing 0 to this bit has no effect, writing 1 to this bit disables the 1033 // interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit 1034 // returns its current enable state. 1035 #define CPU_SCS_NVIC_ICER0_CLRENA3 0x00000008 1036 #define CPU_SCS_NVIC_ICER0_CLRENA3_BITN 3 1037 #define CPU_SCS_NVIC_ICER0_CLRENA3_M 0x00000008 1038 #define CPU_SCS_NVIC_ICER0_CLRENA3_S 3 1039 1040 // Field: [2] CLRENA2 1041 // 1042 // Writing 0 to this bit has no effect, writing 1 to this bit disables the 1043 // interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details). Reading the bit 1044 // returns its current enable state. 1045 #define CPU_SCS_NVIC_ICER0_CLRENA2 0x00000004 1046 #define CPU_SCS_NVIC_ICER0_CLRENA2_BITN 2 1047 #define CPU_SCS_NVIC_ICER0_CLRENA2_M 0x00000004 1048 #define CPU_SCS_NVIC_ICER0_CLRENA2_S 2 1049 1050 // Field: [1] CLRENA1 1051 // 1052 // Writing 0 to this bit has no effect, writing 1 to this bit disables the 1053 // interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details). Reading the bit 1054 // returns its current enable state. 1055 #define CPU_SCS_NVIC_ICER0_CLRENA1 0x00000002 1056 #define CPU_SCS_NVIC_ICER0_CLRENA1_BITN 1 1057 #define CPU_SCS_NVIC_ICER0_CLRENA1_M 0x00000002 1058 #define CPU_SCS_NVIC_ICER0_CLRENA1_S 1 1059 1060 // Field: [0] CLRENA0 1061 // 1062 // Writing 0 to this bit has no effect, writing 1 to this bit disables the 1063 // interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit 1064 // returns its current enable state. 1065 #define CPU_SCS_NVIC_ICER0_CLRENA0 0x00000001 1066 #define CPU_SCS_NVIC_ICER0_CLRENA0_BITN 0 1067 #define CPU_SCS_NVIC_ICER0_CLRENA0_M 0x00000001 1068 #define CPU_SCS_NVIC_ICER0_CLRENA0_S 0 1069 1070 //***************************************************************************** 1071 // 1072 // Register: CPU_SCS_O_NVIC_ICER1 1073 // 1074 //***************************************************************************** 1075 // Field: [1] CLRENA33 1076 // 1077 // Writing 0 to this bit has no effect, writing 1 to this bit disables the 1078 // interrupt number 33 (See EVENT:CPUIRQSEL33.EV for details). Reading the bit 1079 // returns its current enable state. 1080 #define CPU_SCS_NVIC_ICER1_CLRENA33 0x00000002 1081 #define CPU_SCS_NVIC_ICER1_CLRENA33_BITN 1 1082 #define CPU_SCS_NVIC_ICER1_CLRENA33_M 0x00000002 1083 #define CPU_SCS_NVIC_ICER1_CLRENA33_S 1 1084 1085 // Field: [0] CLRENA32 1086 // 1087 // Writing 0 to this bit has no effect, writing 1 to this bit disables the 1088 // interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details). Reading the bit 1089 // returns its current enable state. 1090 #define CPU_SCS_NVIC_ICER1_CLRENA32 0x00000001 1091 #define CPU_SCS_NVIC_ICER1_CLRENA32_BITN 0 1092 #define CPU_SCS_NVIC_ICER1_CLRENA32_M 0x00000001 1093 #define CPU_SCS_NVIC_ICER1_CLRENA32_S 0 1094 1095 //***************************************************************************** 1096 // 1097 // Register: CPU_SCS_O_NVIC_ISPR0 1098 // 1099 //***************************************************************************** 1100 // Field: [31] SETPEND31 1101 // 1102 // Writing 0 to this bit has no effect, writing 1 to this bit pends the 1103 // interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details). Reading the bit 1104 // returns its current state. 1105 #define CPU_SCS_NVIC_ISPR0_SETPEND31 0x80000000 1106 #define CPU_SCS_NVIC_ISPR0_SETPEND31_BITN 31 1107 #define CPU_SCS_NVIC_ISPR0_SETPEND31_M 0x80000000 1108 #define CPU_SCS_NVIC_ISPR0_SETPEND31_S 31 1109 1110 // Field: [30] SETPEND30 1111 // 1112 // Writing 0 to this bit has no effect, writing 1 to this bit pends the 1113 // interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details). Reading the bit 1114 // returns its current state. 1115 #define CPU_SCS_NVIC_ISPR0_SETPEND30 0x40000000 1116 #define CPU_SCS_NVIC_ISPR0_SETPEND30_BITN 30 1117 #define CPU_SCS_NVIC_ISPR0_SETPEND30_M 0x40000000 1118 #define CPU_SCS_NVIC_ISPR0_SETPEND30_S 30 1119 1120 // Field: [29] SETPEND29 1121 // 1122 // Writing 0 to this bit has no effect, writing 1 to this bit pends the 1123 // interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details). Reading the bit 1124 // returns its current state. 1125 #define CPU_SCS_NVIC_ISPR0_SETPEND29 0x20000000 1126 #define CPU_SCS_NVIC_ISPR0_SETPEND29_BITN 29 1127 #define CPU_SCS_NVIC_ISPR0_SETPEND29_M 0x20000000 1128 #define CPU_SCS_NVIC_ISPR0_SETPEND29_S 29 1129 1130 // Field: [28] SETPEND28 1131 // 1132 // Writing 0 to this bit has no effect, writing 1 to this bit pends the 1133 // interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details). Reading the bit 1134 // returns its current state. 1135 #define CPU_SCS_NVIC_ISPR0_SETPEND28 0x10000000 1136 #define CPU_SCS_NVIC_ISPR0_SETPEND28_BITN 28 1137 #define CPU_SCS_NVIC_ISPR0_SETPEND28_M 0x10000000 1138 #define CPU_SCS_NVIC_ISPR0_SETPEND28_S 28 1139 1140 // Field: [27] SETPEND27 1141 // 1142 // Writing 0 to this bit has no effect, writing 1 to this bit pends the 1143 // interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details). Reading the bit 1144 // returns its current state. 1145 #define CPU_SCS_NVIC_ISPR0_SETPEND27 0x08000000 1146 #define CPU_SCS_NVIC_ISPR0_SETPEND27_BITN 27 1147 #define CPU_SCS_NVIC_ISPR0_SETPEND27_M 0x08000000 1148 #define CPU_SCS_NVIC_ISPR0_SETPEND27_S 27 1149 1150 // Field: [26] SETPEND26 1151 // 1152 // Writing 0 to this bit has no effect, writing 1 to this bit pends the 1153 // interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details). Reading the bit 1154 // returns its current state. 1155 #define CPU_SCS_NVIC_ISPR0_SETPEND26 0x04000000 1156 #define CPU_SCS_NVIC_ISPR0_SETPEND26_BITN 26 1157 #define CPU_SCS_NVIC_ISPR0_SETPEND26_M 0x04000000 1158 #define CPU_SCS_NVIC_ISPR0_SETPEND26_S 26 1159 1160 // Field: [25] SETPEND25 1161 // 1162 // Writing 0 to this bit has no effect, writing 1 to this bit pends the 1163 // interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details). Reading the bit 1164 // returns its current state. 1165 #define CPU_SCS_NVIC_ISPR0_SETPEND25 0x02000000 1166 #define CPU_SCS_NVIC_ISPR0_SETPEND25_BITN 25 1167 #define CPU_SCS_NVIC_ISPR0_SETPEND25_M 0x02000000 1168 #define CPU_SCS_NVIC_ISPR0_SETPEND25_S 25 1169 1170 // Field: [24] SETPEND24 1171 // 1172 // Writing 0 to this bit has no effect, writing 1 to this bit pends the 1173 // interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details). Reading the bit 1174 // returns its current state. 1175 #define CPU_SCS_NVIC_ISPR0_SETPEND24 0x01000000 1176 #define CPU_SCS_NVIC_ISPR0_SETPEND24_BITN 24 1177 #define CPU_SCS_NVIC_ISPR0_SETPEND24_M 0x01000000 1178 #define CPU_SCS_NVIC_ISPR0_SETPEND24_S 24 1179 1180 // Field: [23] SETPEND23 1181 // 1182 // Writing 0 to this bit has no effect, writing 1 to this bit pends the 1183 // interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details). Reading the bit 1184 // returns its current state. 1185 #define CPU_SCS_NVIC_ISPR0_SETPEND23 0x00800000 1186 #define CPU_SCS_NVIC_ISPR0_SETPEND23_BITN 23 1187 #define CPU_SCS_NVIC_ISPR0_SETPEND23_M 0x00800000 1188 #define CPU_SCS_NVIC_ISPR0_SETPEND23_S 23 1189 1190 // Field: [22] SETPEND22 1191 // 1192 // Writing 0 to this bit has no effect, writing 1 to this bit pends the 1193 // interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details). Reading the bit 1194 // returns its current state. 1195 #define CPU_SCS_NVIC_ISPR0_SETPEND22 0x00400000 1196 #define CPU_SCS_NVIC_ISPR0_SETPEND22_BITN 22 1197 #define CPU_SCS_NVIC_ISPR0_SETPEND22_M 0x00400000 1198 #define CPU_SCS_NVIC_ISPR0_SETPEND22_S 22 1199 1200 // Field: [21] SETPEND21 1201 // 1202 // Writing 0 to this bit has no effect, writing 1 to this bit pends the 1203 // interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit 1204 // returns its current state. 1205 #define CPU_SCS_NVIC_ISPR0_SETPEND21 0x00200000 1206 #define CPU_SCS_NVIC_ISPR0_SETPEND21_BITN 21 1207 #define CPU_SCS_NVIC_ISPR0_SETPEND21_M 0x00200000 1208 #define CPU_SCS_NVIC_ISPR0_SETPEND21_S 21 1209 1210 // Field: [20] SETPEND20 1211 // 1212 // Writing 0 to this bit has no effect, writing 1 to this bit pends the 1213 // interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details). Reading the bit 1214 // returns its current state. 1215 #define CPU_SCS_NVIC_ISPR0_SETPEND20 0x00100000 1216 #define CPU_SCS_NVIC_ISPR0_SETPEND20_BITN 20 1217 #define CPU_SCS_NVIC_ISPR0_SETPEND20_M 0x00100000 1218 #define CPU_SCS_NVIC_ISPR0_SETPEND20_S 20 1219 1220 // Field: [19] SETPEND19 1221 // 1222 // Writing 0 to this bit has no effect, writing 1 to this bit pends the 1223 // interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details). Reading the bit 1224 // returns its current state. 1225 #define CPU_SCS_NVIC_ISPR0_SETPEND19 0x00080000 1226 #define CPU_SCS_NVIC_ISPR0_SETPEND19_BITN 19 1227 #define CPU_SCS_NVIC_ISPR0_SETPEND19_M 0x00080000 1228 #define CPU_SCS_NVIC_ISPR0_SETPEND19_S 19 1229 1230 // Field: [18] SETPEND18 1231 // 1232 // Writing 0 to this bit has no effect, writing 1 to this bit pends the 1233 // interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details). Reading the bit 1234 // returns its current state. 1235 #define CPU_SCS_NVIC_ISPR0_SETPEND18 0x00040000 1236 #define CPU_SCS_NVIC_ISPR0_SETPEND18_BITN 18 1237 #define CPU_SCS_NVIC_ISPR0_SETPEND18_M 0x00040000 1238 #define CPU_SCS_NVIC_ISPR0_SETPEND18_S 18 1239 1240 // Field: [17] SETPEND17 1241 // 1242 // Writing 0 to this bit has no effect, writing 1 to this bit pends the 1243 // interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details). Reading the bit 1244 // returns its current state. 1245 #define CPU_SCS_NVIC_ISPR0_SETPEND17 0x00020000 1246 #define CPU_SCS_NVIC_ISPR0_SETPEND17_BITN 17 1247 #define CPU_SCS_NVIC_ISPR0_SETPEND17_M 0x00020000 1248 #define CPU_SCS_NVIC_ISPR0_SETPEND17_S 17 1249 1250 // Field: [16] SETPEND16 1251 // 1252 // Writing 0 to this bit has no effect, writing 1 to this bit pends the 1253 // interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details). Reading the bit 1254 // returns its current state. 1255 #define CPU_SCS_NVIC_ISPR0_SETPEND16 0x00010000 1256 #define CPU_SCS_NVIC_ISPR0_SETPEND16_BITN 16 1257 #define CPU_SCS_NVIC_ISPR0_SETPEND16_M 0x00010000 1258 #define CPU_SCS_NVIC_ISPR0_SETPEND16_S 16 1259 1260 // Field: [15] SETPEND15 1261 // 1262 // Writing 0 to this bit has no effect, writing 1 to this bit pends the 1263 // interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details). Reading the bit 1264 // returns its current state. 1265 #define CPU_SCS_NVIC_ISPR0_SETPEND15 0x00008000 1266 #define CPU_SCS_NVIC_ISPR0_SETPEND15_BITN 15 1267 #define CPU_SCS_NVIC_ISPR0_SETPEND15_M 0x00008000 1268 #define CPU_SCS_NVIC_ISPR0_SETPEND15_S 15 1269 1270 // Field: [14] SETPEND14 1271 // 1272 // Writing 0 to this bit has no effect, writing 1 to this bit pends the 1273 // interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details). Reading the bit 1274 // returns its current state. 1275 #define CPU_SCS_NVIC_ISPR0_SETPEND14 0x00004000 1276 #define CPU_SCS_NVIC_ISPR0_SETPEND14_BITN 14 1277 #define CPU_SCS_NVIC_ISPR0_SETPEND14_M 0x00004000 1278 #define CPU_SCS_NVIC_ISPR0_SETPEND14_S 14 1279 1280 // Field: [13] SETPEND13 1281 // 1282 // Writing 0 to this bit has no effect, writing 1 to this bit pends the 1283 // interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details). Reading the bit 1284 // returns its current state. 1285 #define CPU_SCS_NVIC_ISPR0_SETPEND13 0x00002000 1286 #define CPU_SCS_NVIC_ISPR0_SETPEND13_BITN 13 1287 #define CPU_SCS_NVIC_ISPR0_SETPEND13_M 0x00002000 1288 #define CPU_SCS_NVIC_ISPR0_SETPEND13_S 13 1289 1290 // Field: [12] SETPEND12 1291 // 1292 // Writing 0 to this bit has no effect, writing 1 to this bit pends the 1293 // interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details). Reading the bit 1294 // returns its current state. 1295 #define CPU_SCS_NVIC_ISPR0_SETPEND12 0x00001000 1296 #define CPU_SCS_NVIC_ISPR0_SETPEND12_BITN 12 1297 #define CPU_SCS_NVIC_ISPR0_SETPEND12_M 0x00001000 1298 #define CPU_SCS_NVIC_ISPR0_SETPEND12_S 12 1299 1300 // Field: [11] SETPEND11 1301 // 1302 // Writing 0 to this bit has no effect, writing 1 to this bit pends the 1303 // interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details). Reading the bit 1304 // returns its current state. 1305 #define CPU_SCS_NVIC_ISPR0_SETPEND11 0x00000800 1306 #define CPU_SCS_NVIC_ISPR0_SETPEND11_BITN 11 1307 #define CPU_SCS_NVIC_ISPR0_SETPEND11_M 0x00000800 1308 #define CPU_SCS_NVIC_ISPR0_SETPEND11_S 11 1309 1310 // Field: [10] SETPEND10 1311 // 1312 // Writing 0 to this bit has no effect, writing 1 to this bit pends the 1313 // interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details). Reading the bit 1314 // returns its current state. 1315 #define CPU_SCS_NVIC_ISPR0_SETPEND10 0x00000400 1316 #define CPU_SCS_NVIC_ISPR0_SETPEND10_BITN 10 1317 #define CPU_SCS_NVIC_ISPR0_SETPEND10_M 0x00000400 1318 #define CPU_SCS_NVIC_ISPR0_SETPEND10_S 10 1319 1320 // Field: [9] SETPEND9 1321 // 1322 // Writing 0 to this bit has no effect, writing 1 to this bit pends the 1323 // interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details). Reading the bit 1324 // returns its current state. 1325 #define CPU_SCS_NVIC_ISPR0_SETPEND9 0x00000200 1326 #define CPU_SCS_NVIC_ISPR0_SETPEND9_BITN 9 1327 #define CPU_SCS_NVIC_ISPR0_SETPEND9_M 0x00000200 1328 #define CPU_SCS_NVIC_ISPR0_SETPEND9_S 9 1329 1330 // Field: [8] SETPEND8 1331 // 1332 // Writing 0 to this bit has no effect, writing 1 to this bit pends the 1333 // interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details). Reading the bit 1334 // returns its current state. 1335 #define CPU_SCS_NVIC_ISPR0_SETPEND8 0x00000100 1336 #define CPU_SCS_NVIC_ISPR0_SETPEND8_BITN 8 1337 #define CPU_SCS_NVIC_ISPR0_SETPEND8_M 0x00000100 1338 #define CPU_SCS_NVIC_ISPR0_SETPEND8_S 8 1339 1340 // Field: [7] SETPEND7 1341 // 1342 // Writing 0 to this bit has no effect, writing 1 to this bit pends the 1343 // interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details). Reading the bit 1344 // returns its current state. 1345 #define CPU_SCS_NVIC_ISPR0_SETPEND7 0x00000080 1346 #define CPU_SCS_NVIC_ISPR0_SETPEND7_BITN 7 1347 #define CPU_SCS_NVIC_ISPR0_SETPEND7_M 0x00000080 1348 #define CPU_SCS_NVIC_ISPR0_SETPEND7_S 7 1349 1350 // Field: [6] SETPEND6 1351 // 1352 // Writing 0 to this bit has no effect, writing 1 to this bit pends the 1353 // interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details). Reading the bit 1354 // returns its current state. 1355 #define CPU_SCS_NVIC_ISPR0_SETPEND6 0x00000040 1356 #define CPU_SCS_NVIC_ISPR0_SETPEND6_BITN 6 1357 #define CPU_SCS_NVIC_ISPR0_SETPEND6_M 0x00000040 1358 #define CPU_SCS_NVIC_ISPR0_SETPEND6_S 6 1359 1360 // Field: [5] SETPEND5 1361 // 1362 // Writing 0 to this bit has no effect, writing 1 to this bit pends the 1363 // interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details). Reading the bit 1364 // returns its current state. 1365 #define CPU_SCS_NVIC_ISPR0_SETPEND5 0x00000020 1366 #define CPU_SCS_NVIC_ISPR0_SETPEND5_BITN 5 1367 #define CPU_SCS_NVIC_ISPR0_SETPEND5_M 0x00000020 1368 #define CPU_SCS_NVIC_ISPR0_SETPEND5_S 5 1369 1370 // Field: [4] SETPEND4 1371 // 1372 // Writing 0 to this bit has no effect, writing 1 to this bit pends the 1373 // interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details). Reading the bit 1374 // returns its current state. 1375 #define CPU_SCS_NVIC_ISPR0_SETPEND4 0x00000010 1376 #define CPU_SCS_NVIC_ISPR0_SETPEND4_BITN 4 1377 #define CPU_SCS_NVIC_ISPR0_SETPEND4_M 0x00000010 1378 #define CPU_SCS_NVIC_ISPR0_SETPEND4_S 4 1379 1380 // Field: [3] SETPEND3 1381 // 1382 // Writing 0 to this bit has no effect, writing 1 to this bit pends the 1383 // interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit 1384 // returns its current state. 1385 #define CPU_SCS_NVIC_ISPR0_SETPEND3 0x00000008 1386 #define CPU_SCS_NVIC_ISPR0_SETPEND3_BITN 3 1387 #define CPU_SCS_NVIC_ISPR0_SETPEND3_M 0x00000008 1388 #define CPU_SCS_NVIC_ISPR0_SETPEND3_S 3 1389 1390 // Field: [2] SETPEND2 1391 // 1392 // Writing 0 to this bit has no effect, writing 1 to this bit pends the 1393 // interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details). Reading the bit 1394 // returns its current state. 1395 #define CPU_SCS_NVIC_ISPR0_SETPEND2 0x00000004 1396 #define CPU_SCS_NVIC_ISPR0_SETPEND2_BITN 2 1397 #define CPU_SCS_NVIC_ISPR0_SETPEND2_M 0x00000004 1398 #define CPU_SCS_NVIC_ISPR0_SETPEND2_S 2 1399 1400 // Field: [1] SETPEND1 1401 // 1402 // Writing 0 to this bit has no effect, writing 1 to this bit pends the 1403 // interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details). Reading the bit 1404 // returns its current state. 1405 #define CPU_SCS_NVIC_ISPR0_SETPEND1 0x00000002 1406 #define CPU_SCS_NVIC_ISPR0_SETPEND1_BITN 1 1407 #define CPU_SCS_NVIC_ISPR0_SETPEND1_M 0x00000002 1408 #define CPU_SCS_NVIC_ISPR0_SETPEND1_S 1 1409 1410 // Field: [0] SETPEND0 1411 // 1412 // Writing 0 to this bit has no effect, writing 1 to this bit pends the 1413 // interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit 1414 // returns its current state. 1415 #define CPU_SCS_NVIC_ISPR0_SETPEND0 0x00000001 1416 #define CPU_SCS_NVIC_ISPR0_SETPEND0_BITN 0 1417 #define CPU_SCS_NVIC_ISPR0_SETPEND0_M 0x00000001 1418 #define CPU_SCS_NVIC_ISPR0_SETPEND0_S 0 1419 1420 //***************************************************************************** 1421 // 1422 // Register: CPU_SCS_O_NVIC_ISPR1 1423 // 1424 //***************************************************************************** 1425 // Field: [1] SETPEND33 1426 // 1427 // Writing 0 to this bit has no effect, writing 1 to this bit pends the 1428 // interrupt number 33 (See EVENT:CPUIRQSEL33.EV for details). Reading the bit 1429 // returns its current state. 1430 #define CPU_SCS_NVIC_ISPR1_SETPEND33 0x00000002 1431 #define CPU_SCS_NVIC_ISPR1_SETPEND33_BITN 1 1432 #define CPU_SCS_NVIC_ISPR1_SETPEND33_M 0x00000002 1433 #define CPU_SCS_NVIC_ISPR1_SETPEND33_S 1 1434 1435 // Field: [0] SETPEND32 1436 // 1437 // Writing 0 to this bit has no effect, writing 1 to this bit pends the 1438 // interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details). Reading the bit 1439 // returns its current state. 1440 #define CPU_SCS_NVIC_ISPR1_SETPEND32 0x00000001 1441 #define CPU_SCS_NVIC_ISPR1_SETPEND32_BITN 0 1442 #define CPU_SCS_NVIC_ISPR1_SETPEND32_M 0x00000001 1443 #define CPU_SCS_NVIC_ISPR1_SETPEND32_S 0 1444 1445 //***************************************************************************** 1446 // 1447 // Register: CPU_SCS_O_NVIC_ICPR0 1448 // 1449 //***************************************************************************** 1450 // Field: [31] CLRPEND31 1451 // 1452 // Writing 0 to this bit has no effect, writing 1 to this bit clears the 1453 // corresponding pending interrupt 31 (See EVENT:CPUIRQSEL31.EV for details). 1454 // Reading the bit returns its current state. 1455 #define CPU_SCS_NVIC_ICPR0_CLRPEND31 0x80000000 1456 #define CPU_SCS_NVIC_ICPR0_CLRPEND31_BITN 31 1457 #define CPU_SCS_NVIC_ICPR0_CLRPEND31_M 0x80000000 1458 #define CPU_SCS_NVIC_ICPR0_CLRPEND31_S 31 1459 1460 // Field: [30] CLRPEND30 1461 // 1462 // Writing 0 to this bit has no effect, writing 1 to this bit clears the 1463 // corresponding pending interrupt 30 (See EVENT:CPUIRQSEL30.EV for details). 1464 // Reading the bit returns its current state. 1465 #define CPU_SCS_NVIC_ICPR0_CLRPEND30 0x40000000 1466 #define CPU_SCS_NVIC_ICPR0_CLRPEND30_BITN 30 1467 #define CPU_SCS_NVIC_ICPR0_CLRPEND30_M 0x40000000 1468 #define CPU_SCS_NVIC_ICPR0_CLRPEND30_S 30 1469 1470 // Field: [29] CLRPEND29 1471 // 1472 // Writing 0 to this bit has no effect, writing 1 to this bit clears the 1473 // corresponding pending interrupt 29 (See EVENT:CPUIRQSEL29.EV for details). 1474 // Reading the bit returns its current state. 1475 #define CPU_SCS_NVIC_ICPR0_CLRPEND29 0x20000000 1476 #define CPU_SCS_NVIC_ICPR0_CLRPEND29_BITN 29 1477 #define CPU_SCS_NVIC_ICPR0_CLRPEND29_M 0x20000000 1478 #define CPU_SCS_NVIC_ICPR0_CLRPEND29_S 29 1479 1480 // Field: [28] CLRPEND28 1481 // 1482 // Writing 0 to this bit has no effect, writing 1 to this bit clears the 1483 // corresponding pending interrupt 28 (See EVENT:CPUIRQSEL28.EV for details). 1484 // Reading the bit returns its current state. 1485 #define CPU_SCS_NVIC_ICPR0_CLRPEND28 0x10000000 1486 #define CPU_SCS_NVIC_ICPR0_CLRPEND28_BITN 28 1487 #define CPU_SCS_NVIC_ICPR0_CLRPEND28_M 0x10000000 1488 #define CPU_SCS_NVIC_ICPR0_CLRPEND28_S 28 1489 1490 // Field: [27] CLRPEND27 1491 // 1492 // Writing 0 to this bit has no effect, writing 1 to this bit clears the 1493 // corresponding pending interrupt 27 (See EVENT:CPUIRQSEL27.EV for details). 1494 // Reading the bit returns its current state. 1495 #define CPU_SCS_NVIC_ICPR0_CLRPEND27 0x08000000 1496 #define CPU_SCS_NVIC_ICPR0_CLRPEND27_BITN 27 1497 #define CPU_SCS_NVIC_ICPR0_CLRPEND27_M 0x08000000 1498 #define CPU_SCS_NVIC_ICPR0_CLRPEND27_S 27 1499 1500 // Field: [26] CLRPEND26 1501 // 1502 // Writing 0 to this bit has no effect, writing 1 to this bit clears the 1503 // corresponding pending interrupt 26 (See EVENT:CPUIRQSEL26.EV for details). 1504 // Reading the bit returns its current state. 1505 #define CPU_SCS_NVIC_ICPR0_CLRPEND26 0x04000000 1506 #define CPU_SCS_NVIC_ICPR0_CLRPEND26_BITN 26 1507 #define CPU_SCS_NVIC_ICPR0_CLRPEND26_M 0x04000000 1508 #define CPU_SCS_NVIC_ICPR0_CLRPEND26_S 26 1509 1510 // Field: [25] CLRPEND25 1511 // 1512 // Writing 0 to this bit has no effect, writing 1 to this bit clears the 1513 // corresponding pending interrupt 25 (See EVENT:CPUIRQSEL25.EV for details). 1514 // Reading the bit returns its current state. 1515 #define CPU_SCS_NVIC_ICPR0_CLRPEND25 0x02000000 1516 #define CPU_SCS_NVIC_ICPR0_CLRPEND25_BITN 25 1517 #define CPU_SCS_NVIC_ICPR0_CLRPEND25_M 0x02000000 1518 #define CPU_SCS_NVIC_ICPR0_CLRPEND25_S 25 1519 1520 // Field: [24] CLRPEND24 1521 // 1522 // Writing 0 to this bit has no effect, writing 1 to this bit clears the 1523 // corresponding pending interrupt 24 (See EVENT:CPUIRQSEL24.EV for details). 1524 // Reading the bit returns its current state. 1525 #define CPU_SCS_NVIC_ICPR0_CLRPEND24 0x01000000 1526 #define CPU_SCS_NVIC_ICPR0_CLRPEND24_BITN 24 1527 #define CPU_SCS_NVIC_ICPR0_CLRPEND24_M 0x01000000 1528 #define CPU_SCS_NVIC_ICPR0_CLRPEND24_S 24 1529 1530 // Field: [23] CLRPEND23 1531 // 1532 // Writing 0 to this bit has no effect, writing 1 to this bit clears the 1533 // corresponding pending interrupt 23 (See EVENT:CPUIRQSEL23.EV for details). 1534 // Reading the bit returns its current state. 1535 #define CPU_SCS_NVIC_ICPR0_CLRPEND23 0x00800000 1536 #define CPU_SCS_NVIC_ICPR0_CLRPEND23_BITN 23 1537 #define CPU_SCS_NVIC_ICPR0_CLRPEND23_M 0x00800000 1538 #define CPU_SCS_NVIC_ICPR0_CLRPEND23_S 23 1539 1540 // Field: [22] CLRPEND22 1541 // 1542 // Writing 0 to this bit has no effect, writing 1 to this bit clears the 1543 // corresponding pending interrupt 22 (See EVENT:CPUIRQSEL22.EV for details). 1544 // Reading the bit returns its current state. 1545 #define CPU_SCS_NVIC_ICPR0_CLRPEND22 0x00400000 1546 #define CPU_SCS_NVIC_ICPR0_CLRPEND22_BITN 22 1547 #define CPU_SCS_NVIC_ICPR0_CLRPEND22_M 0x00400000 1548 #define CPU_SCS_NVIC_ICPR0_CLRPEND22_S 22 1549 1550 // Field: [21] CLRPEND21 1551 // 1552 // Writing 0 to this bit has no effect, writing 1 to this bit clears the 1553 // corresponding pending interrupt 21 (See EVENT:CPUIRQSEL21.EV for details). 1554 // Reading the bit returns its current state. 1555 #define CPU_SCS_NVIC_ICPR0_CLRPEND21 0x00200000 1556 #define CPU_SCS_NVIC_ICPR0_CLRPEND21_BITN 21 1557 #define CPU_SCS_NVIC_ICPR0_CLRPEND21_M 0x00200000 1558 #define CPU_SCS_NVIC_ICPR0_CLRPEND21_S 21 1559 1560 // Field: [20] CLRPEND20 1561 // 1562 // Writing 0 to this bit has no effect, writing 1 to this bit clears the 1563 // corresponding pending interrupt 20 (See EVENT:CPUIRQSEL20.EV for details). 1564 // Reading the bit returns its current state. 1565 #define CPU_SCS_NVIC_ICPR0_CLRPEND20 0x00100000 1566 #define CPU_SCS_NVIC_ICPR0_CLRPEND20_BITN 20 1567 #define CPU_SCS_NVIC_ICPR0_CLRPEND20_M 0x00100000 1568 #define CPU_SCS_NVIC_ICPR0_CLRPEND20_S 20 1569 1570 // Field: [19] CLRPEND19 1571 // 1572 // Writing 0 to this bit has no effect, writing 1 to this bit clears the 1573 // corresponding pending interrupt 19 (See EVENT:CPUIRQSEL19.EV for details). 1574 // Reading the bit returns its current state. 1575 #define CPU_SCS_NVIC_ICPR0_CLRPEND19 0x00080000 1576 #define CPU_SCS_NVIC_ICPR0_CLRPEND19_BITN 19 1577 #define CPU_SCS_NVIC_ICPR0_CLRPEND19_M 0x00080000 1578 #define CPU_SCS_NVIC_ICPR0_CLRPEND19_S 19 1579 1580 // Field: [18] CLRPEND18 1581 // 1582 // Writing 0 to this bit has no effect, writing 1 to this bit clears the 1583 // corresponding pending interrupt 18 (See EVENT:CPUIRQSEL18.EV for details). 1584 // Reading the bit returns its current state. 1585 #define CPU_SCS_NVIC_ICPR0_CLRPEND18 0x00040000 1586 #define CPU_SCS_NVIC_ICPR0_CLRPEND18_BITN 18 1587 #define CPU_SCS_NVIC_ICPR0_CLRPEND18_M 0x00040000 1588 #define CPU_SCS_NVIC_ICPR0_CLRPEND18_S 18 1589 1590 // Field: [17] CLRPEND17 1591 // 1592 // Writing 0 to this bit has no effect, writing 1 to this bit clears the 1593 // corresponding pending interrupt 17 (See EVENT:CPUIRQSEL17.EV for details). 1594 // Reading the bit returns its current state. 1595 #define CPU_SCS_NVIC_ICPR0_CLRPEND17 0x00020000 1596 #define CPU_SCS_NVIC_ICPR0_CLRPEND17_BITN 17 1597 #define CPU_SCS_NVIC_ICPR0_CLRPEND17_M 0x00020000 1598 #define CPU_SCS_NVIC_ICPR0_CLRPEND17_S 17 1599 1600 // Field: [16] CLRPEND16 1601 // 1602 // Writing 0 to this bit has no effect, writing 1 to this bit clears the 1603 // corresponding pending interrupt 16 (See EVENT:CPUIRQSEL16.EV for details). 1604 // Reading the bit returns its current state. 1605 #define CPU_SCS_NVIC_ICPR0_CLRPEND16 0x00010000 1606 #define CPU_SCS_NVIC_ICPR0_CLRPEND16_BITN 16 1607 #define CPU_SCS_NVIC_ICPR0_CLRPEND16_M 0x00010000 1608 #define CPU_SCS_NVIC_ICPR0_CLRPEND16_S 16 1609 1610 // Field: [15] CLRPEND15 1611 // 1612 // Writing 0 to this bit has no effect, writing 1 to this bit clears the 1613 // corresponding pending interrupt 15 (See EVENT:CPUIRQSEL15.EV for details). 1614 // Reading the bit returns its current state. 1615 #define CPU_SCS_NVIC_ICPR0_CLRPEND15 0x00008000 1616 #define CPU_SCS_NVIC_ICPR0_CLRPEND15_BITN 15 1617 #define CPU_SCS_NVIC_ICPR0_CLRPEND15_M 0x00008000 1618 #define CPU_SCS_NVIC_ICPR0_CLRPEND15_S 15 1619 1620 // Field: [14] CLRPEND14 1621 // 1622 // Writing 0 to this bit has no effect, writing 1 to this bit clears the 1623 // corresponding pending interrupt 14 (See EVENT:CPUIRQSEL14.EV for details). 1624 // Reading the bit returns its current state. 1625 #define CPU_SCS_NVIC_ICPR0_CLRPEND14 0x00004000 1626 #define CPU_SCS_NVIC_ICPR0_CLRPEND14_BITN 14 1627 #define CPU_SCS_NVIC_ICPR0_CLRPEND14_M 0x00004000 1628 #define CPU_SCS_NVIC_ICPR0_CLRPEND14_S 14 1629 1630 // Field: [13] CLRPEND13 1631 // 1632 // Writing 0 to this bit has no effect, writing 1 to this bit clears the 1633 // corresponding pending interrupt 13 (See EVENT:CPUIRQSEL13.EV for details). 1634 // Reading the bit returns its current state. 1635 #define CPU_SCS_NVIC_ICPR0_CLRPEND13 0x00002000 1636 #define CPU_SCS_NVIC_ICPR0_CLRPEND13_BITN 13 1637 #define CPU_SCS_NVIC_ICPR0_CLRPEND13_M 0x00002000 1638 #define CPU_SCS_NVIC_ICPR0_CLRPEND13_S 13 1639 1640 // Field: [12] CLRPEND12 1641 // 1642 // Writing 0 to this bit has no effect, writing 1 to this bit clears the 1643 // corresponding pending interrupt 12 (See EVENT:CPUIRQSEL12.EV for details). 1644 // Reading the bit returns its current state. 1645 #define CPU_SCS_NVIC_ICPR0_CLRPEND12 0x00001000 1646 #define CPU_SCS_NVIC_ICPR0_CLRPEND12_BITN 12 1647 #define CPU_SCS_NVIC_ICPR0_CLRPEND12_M 0x00001000 1648 #define CPU_SCS_NVIC_ICPR0_CLRPEND12_S 12 1649 1650 // Field: [11] CLRPEND11 1651 // 1652 // Writing 0 to this bit has no effect, writing 1 to this bit clears the 1653 // corresponding pending interrupt 11 (See EVENT:CPUIRQSEL11.EV for details). 1654 // Reading the bit returns its current state. 1655 #define CPU_SCS_NVIC_ICPR0_CLRPEND11 0x00000800 1656 #define CPU_SCS_NVIC_ICPR0_CLRPEND11_BITN 11 1657 #define CPU_SCS_NVIC_ICPR0_CLRPEND11_M 0x00000800 1658 #define CPU_SCS_NVIC_ICPR0_CLRPEND11_S 11 1659 1660 // Field: [10] CLRPEND10 1661 // 1662 // Writing 0 to this bit has no effect, writing 1 to this bit clears the 1663 // corresponding pending interrupt 10 (See EVENT:CPUIRQSEL10.EV for details). 1664 // Reading the bit returns its current state. 1665 #define CPU_SCS_NVIC_ICPR0_CLRPEND10 0x00000400 1666 #define CPU_SCS_NVIC_ICPR0_CLRPEND10_BITN 10 1667 #define CPU_SCS_NVIC_ICPR0_CLRPEND10_M 0x00000400 1668 #define CPU_SCS_NVIC_ICPR0_CLRPEND10_S 10 1669 1670 // Field: [9] CLRPEND9 1671 // 1672 // Writing 0 to this bit has no effect, writing 1 to this bit clears the 1673 // corresponding pending interrupt 9 (See EVENT:CPUIRQSEL9.EV for details). 1674 // Reading the bit returns its current state. 1675 #define CPU_SCS_NVIC_ICPR0_CLRPEND9 0x00000200 1676 #define CPU_SCS_NVIC_ICPR0_CLRPEND9_BITN 9 1677 #define CPU_SCS_NVIC_ICPR0_CLRPEND9_M 0x00000200 1678 #define CPU_SCS_NVIC_ICPR0_CLRPEND9_S 9 1679 1680 // Field: [8] CLRPEND8 1681 // 1682 // Writing 0 to this bit has no effect, writing 1 to this bit clears the 1683 // corresponding pending interrupt 8 (See EVENT:CPUIRQSEL8.EV for details). 1684 // Reading the bit returns its current state. 1685 #define CPU_SCS_NVIC_ICPR0_CLRPEND8 0x00000100 1686 #define CPU_SCS_NVIC_ICPR0_CLRPEND8_BITN 8 1687 #define CPU_SCS_NVIC_ICPR0_CLRPEND8_M 0x00000100 1688 #define CPU_SCS_NVIC_ICPR0_CLRPEND8_S 8 1689 1690 // Field: [7] CLRPEND7 1691 // 1692 // Writing 0 to this bit has no effect, writing 1 to this bit clears the 1693 // corresponding pending interrupt 7 (See EVENT:CPUIRQSEL7.EV for details). 1694 // Reading the bit returns its current state. 1695 #define CPU_SCS_NVIC_ICPR0_CLRPEND7 0x00000080 1696 #define CPU_SCS_NVIC_ICPR0_CLRPEND7_BITN 7 1697 #define CPU_SCS_NVIC_ICPR0_CLRPEND7_M 0x00000080 1698 #define CPU_SCS_NVIC_ICPR0_CLRPEND7_S 7 1699 1700 // Field: [6] CLRPEND6 1701 // 1702 // Writing 0 to this bit has no effect, writing 1 to this bit clears the 1703 // corresponding pending interrupt 6 (See EVENT:CPUIRQSEL6.EV for details). 1704 // Reading the bit returns its current state. 1705 #define CPU_SCS_NVIC_ICPR0_CLRPEND6 0x00000040 1706 #define CPU_SCS_NVIC_ICPR0_CLRPEND6_BITN 6 1707 #define CPU_SCS_NVIC_ICPR0_CLRPEND6_M 0x00000040 1708 #define CPU_SCS_NVIC_ICPR0_CLRPEND6_S 6 1709 1710 // Field: [5] CLRPEND5 1711 // 1712 // Writing 0 to this bit has no effect, writing 1 to this bit clears the 1713 // corresponding pending interrupt 5 (See EVENT:CPUIRQSEL5.EV for details). 1714 // Reading the bit returns its current state. 1715 #define CPU_SCS_NVIC_ICPR0_CLRPEND5 0x00000020 1716 #define CPU_SCS_NVIC_ICPR0_CLRPEND5_BITN 5 1717 #define CPU_SCS_NVIC_ICPR0_CLRPEND5_M 0x00000020 1718 #define CPU_SCS_NVIC_ICPR0_CLRPEND5_S 5 1719 1720 // Field: [4] CLRPEND4 1721 // 1722 // Writing 0 to this bit has no effect, writing 1 to this bit clears the 1723 // corresponding pending interrupt 4 (See EVENT:CPUIRQSEL4.EV for details). 1724 // Reading the bit returns its current state. 1725 #define CPU_SCS_NVIC_ICPR0_CLRPEND4 0x00000010 1726 #define CPU_SCS_NVIC_ICPR0_CLRPEND4_BITN 4 1727 #define CPU_SCS_NVIC_ICPR0_CLRPEND4_M 0x00000010 1728 #define CPU_SCS_NVIC_ICPR0_CLRPEND4_S 4 1729 1730 // Field: [3] CLRPEND3 1731 // 1732 // Writing 0 to this bit has no effect, writing 1 to this bit clears the 1733 // corresponding pending interrupt 3 (See EVENT:CPUIRQSEL3.EV for details). 1734 // Reading the bit returns its current state. 1735 #define CPU_SCS_NVIC_ICPR0_CLRPEND3 0x00000008 1736 #define CPU_SCS_NVIC_ICPR0_CLRPEND3_BITN 3 1737 #define CPU_SCS_NVIC_ICPR0_CLRPEND3_M 0x00000008 1738 #define CPU_SCS_NVIC_ICPR0_CLRPEND3_S 3 1739 1740 // Field: [2] CLRPEND2 1741 // 1742 // Writing 0 to this bit has no effect, writing 1 to this bit clears the 1743 // corresponding pending interrupt 2 (See EVENT:CPUIRQSEL2.EV for details). 1744 // Reading the bit returns its current state. 1745 #define CPU_SCS_NVIC_ICPR0_CLRPEND2 0x00000004 1746 #define CPU_SCS_NVIC_ICPR0_CLRPEND2_BITN 2 1747 #define CPU_SCS_NVIC_ICPR0_CLRPEND2_M 0x00000004 1748 #define CPU_SCS_NVIC_ICPR0_CLRPEND2_S 2 1749 1750 // Field: [1] CLRPEND1 1751 // 1752 // Writing 0 to this bit has no effect, writing 1 to this bit clears the 1753 // corresponding pending interrupt 1 (See EVENT:CPUIRQSEL1.EV for details). 1754 // Reading the bit returns its current state. 1755 #define CPU_SCS_NVIC_ICPR0_CLRPEND1 0x00000002 1756 #define CPU_SCS_NVIC_ICPR0_CLRPEND1_BITN 1 1757 #define CPU_SCS_NVIC_ICPR0_CLRPEND1_M 0x00000002 1758 #define CPU_SCS_NVIC_ICPR0_CLRPEND1_S 1 1759 1760 // Field: [0] CLRPEND0 1761 // 1762 // Writing 0 to this bit has no effect, writing 1 to this bit clears the 1763 // corresponding pending interrupt 0 (See EVENT:CPUIRQSEL0.EV for details). 1764 // Reading the bit returns its current state. 1765 #define CPU_SCS_NVIC_ICPR0_CLRPEND0 0x00000001 1766 #define CPU_SCS_NVIC_ICPR0_CLRPEND0_BITN 0 1767 #define CPU_SCS_NVIC_ICPR0_CLRPEND0_M 0x00000001 1768 #define CPU_SCS_NVIC_ICPR0_CLRPEND0_S 0 1769 1770 //***************************************************************************** 1771 // 1772 // Register: CPU_SCS_O_NVIC_ICPR1 1773 // 1774 //***************************************************************************** 1775 // Field: [1] CLRPEND33 1776 // 1777 // Writing 0 to this bit has no effect, writing 1 to this bit clears the 1778 // corresponding pending interrupt 33 (See EVENT:CPUIRQSEL33.EV for details). 1779 // Reading the bit returns its current state. 1780 #define CPU_SCS_NVIC_ICPR1_CLRPEND33 0x00000002 1781 #define CPU_SCS_NVIC_ICPR1_CLRPEND33_BITN 1 1782 #define CPU_SCS_NVIC_ICPR1_CLRPEND33_M 0x00000002 1783 #define CPU_SCS_NVIC_ICPR1_CLRPEND33_S 1 1784 1785 // Field: [0] CLRPEND32 1786 // 1787 // Writing 0 to this bit has no effect, writing 1 to this bit clears the 1788 // corresponding pending interrupt 32 (See EVENT:CPUIRQSEL32.EV for details). 1789 // Reading the bit returns its current state. 1790 #define CPU_SCS_NVIC_ICPR1_CLRPEND32 0x00000001 1791 #define CPU_SCS_NVIC_ICPR1_CLRPEND32_BITN 0 1792 #define CPU_SCS_NVIC_ICPR1_CLRPEND32_M 0x00000001 1793 #define CPU_SCS_NVIC_ICPR1_CLRPEND32_S 0 1794 1795 //***************************************************************************** 1796 // 1797 // Register: CPU_SCS_O_NVIC_IABR0 1798 // 1799 //***************************************************************************** 1800 // Field: [31] ACTIVE31 1801 // 1802 // Reading 0 from this bit implies that interrupt line 31 is not active. 1803 // Reading 1 from this bit implies that the interrupt line 31 is active (See 1804 // EVENT:CPUIRQSEL31.EV for details). 1805 #define CPU_SCS_NVIC_IABR0_ACTIVE31 0x80000000 1806 #define CPU_SCS_NVIC_IABR0_ACTIVE31_BITN 31 1807 #define CPU_SCS_NVIC_IABR0_ACTIVE31_M 0x80000000 1808 #define CPU_SCS_NVIC_IABR0_ACTIVE31_S 31 1809 1810 // Field: [30] ACTIVE30 1811 // 1812 // Reading 0 from this bit implies that interrupt line 30 is not active. 1813 // Reading 1 from this bit implies that the interrupt line 30 is active (See 1814 // EVENT:CPUIRQSEL30.EV for details). 1815 #define CPU_SCS_NVIC_IABR0_ACTIVE30 0x40000000 1816 #define CPU_SCS_NVIC_IABR0_ACTIVE30_BITN 30 1817 #define CPU_SCS_NVIC_IABR0_ACTIVE30_M 0x40000000 1818 #define CPU_SCS_NVIC_IABR0_ACTIVE30_S 30 1819 1820 // Field: [29] ACTIVE29 1821 // 1822 // Reading 0 from this bit implies that interrupt line 29 is not active. 1823 // Reading 1 from this bit implies that the interrupt line 29 is active (See 1824 // EVENT:CPUIRQSEL29.EV for details). 1825 #define CPU_SCS_NVIC_IABR0_ACTIVE29 0x20000000 1826 #define CPU_SCS_NVIC_IABR0_ACTIVE29_BITN 29 1827 #define CPU_SCS_NVIC_IABR0_ACTIVE29_M 0x20000000 1828 #define CPU_SCS_NVIC_IABR0_ACTIVE29_S 29 1829 1830 // Field: [28] ACTIVE28 1831 // 1832 // Reading 0 from this bit implies that interrupt line 28 is not active. 1833 // Reading 1 from this bit implies that the interrupt line 28 is active (See 1834 // EVENT:CPUIRQSEL28.EV for details). 1835 #define CPU_SCS_NVIC_IABR0_ACTIVE28 0x10000000 1836 #define CPU_SCS_NVIC_IABR0_ACTIVE28_BITN 28 1837 #define CPU_SCS_NVIC_IABR0_ACTIVE28_M 0x10000000 1838 #define CPU_SCS_NVIC_IABR0_ACTIVE28_S 28 1839 1840 // Field: [27] ACTIVE27 1841 // 1842 // Reading 0 from this bit implies that interrupt line 27 is not active. 1843 // Reading 1 from this bit implies that the interrupt line 27 is active (See 1844 // EVENT:CPUIRQSEL27.EV for details). 1845 #define CPU_SCS_NVIC_IABR0_ACTIVE27 0x08000000 1846 #define CPU_SCS_NVIC_IABR0_ACTIVE27_BITN 27 1847 #define CPU_SCS_NVIC_IABR0_ACTIVE27_M 0x08000000 1848 #define CPU_SCS_NVIC_IABR0_ACTIVE27_S 27 1849 1850 // Field: [26] ACTIVE26 1851 // 1852 // Reading 0 from this bit implies that interrupt line 26 is not active. 1853 // Reading 1 from this bit implies that the interrupt line 26 is active (See 1854 // EVENT:CPUIRQSEL26.EV for details). 1855 #define CPU_SCS_NVIC_IABR0_ACTIVE26 0x04000000 1856 #define CPU_SCS_NVIC_IABR0_ACTIVE26_BITN 26 1857 #define CPU_SCS_NVIC_IABR0_ACTIVE26_M 0x04000000 1858 #define CPU_SCS_NVIC_IABR0_ACTIVE26_S 26 1859 1860 // Field: [25] ACTIVE25 1861 // 1862 // Reading 0 from this bit implies that interrupt line 25 is not active. 1863 // Reading 1 from this bit implies that the interrupt line 25 is active (See 1864 // EVENT:CPUIRQSEL25.EV for details). 1865 #define CPU_SCS_NVIC_IABR0_ACTIVE25 0x02000000 1866 #define CPU_SCS_NVIC_IABR0_ACTIVE25_BITN 25 1867 #define CPU_SCS_NVIC_IABR0_ACTIVE25_M 0x02000000 1868 #define CPU_SCS_NVIC_IABR0_ACTIVE25_S 25 1869 1870 // Field: [24] ACTIVE24 1871 // 1872 // Reading 0 from this bit implies that interrupt line 24 is not active. 1873 // Reading 1 from this bit implies that the interrupt line 24 is active (See 1874 // EVENT:CPUIRQSEL24.EV for details). 1875 #define CPU_SCS_NVIC_IABR0_ACTIVE24 0x01000000 1876 #define CPU_SCS_NVIC_IABR0_ACTIVE24_BITN 24 1877 #define CPU_SCS_NVIC_IABR0_ACTIVE24_M 0x01000000 1878 #define CPU_SCS_NVIC_IABR0_ACTIVE24_S 24 1879 1880 // Field: [23] ACTIVE23 1881 // 1882 // Reading 0 from this bit implies that interrupt line 23 is not active. 1883 // Reading 1 from this bit implies that the interrupt line 23 is active (See 1884 // EVENT:CPUIRQSEL23.EV for details). 1885 #define CPU_SCS_NVIC_IABR0_ACTIVE23 0x00800000 1886 #define CPU_SCS_NVIC_IABR0_ACTIVE23_BITN 23 1887 #define CPU_SCS_NVIC_IABR0_ACTIVE23_M 0x00800000 1888 #define CPU_SCS_NVIC_IABR0_ACTIVE23_S 23 1889 1890 // Field: [22] ACTIVE22 1891 // 1892 // Reading 0 from this bit implies that interrupt line 22 is not active. 1893 // Reading 1 from this bit implies that the interrupt line 22 is active (See 1894 // EVENT:CPUIRQSEL22.EV for details). 1895 #define CPU_SCS_NVIC_IABR0_ACTIVE22 0x00400000 1896 #define CPU_SCS_NVIC_IABR0_ACTIVE22_BITN 22 1897 #define CPU_SCS_NVIC_IABR0_ACTIVE22_M 0x00400000 1898 #define CPU_SCS_NVIC_IABR0_ACTIVE22_S 22 1899 1900 // Field: [21] ACTIVE21 1901 // 1902 // Reading 0 from this bit implies that interrupt line 21 is not active. 1903 // Reading 1 from this bit implies that the interrupt line 21 is active (See 1904 // EVENT:CPUIRQSEL21.EV for details). 1905 #define CPU_SCS_NVIC_IABR0_ACTIVE21 0x00200000 1906 #define CPU_SCS_NVIC_IABR0_ACTIVE21_BITN 21 1907 #define CPU_SCS_NVIC_IABR0_ACTIVE21_M 0x00200000 1908 #define CPU_SCS_NVIC_IABR0_ACTIVE21_S 21 1909 1910 // Field: [20] ACTIVE20 1911 // 1912 // Reading 0 from this bit implies that interrupt line 20 is not active. 1913 // Reading 1 from this bit implies that the interrupt line 20 is active (See 1914 // EVENT:CPUIRQSEL20.EV for details). 1915 #define CPU_SCS_NVIC_IABR0_ACTIVE20 0x00100000 1916 #define CPU_SCS_NVIC_IABR0_ACTIVE20_BITN 20 1917 #define CPU_SCS_NVIC_IABR0_ACTIVE20_M 0x00100000 1918 #define CPU_SCS_NVIC_IABR0_ACTIVE20_S 20 1919 1920 // Field: [19] ACTIVE19 1921 // 1922 // Reading 0 from this bit implies that interrupt line 19 is not active. 1923 // Reading 1 from this bit implies that the interrupt line 19 is active (See 1924 // EVENT:CPUIRQSEL19.EV for details). 1925 #define CPU_SCS_NVIC_IABR0_ACTIVE19 0x00080000 1926 #define CPU_SCS_NVIC_IABR0_ACTIVE19_BITN 19 1927 #define CPU_SCS_NVIC_IABR0_ACTIVE19_M 0x00080000 1928 #define CPU_SCS_NVIC_IABR0_ACTIVE19_S 19 1929 1930 // Field: [18] ACTIVE18 1931 // 1932 // Reading 0 from this bit implies that interrupt line 18 is not active. 1933 // Reading 1 from this bit implies that the interrupt line 18 is active (See 1934 // EVENT:CPUIRQSEL18.EV for details). 1935 #define CPU_SCS_NVIC_IABR0_ACTIVE18 0x00040000 1936 #define CPU_SCS_NVIC_IABR0_ACTIVE18_BITN 18 1937 #define CPU_SCS_NVIC_IABR0_ACTIVE18_M 0x00040000 1938 #define CPU_SCS_NVIC_IABR0_ACTIVE18_S 18 1939 1940 // Field: [17] ACTIVE17 1941 // 1942 // Reading 0 from this bit implies that interrupt line 17 is not active. 1943 // Reading 1 from this bit implies that the interrupt line 17 is active (See 1944 // EVENT:CPUIRQSEL17.EV for details). 1945 #define CPU_SCS_NVIC_IABR0_ACTIVE17 0x00020000 1946 #define CPU_SCS_NVIC_IABR0_ACTIVE17_BITN 17 1947 #define CPU_SCS_NVIC_IABR0_ACTIVE17_M 0x00020000 1948 #define CPU_SCS_NVIC_IABR0_ACTIVE17_S 17 1949 1950 // Field: [16] ACTIVE16 1951 // 1952 // Reading 0 from this bit implies that interrupt line 16 is not active. 1953 // Reading 1 from this bit implies that the interrupt line 16 is active (See 1954 // EVENT:CPUIRQSEL16.EV for details). 1955 #define CPU_SCS_NVIC_IABR0_ACTIVE16 0x00010000 1956 #define CPU_SCS_NVIC_IABR0_ACTIVE16_BITN 16 1957 #define CPU_SCS_NVIC_IABR0_ACTIVE16_M 0x00010000 1958 #define CPU_SCS_NVIC_IABR0_ACTIVE16_S 16 1959 1960 // Field: [15] ACTIVE15 1961 // 1962 // Reading 0 from this bit implies that interrupt line 15 is not active. 1963 // Reading 1 from this bit implies that the interrupt line 15 is active (See 1964 // EVENT:CPUIRQSEL15.EV for details). 1965 #define CPU_SCS_NVIC_IABR0_ACTIVE15 0x00008000 1966 #define CPU_SCS_NVIC_IABR0_ACTIVE15_BITN 15 1967 #define CPU_SCS_NVIC_IABR0_ACTIVE15_M 0x00008000 1968 #define CPU_SCS_NVIC_IABR0_ACTIVE15_S 15 1969 1970 // Field: [14] ACTIVE14 1971 // 1972 // Reading 0 from this bit implies that interrupt line 14 is not active. 1973 // Reading 1 from this bit implies that the interrupt line 14 is active (See 1974 // EVENT:CPUIRQSEL14.EV for details). 1975 #define CPU_SCS_NVIC_IABR0_ACTIVE14 0x00004000 1976 #define CPU_SCS_NVIC_IABR0_ACTIVE14_BITN 14 1977 #define CPU_SCS_NVIC_IABR0_ACTIVE14_M 0x00004000 1978 #define CPU_SCS_NVIC_IABR0_ACTIVE14_S 14 1979 1980 // Field: [13] ACTIVE13 1981 // 1982 // Reading 0 from this bit implies that interrupt line 13 is not active. 1983 // Reading 1 from this bit implies that the interrupt line 13 is active (See 1984 // EVENT:CPUIRQSEL13.EV for details). 1985 #define CPU_SCS_NVIC_IABR0_ACTIVE13 0x00002000 1986 #define CPU_SCS_NVIC_IABR0_ACTIVE13_BITN 13 1987 #define CPU_SCS_NVIC_IABR0_ACTIVE13_M 0x00002000 1988 #define CPU_SCS_NVIC_IABR0_ACTIVE13_S 13 1989 1990 // Field: [12] ACTIVE12 1991 // 1992 // Reading 0 from this bit implies that interrupt line 12 is not active. 1993 // Reading 1 from this bit implies that the interrupt line 12 is active (See 1994 // EVENT:CPUIRQSEL12.EV for details). 1995 #define CPU_SCS_NVIC_IABR0_ACTIVE12 0x00001000 1996 #define CPU_SCS_NVIC_IABR0_ACTIVE12_BITN 12 1997 #define CPU_SCS_NVIC_IABR0_ACTIVE12_M 0x00001000 1998 #define CPU_SCS_NVIC_IABR0_ACTIVE12_S 12 1999 2000 // Field: [11] ACTIVE11 2001 // 2002 // Reading 0 from this bit implies that interrupt line 11 is not active. 2003 // Reading 1 from this bit implies that the interrupt line 11 is active (See 2004 // EVENT:CPUIRQSEL11.EV for details). 2005 #define CPU_SCS_NVIC_IABR0_ACTIVE11 0x00000800 2006 #define CPU_SCS_NVIC_IABR0_ACTIVE11_BITN 11 2007 #define CPU_SCS_NVIC_IABR0_ACTIVE11_M 0x00000800 2008 #define CPU_SCS_NVIC_IABR0_ACTIVE11_S 11 2009 2010 // Field: [10] ACTIVE10 2011 // 2012 // Reading 0 from this bit implies that interrupt line 10 is not active. 2013 // Reading 1 from this bit implies that the interrupt line 10 is active (See 2014 // EVENT:CPUIRQSEL10.EV for details). 2015 #define CPU_SCS_NVIC_IABR0_ACTIVE10 0x00000400 2016 #define CPU_SCS_NVIC_IABR0_ACTIVE10_BITN 10 2017 #define CPU_SCS_NVIC_IABR0_ACTIVE10_M 0x00000400 2018 #define CPU_SCS_NVIC_IABR0_ACTIVE10_S 10 2019 2020 // Field: [9] ACTIVE9 2021 // 2022 // Reading 0 from this bit implies that interrupt line 9 is not active. Reading 2023 // 1 from this bit implies that the interrupt line 9 is active (See 2024 // EVENT:CPUIRQSEL9.EV for details). 2025 #define CPU_SCS_NVIC_IABR0_ACTIVE9 0x00000200 2026 #define CPU_SCS_NVIC_IABR0_ACTIVE9_BITN 9 2027 #define CPU_SCS_NVIC_IABR0_ACTIVE9_M 0x00000200 2028 #define CPU_SCS_NVIC_IABR0_ACTIVE9_S 9 2029 2030 // Field: [8] ACTIVE8 2031 // 2032 // Reading 0 from this bit implies that interrupt line 8 is not active. Reading 2033 // 1 from this bit implies that the interrupt line 8 is active (See 2034 // EVENT:CPUIRQSEL8.EV for details). 2035 #define CPU_SCS_NVIC_IABR0_ACTIVE8 0x00000100 2036 #define CPU_SCS_NVIC_IABR0_ACTIVE8_BITN 8 2037 #define CPU_SCS_NVIC_IABR0_ACTIVE8_M 0x00000100 2038 #define CPU_SCS_NVIC_IABR0_ACTIVE8_S 8 2039 2040 // Field: [7] ACTIVE7 2041 // 2042 // Reading 0 from this bit implies that interrupt line 7 is not active. Reading 2043 // 1 from this bit implies that the interrupt line 7 is active (See 2044 // EVENT:CPUIRQSEL7.EV for details). 2045 #define CPU_SCS_NVIC_IABR0_ACTIVE7 0x00000080 2046 #define CPU_SCS_NVIC_IABR0_ACTIVE7_BITN 7 2047 #define CPU_SCS_NVIC_IABR0_ACTIVE7_M 0x00000080 2048 #define CPU_SCS_NVIC_IABR0_ACTIVE7_S 7 2049 2050 // Field: [6] ACTIVE6 2051 // 2052 // Reading 0 from this bit implies that interrupt line 6 is not active. Reading 2053 // 1 from this bit implies that the interrupt line 6 is active (See 2054 // EVENT:CPUIRQSEL6.EV for details). 2055 #define CPU_SCS_NVIC_IABR0_ACTIVE6 0x00000040 2056 #define CPU_SCS_NVIC_IABR0_ACTIVE6_BITN 6 2057 #define CPU_SCS_NVIC_IABR0_ACTIVE6_M 0x00000040 2058 #define CPU_SCS_NVIC_IABR0_ACTIVE6_S 6 2059 2060 // Field: [5] ACTIVE5 2061 // 2062 // Reading 0 from this bit implies that interrupt line 5 is not active. Reading 2063 // 1 from this bit implies that the interrupt line 5 is active (See 2064 // EVENT:CPUIRQSEL5.EV for details). 2065 #define CPU_SCS_NVIC_IABR0_ACTIVE5 0x00000020 2066 #define CPU_SCS_NVIC_IABR0_ACTIVE5_BITN 5 2067 #define CPU_SCS_NVIC_IABR0_ACTIVE5_M 0x00000020 2068 #define CPU_SCS_NVIC_IABR0_ACTIVE5_S 5 2069 2070 // Field: [4] ACTIVE4 2071 // 2072 // Reading 0 from this bit implies that interrupt line 4 is not active. Reading 2073 // 1 from this bit implies that the interrupt line 4 is active (See 2074 // EVENT:CPUIRQSEL4.EV for details). 2075 #define CPU_SCS_NVIC_IABR0_ACTIVE4 0x00000010 2076 #define CPU_SCS_NVIC_IABR0_ACTIVE4_BITN 4 2077 #define CPU_SCS_NVIC_IABR0_ACTIVE4_M 0x00000010 2078 #define CPU_SCS_NVIC_IABR0_ACTIVE4_S 4 2079 2080 // Field: [3] ACTIVE3 2081 // 2082 // Reading 0 from this bit implies that interrupt line 3 is not active. Reading 2083 // 1 from this bit implies that the interrupt line 3 is active (See 2084 // EVENT:CPUIRQSEL3.EV for details). 2085 #define CPU_SCS_NVIC_IABR0_ACTIVE3 0x00000008 2086 #define CPU_SCS_NVIC_IABR0_ACTIVE3_BITN 3 2087 #define CPU_SCS_NVIC_IABR0_ACTIVE3_M 0x00000008 2088 #define CPU_SCS_NVIC_IABR0_ACTIVE3_S 3 2089 2090 // Field: [2] ACTIVE2 2091 // 2092 // Reading 0 from this bit implies that interrupt line 2 is not active. Reading 2093 // 1 from this bit implies that the interrupt line 2 is active (See 2094 // EVENT:CPUIRQSEL2.EV for details). 2095 #define CPU_SCS_NVIC_IABR0_ACTIVE2 0x00000004 2096 #define CPU_SCS_NVIC_IABR0_ACTIVE2_BITN 2 2097 #define CPU_SCS_NVIC_IABR0_ACTIVE2_M 0x00000004 2098 #define CPU_SCS_NVIC_IABR0_ACTIVE2_S 2 2099 2100 // Field: [1] ACTIVE1 2101 // 2102 // Reading 0 from this bit implies that interrupt line 1 is not active. Reading 2103 // 1 from this bit implies that the interrupt line 1 is active (See 2104 // EVENT:CPUIRQSEL1.EV for details). 2105 #define CPU_SCS_NVIC_IABR0_ACTIVE1 0x00000002 2106 #define CPU_SCS_NVIC_IABR0_ACTIVE1_BITN 1 2107 #define CPU_SCS_NVIC_IABR0_ACTIVE1_M 0x00000002 2108 #define CPU_SCS_NVIC_IABR0_ACTIVE1_S 1 2109 2110 // Field: [0] ACTIVE0 2111 // 2112 // Reading 0 from this bit implies that interrupt line 0 is not active. Reading 2113 // 1 from this bit implies that the interrupt line 0 is active (See 2114 // EVENT:CPUIRQSEL0.EV for details). 2115 #define CPU_SCS_NVIC_IABR0_ACTIVE0 0x00000001 2116 #define CPU_SCS_NVIC_IABR0_ACTIVE0_BITN 0 2117 #define CPU_SCS_NVIC_IABR0_ACTIVE0_M 0x00000001 2118 #define CPU_SCS_NVIC_IABR0_ACTIVE0_S 0 2119 2120 //***************************************************************************** 2121 // 2122 // Register: CPU_SCS_O_NVIC_IABR1 2123 // 2124 //***************************************************************************** 2125 // Field: [1] ACTIVE33 2126 // 2127 // Reading 0 from this bit implies that interrupt line 33 is not active. 2128 // Reading 1 from this bit implies that the interrupt line 33 is active (See 2129 // EVENT:CPUIRQSEL33.EV for details). 2130 #define CPU_SCS_NVIC_IABR1_ACTIVE33 0x00000002 2131 #define CPU_SCS_NVIC_IABR1_ACTIVE33_BITN 1 2132 #define CPU_SCS_NVIC_IABR1_ACTIVE33_M 0x00000002 2133 #define CPU_SCS_NVIC_IABR1_ACTIVE33_S 1 2134 2135 // Field: [0] ACTIVE32 2136 // 2137 // Reading 0 from this bit implies that interrupt line 32 is not active. 2138 // Reading 1 from this bit implies that the interrupt line 32 is active (See 2139 // EVENT:CPUIRQSEL32.EV for details). 2140 #define CPU_SCS_NVIC_IABR1_ACTIVE32 0x00000001 2141 #define CPU_SCS_NVIC_IABR1_ACTIVE32_BITN 0 2142 #define CPU_SCS_NVIC_IABR1_ACTIVE32_M 0x00000001 2143 #define CPU_SCS_NVIC_IABR1_ACTIVE32_S 0 2144 2145 //***************************************************************************** 2146 // 2147 // Register: CPU_SCS_O_NVIC_IPR0 2148 // 2149 //***************************************************************************** 2150 // Field: [31:24] PRI_3 2151 // 2152 // Priority of interrupt 3 (See EVENT:CPUIRQSEL3.EV for details). 2153 #define CPU_SCS_NVIC_IPR0_PRI_3_W 8 2154 #define CPU_SCS_NVIC_IPR0_PRI_3_M 0xFF000000 2155 #define CPU_SCS_NVIC_IPR0_PRI_3_S 24 2156 2157 // Field: [23:16] PRI_2 2158 // 2159 // Priority of interrupt 2 (See EVENT:CPUIRQSEL2.EV for details). 2160 #define CPU_SCS_NVIC_IPR0_PRI_2_W 8 2161 #define CPU_SCS_NVIC_IPR0_PRI_2_M 0x00FF0000 2162 #define CPU_SCS_NVIC_IPR0_PRI_2_S 16 2163 2164 // Field: [15:8] PRI_1 2165 // 2166 // Priority of interrupt 1 (See EVENT:CPUIRQSEL1.EV for details). 2167 #define CPU_SCS_NVIC_IPR0_PRI_1_W 8 2168 #define CPU_SCS_NVIC_IPR0_PRI_1_M 0x0000FF00 2169 #define CPU_SCS_NVIC_IPR0_PRI_1_S 8 2170 2171 // Field: [7:0] PRI_0 2172 // 2173 // Priority of interrupt 0 (See EVENT:CPUIRQSEL0.EV for details). 2174 #define CPU_SCS_NVIC_IPR0_PRI_0_W 8 2175 #define CPU_SCS_NVIC_IPR0_PRI_0_M 0x000000FF 2176 #define CPU_SCS_NVIC_IPR0_PRI_0_S 0 2177 2178 //***************************************************************************** 2179 // 2180 // Register: CPU_SCS_O_NVIC_IPR1 2181 // 2182 //***************************************************************************** 2183 // Field: [31:24] PRI_7 2184 // 2185 // Priority of interrupt 7 (See EVENT:CPUIRQSEL7.EV for details). 2186 #define CPU_SCS_NVIC_IPR1_PRI_7_W 8 2187 #define CPU_SCS_NVIC_IPR1_PRI_7_M 0xFF000000 2188 #define CPU_SCS_NVIC_IPR1_PRI_7_S 24 2189 2190 // Field: [23:16] PRI_6 2191 // 2192 // Priority of interrupt 6 (See EVENT:CPUIRQSEL6.EV for details). 2193 #define CPU_SCS_NVIC_IPR1_PRI_6_W 8 2194 #define CPU_SCS_NVIC_IPR1_PRI_6_M 0x00FF0000 2195 #define CPU_SCS_NVIC_IPR1_PRI_6_S 16 2196 2197 // Field: [15:8] PRI_5 2198 // 2199 // Priority of interrupt 5 (See EVENT:CPUIRQSEL5.EV for details). 2200 #define CPU_SCS_NVIC_IPR1_PRI_5_W 8 2201 #define CPU_SCS_NVIC_IPR1_PRI_5_M 0x0000FF00 2202 #define CPU_SCS_NVIC_IPR1_PRI_5_S 8 2203 2204 // Field: [7:0] PRI_4 2205 // 2206 // Priority of interrupt 4 (See EVENT:CPUIRQSEL4.EV for details). 2207 #define CPU_SCS_NVIC_IPR1_PRI_4_W 8 2208 #define CPU_SCS_NVIC_IPR1_PRI_4_M 0x000000FF 2209 #define CPU_SCS_NVIC_IPR1_PRI_4_S 0 2210 2211 //***************************************************************************** 2212 // 2213 // Register: CPU_SCS_O_NVIC_IPR2 2214 // 2215 //***************************************************************************** 2216 // Field: [31:24] PRI_11 2217 // 2218 // Priority of interrupt 11 (See EVENT:CPUIRQSEL11.EV for details). 2219 #define CPU_SCS_NVIC_IPR2_PRI_11_W 8 2220 #define CPU_SCS_NVIC_IPR2_PRI_11_M 0xFF000000 2221 #define CPU_SCS_NVIC_IPR2_PRI_11_S 24 2222 2223 // Field: [23:16] PRI_10 2224 // 2225 // Priority of interrupt 10 (See EVENT:CPUIRQSEL10.EV for details). 2226 #define CPU_SCS_NVIC_IPR2_PRI_10_W 8 2227 #define CPU_SCS_NVIC_IPR2_PRI_10_M 0x00FF0000 2228 #define CPU_SCS_NVIC_IPR2_PRI_10_S 16 2229 2230 // Field: [15:8] PRI_9 2231 // 2232 // Priority of interrupt 9 (See EVENT:CPUIRQSEL9.EV for details). 2233 #define CPU_SCS_NVIC_IPR2_PRI_9_W 8 2234 #define CPU_SCS_NVIC_IPR2_PRI_9_M 0x0000FF00 2235 #define CPU_SCS_NVIC_IPR2_PRI_9_S 8 2236 2237 // Field: [7:0] PRI_8 2238 // 2239 // Priority of interrupt 8 (See EVENT:CPUIRQSEL8.EV for details). 2240 #define CPU_SCS_NVIC_IPR2_PRI_8_W 8 2241 #define CPU_SCS_NVIC_IPR2_PRI_8_M 0x000000FF 2242 #define CPU_SCS_NVIC_IPR2_PRI_8_S 0 2243 2244 //***************************************************************************** 2245 // 2246 // Register: CPU_SCS_O_NVIC_IPR3 2247 // 2248 //***************************************************************************** 2249 // Field: [31:24] PRI_15 2250 // 2251 // Priority of interrupt 15 (See EVENT:CPUIRQSEL15.EV for details). 2252 #define CPU_SCS_NVIC_IPR3_PRI_15_W 8 2253 #define CPU_SCS_NVIC_IPR3_PRI_15_M 0xFF000000 2254 #define CPU_SCS_NVIC_IPR3_PRI_15_S 24 2255 2256 // Field: [23:16] PRI_14 2257 // 2258 // Priority of interrupt 14 (See EVENT:CPUIRQSEL14.EV for details). 2259 #define CPU_SCS_NVIC_IPR3_PRI_14_W 8 2260 #define CPU_SCS_NVIC_IPR3_PRI_14_M 0x00FF0000 2261 #define CPU_SCS_NVIC_IPR3_PRI_14_S 16 2262 2263 // Field: [15:8] PRI_13 2264 // 2265 // Priority of interrupt 13 (See EVENT:CPUIRQSEL13.EV for details). 2266 #define CPU_SCS_NVIC_IPR3_PRI_13_W 8 2267 #define CPU_SCS_NVIC_IPR3_PRI_13_M 0x0000FF00 2268 #define CPU_SCS_NVIC_IPR3_PRI_13_S 8 2269 2270 // Field: [7:0] PRI_12 2271 // 2272 // Priority of interrupt 12 (See EVENT:CPUIRQSEL12.EV for details). 2273 #define CPU_SCS_NVIC_IPR3_PRI_12_W 8 2274 #define CPU_SCS_NVIC_IPR3_PRI_12_M 0x000000FF 2275 #define CPU_SCS_NVIC_IPR3_PRI_12_S 0 2276 2277 //***************************************************************************** 2278 // 2279 // Register: CPU_SCS_O_NVIC_IPR4 2280 // 2281 //***************************************************************************** 2282 // Field: [31:24] PRI_19 2283 // 2284 // Priority of interrupt 19 (See EVENT:CPUIRQSEL19.EV for details). 2285 #define CPU_SCS_NVIC_IPR4_PRI_19_W 8 2286 #define CPU_SCS_NVIC_IPR4_PRI_19_M 0xFF000000 2287 #define CPU_SCS_NVIC_IPR4_PRI_19_S 24 2288 2289 // Field: [23:16] PRI_18 2290 // 2291 // Priority of interrupt 18 (See EVENT:CPUIRQSEL18.EV for details). 2292 #define CPU_SCS_NVIC_IPR4_PRI_18_W 8 2293 #define CPU_SCS_NVIC_IPR4_PRI_18_M 0x00FF0000 2294 #define CPU_SCS_NVIC_IPR4_PRI_18_S 16 2295 2296 // Field: [15:8] PRI_17 2297 // 2298 // Priority of interrupt 17 (See EVENT:CPUIRQSEL17.EV for details). 2299 #define CPU_SCS_NVIC_IPR4_PRI_17_W 8 2300 #define CPU_SCS_NVIC_IPR4_PRI_17_M 0x0000FF00 2301 #define CPU_SCS_NVIC_IPR4_PRI_17_S 8 2302 2303 // Field: [7:0] PRI_16 2304 // 2305 // Priority of interrupt 16 (See EVENT:CPUIRQSEL16.EV for details). 2306 #define CPU_SCS_NVIC_IPR4_PRI_16_W 8 2307 #define CPU_SCS_NVIC_IPR4_PRI_16_M 0x000000FF 2308 #define CPU_SCS_NVIC_IPR4_PRI_16_S 0 2309 2310 //***************************************************************************** 2311 // 2312 // Register: CPU_SCS_O_NVIC_IPR5 2313 // 2314 //***************************************************************************** 2315 // Field: [31:24] PRI_23 2316 // 2317 // Priority of interrupt 23 (See EVENT:CPUIRQSEL23.EV for details). 2318 #define CPU_SCS_NVIC_IPR5_PRI_23_W 8 2319 #define CPU_SCS_NVIC_IPR5_PRI_23_M 0xFF000000 2320 #define CPU_SCS_NVIC_IPR5_PRI_23_S 24 2321 2322 // Field: [23:16] PRI_22 2323 // 2324 // Priority of interrupt 22 (See EVENT:CPUIRQSEL22.EV for details). 2325 #define CPU_SCS_NVIC_IPR5_PRI_22_W 8 2326 #define CPU_SCS_NVIC_IPR5_PRI_22_M 0x00FF0000 2327 #define CPU_SCS_NVIC_IPR5_PRI_22_S 16 2328 2329 // Field: [15:8] PRI_21 2330 // 2331 // Priority of interrupt 21 (See EVENT:CPUIRQSEL21.EV for details). 2332 #define CPU_SCS_NVIC_IPR5_PRI_21_W 8 2333 #define CPU_SCS_NVIC_IPR5_PRI_21_M 0x0000FF00 2334 #define CPU_SCS_NVIC_IPR5_PRI_21_S 8 2335 2336 // Field: [7:0] PRI_20 2337 // 2338 // Priority of interrupt 20 (See EVENT:CPUIRQSEL20.EV for details). 2339 #define CPU_SCS_NVIC_IPR5_PRI_20_W 8 2340 #define CPU_SCS_NVIC_IPR5_PRI_20_M 0x000000FF 2341 #define CPU_SCS_NVIC_IPR5_PRI_20_S 0 2342 2343 //***************************************************************************** 2344 // 2345 // Register: CPU_SCS_O_NVIC_IPR6 2346 // 2347 //***************************************************************************** 2348 // Field: [31:24] PRI_27 2349 // 2350 // Priority of interrupt 27 (See EVENT:CPUIRQSEL27.EV for details). 2351 #define CPU_SCS_NVIC_IPR6_PRI_27_W 8 2352 #define CPU_SCS_NVIC_IPR6_PRI_27_M 0xFF000000 2353 #define CPU_SCS_NVIC_IPR6_PRI_27_S 24 2354 2355 // Field: [23:16] PRI_26 2356 // 2357 // Priority of interrupt 26 (See EVENT:CPUIRQSEL26.EV for details). 2358 #define CPU_SCS_NVIC_IPR6_PRI_26_W 8 2359 #define CPU_SCS_NVIC_IPR6_PRI_26_M 0x00FF0000 2360 #define CPU_SCS_NVIC_IPR6_PRI_26_S 16 2361 2362 // Field: [15:8] PRI_25 2363 // 2364 // Priority of interrupt 25 (See EVENT:CPUIRQSEL25.EV for details). 2365 #define CPU_SCS_NVIC_IPR6_PRI_25_W 8 2366 #define CPU_SCS_NVIC_IPR6_PRI_25_M 0x0000FF00 2367 #define CPU_SCS_NVIC_IPR6_PRI_25_S 8 2368 2369 // Field: [7:0] PRI_24 2370 // 2371 // Priority of interrupt 24 (See EVENT:CPUIRQSEL24.EV for details). 2372 #define CPU_SCS_NVIC_IPR6_PRI_24_W 8 2373 #define CPU_SCS_NVIC_IPR6_PRI_24_M 0x000000FF 2374 #define CPU_SCS_NVIC_IPR6_PRI_24_S 0 2375 2376 //***************************************************************************** 2377 // 2378 // Register: CPU_SCS_O_NVIC_IPR7 2379 // 2380 //***************************************************************************** 2381 // Field: [31:24] PRI_31 2382 // 2383 // Priority of interrupt 31 (See EVENT:CPUIRQSEL31.EV for details). 2384 #define CPU_SCS_NVIC_IPR7_PRI_31_W 8 2385 #define CPU_SCS_NVIC_IPR7_PRI_31_M 0xFF000000 2386 #define CPU_SCS_NVIC_IPR7_PRI_31_S 24 2387 2388 // Field: [23:16] PRI_30 2389 // 2390 // Priority of interrupt 30 (See EVENT:CPUIRQSEL30.EV for details). 2391 #define CPU_SCS_NVIC_IPR7_PRI_30_W 8 2392 #define CPU_SCS_NVIC_IPR7_PRI_30_M 0x00FF0000 2393 #define CPU_SCS_NVIC_IPR7_PRI_30_S 16 2394 2395 // Field: [15:8] PRI_29 2396 // 2397 // Priority of interrupt 29 (See EVENT:CPUIRQSEL29.EV for details). 2398 #define CPU_SCS_NVIC_IPR7_PRI_29_W 8 2399 #define CPU_SCS_NVIC_IPR7_PRI_29_M 0x0000FF00 2400 #define CPU_SCS_NVIC_IPR7_PRI_29_S 8 2401 2402 // Field: [7:0] PRI_28 2403 // 2404 // Priority of interrupt 28 (See EVENT:CPUIRQSEL28.EV for details). 2405 #define CPU_SCS_NVIC_IPR7_PRI_28_W 8 2406 #define CPU_SCS_NVIC_IPR7_PRI_28_M 0x000000FF 2407 #define CPU_SCS_NVIC_IPR7_PRI_28_S 0 2408 2409 //***************************************************************************** 2410 // 2411 // Register: CPU_SCS_O_NVIC_IPR8 2412 // 2413 //***************************************************************************** 2414 // Field: [15:8] PRI_33 2415 // 2416 // Priority of interrupt 33 (See EVENT:CPUIRQSEL33.EV for details). 2417 #define CPU_SCS_NVIC_IPR8_PRI_33_W 8 2418 #define CPU_SCS_NVIC_IPR8_PRI_33_M 0x0000FF00 2419 #define CPU_SCS_NVIC_IPR8_PRI_33_S 8 2420 2421 // Field: [7:0] PRI_32 2422 // 2423 // Priority of interrupt 32 (See EVENT:CPUIRQSEL32.EV for details). 2424 #define CPU_SCS_NVIC_IPR8_PRI_32_W 8 2425 #define CPU_SCS_NVIC_IPR8_PRI_32_M 0x000000FF 2426 #define CPU_SCS_NVIC_IPR8_PRI_32_S 0 2427 2428 //***************************************************************************** 2429 // 2430 // Register: CPU_SCS_O_CPUID 2431 // 2432 //***************************************************************************** 2433 // Field: [31:24] IMPLEMENTER 2434 // 2435 // Implementor code. 2436 #define CPU_SCS_CPUID_IMPLEMENTER_W 8 2437 #define CPU_SCS_CPUID_IMPLEMENTER_M 0xFF000000 2438 #define CPU_SCS_CPUID_IMPLEMENTER_S 24 2439 2440 // Field: [23:20] VARIANT 2441 // 2442 // Implementation defined variant number. 2443 #define CPU_SCS_CPUID_VARIANT_W 4 2444 #define CPU_SCS_CPUID_VARIANT_M 0x00F00000 2445 #define CPU_SCS_CPUID_VARIANT_S 20 2446 2447 // Field: [19:16] CONSTANT 2448 // 2449 // Reads as 0xF 2450 #define CPU_SCS_CPUID_CONSTANT_W 4 2451 #define CPU_SCS_CPUID_CONSTANT_M 0x000F0000 2452 #define CPU_SCS_CPUID_CONSTANT_S 16 2453 2454 // Field: [15:4] PARTNO 2455 // 2456 // Number of processor within family. 2457 #define CPU_SCS_CPUID_PARTNO_W 12 2458 #define CPU_SCS_CPUID_PARTNO_M 0x0000FFF0 2459 #define CPU_SCS_CPUID_PARTNO_S 4 2460 2461 // Field: [3:0] REVISION 2462 // 2463 // Implementation defined revision number. 2464 #define CPU_SCS_CPUID_REVISION_W 4 2465 #define CPU_SCS_CPUID_REVISION_M 0x0000000F 2466 #define CPU_SCS_CPUID_REVISION_S 0 2467 2468 //***************************************************************************** 2469 // 2470 // Register: CPU_SCS_O_ICSR 2471 // 2472 //***************************************************************************** 2473 // Field: [31] NMIPENDSET 2474 // 2475 // Set pending NMI bit. Setting this bit pends and activates an NMI. Because 2476 // NMI is the highest-priority interrupt, it takes effect as soon as it 2477 // registers. 2478 // 2479 // 0: No action 2480 // 1: Set pending NMI 2481 #define CPU_SCS_ICSR_NMIPENDSET 0x80000000 2482 #define CPU_SCS_ICSR_NMIPENDSET_BITN 31 2483 #define CPU_SCS_ICSR_NMIPENDSET_M 0x80000000 2484 #define CPU_SCS_ICSR_NMIPENDSET_S 31 2485 2486 // Field: [28] PENDSVSET 2487 // 2488 // Set pending pendSV bit. 2489 // 2490 // 0: No action 2491 // 1: Set pending PendSV 2492 #define CPU_SCS_ICSR_PENDSVSET 0x10000000 2493 #define CPU_SCS_ICSR_PENDSVSET_BITN 28 2494 #define CPU_SCS_ICSR_PENDSVSET_M 0x10000000 2495 #define CPU_SCS_ICSR_PENDSVSET_S 28 2496 2497 // Field: [27] PENDSVCLR 2498 // 2499 // Clear pending pendSV bit 2500 // 2501 // 0: No action 2502 // 1: Clear pending pendSV 2503 #define CPU_SCS_ICSR_PENDSVCLR 0x08000000 2504 #define CPU_SCS_ICSR_PENDSVCLR_BITN 27 2505 #define CPU_SCS_ICSR_PENDSVCLR_M 0x08000000 2506 #define CPU_SCS_ICSR_PENDSVCLR_S 27 2507 2508 // Field: [26] PENDSTSET 2509 // 2510 // Set a pending SysTick bit. 2511 // 2512 // 0: No action 2513 // 1: Set pending SysTick 2514 #define CPU_SCS_ICSR_PENDSTSET 0x04000000 2515 #define CPU_SCS_ICSR_PENDSTSET_BITN 26 2516 #define CPU_SCS_ICSR_PENDSTSET_M 0x04000000 2517 #define CPU_SCS_ICSR_PENDSTSET_S 26 2518 2519 // Field: [25] PENDSTCLR 2520 // 2521 // Clear pending SysTick bit 2522 // 2523 // 0: No action 2524 // 1: Clear pending SysTick 2525 #define CPU_SCS_ICSR_PENDSTCLR 0x02000000 2526 #define CPU_SCS_ICSR_PENDSTCLR_BITN 25 2527 #define CPU_SCS_ICSR_PENDSTCLR_M 0x02000000 2528 #define CPU_SCS_ICSR_PENDSTCLR_S 25 2529 2530 // Field: [23] ISRPREEMPT 2531 // 2532 // This field can only be used at debug time. It indicates that a pending 2533 // interrupt is to be taken in the next running cycle. If DHCSR.C_MASKINTS= 0, 2534 // the interrupt is serviced. 2535 // 2536 // 0: A pending exception is not serviced. 2537 // 1: A pending exception is serviced on exit from the debug halt state 2538 #define CPU_SCS_ICSR_ISRPREEMPT 0x00800000 2539 #define CPU_SCS_ICSR_ISRPREEMPT_BITN 23 2540 #define CPU_SCS_ICSR_ISRPREEMPT_M 0x00800000 2541 #define CPU_SCS_ICSR_ISRPREEMPT_S 23 2542 2543 // Field: [22] ISRPENDING 2544 // 2545 // Interrupt pending flag. Excludes NMI and faults. 2546 // 2547 // 0x0: Interrupt not pending 2548 // 0x1: Interrupt pending 2549 #define CPU_SCS_ICSR_ISRPENDING 0x00400000 2550 #define CPU_SCS_ICSR_ISRPENDING_BITN 22 2551 #define CPU_SCS_ICSR_ISRPENDING_M 0x00400000 2552 #define CPU_SCS_ICSR_ISRPENDING_S 22 2553 2554 // Field: [17:12] VECTPENDING 2555 // 2556 // Pending ISR number field. This field contains the interrupt number of the 2557 // highest priority pending ISR. 2558 #define CPU_SCS_ICSR_VECTPENDING_W 6 2559 #define CPU_SCS_ICSR_VECTPENDING_M 0x0003F000 2560 #define CPU_SCS_ICSR_VECTPENDING_S 12 2561 2562 // Field: [11] RETTOBASE 2563 // 2564 // Indicates whether there are preempted active exceptions: 2565 // 2566 // 0: There are preempted active exceptions to execute 2567 // 1: There are no active exceptions, or the currently-executing exception is 2568 // the only active exception. 2569 #define CPU_SCS_ICSR_RETTOBASE 0x00000800 2570 #define CPU_SCS_ICSR_RETTOBASE_BITN 11 2571 #define CPU_SCS_ICSR_RETTOBASE_M 0x00000800 2572 #define CPU_SCS_ICSR_RETTOBASE_S 11 2573 2574 // Field: [8:0] VECTACTIVE 2575 // 2576 // Active ISR number field. Reset clears this field. 2577 #define CPU_SCS_ICSR_VECTACTIVE_W 9 2578 #define CPU_SCS_ICSR_VECTACTIVE_M 0x000001FF 2579 #define CPU_SCS_ICSR_VECTACTIVE_S 0 2580 2581 //***************************************************************************** 2582 // 2583 // Register: CPU_SCS_O_VTOR 2584 // 2585 //***************************************************************************** 2586 // Field: [29:7] TBLOFF 2587 // 2588 // Bits 29 down to 7 of the vector table base offset. 2589 #define CPU_SCS_VTOR_TBLOFF_W 23 2590 #define CPU_SCS_VTOR_TBLOFF_M 0x3FFFFF80 2591 #define CPU_SCS_VTOR_TBLOFF_S 7 2592 2593 //***************************************************************************** 2594 // 2595 // Register: CPU_SCS_O_AIRCR 2596 // 2597 //***************************************************************************** 2598 // Field: [31:16] VECTKEY 2599 // 2600 // Register key. Writing to this register (AIRCR) requires 0x05FA in VECTKEY. 2601 // Otherwise the write value is ignored. Read always returns 0xFA05. 2602 #define CPU_SCS_AIRCR_VECTKEY_W 16 2603 #define CPU_SCS_AIRCR_VECTKEY_M 0xFFFF0000 2604 #define CPU_SCS_AIRCR_VECTKEY_S 16 2605 2606 // Field: [15] ENDIANESS 2607 // 2608 // Data endianness bit 2609 // ENUMs: 2610 // BIG Big endian 2611 // LITTLE Little endian 2612 #define CPU_SCS_AIRCR_ENDIANESS 0x00008000 2613 #define CPU_SCS_AIRCR_ENDIANESS_BITN 15 2614 #define CPU_SCS_AIRCR_ENDIANESS_M 0x00008000 2615 #define CPU_SCS_AIRCR_ENDIANESS_S 15 2616 #define CPU_SCS_AIRCR_ENDIANESS_BIG 0x00008000 2617 #define CPU_SCS_AIRCR_ENDIANESS_LITTLE 0x00000000 2618 2619 // Field: [10:8] PRIGROUP 2620 // 2621 // Interrupt priority grouping field. This field is a binary point position 2622 // indicator for creating subpriorities for exceptions that share the same 2623 // pre-emption level. It divides the PRI_n field in the Interrupt Priority 2624 // Registers (NVIC_IPR0, NVIC_IPR1,..., and NVIC_IPR8) into a pre-emption 2625 // level and a subpriority level. The binary point is a left-of value. This 2626 // means that the PRIGROUP value represents a point starting at the left of the 2627 // Least Significant Bit (LSB). The lowest value might not be 0 depending on 2628 // the number of bits allocated for priorities, and implementation choices. 2629 #define CPU_SCS_AIRCR_PRIGROUP_W 3 2630 #define CPU_SCS_AIRCR_PRIGROUP_M 0x00000700 2631 #define CPU_SCS_AIRCR_PRIGROUP_S 8 2632 2633 // Field: [2] SYSRESETREQ 2634 // 2635 // Requests a warm reset. Setting this bit does not prevent Halting Debug from 2636 // running. 2637 #define CPU_SCS_AIRCR_SYSRESETREQ 0x00000004 2638 #define CPU_SCS_AIRCR_SYSRESETREQ_BITN 2 2639 #define CPU_SCS_AIRCR_SYSRESETREQ_M 0x00000004 2640 #define CPU_SCS_AIRCR_SYSRESETREQ_S 2 2641 2642 // Field: [1] VECTCLRACTIVE 2643 // 2644 // Clears all active state information for active NMI, fault, and interrupts. 2645 // It is the responsibility of the application to reinitialize the stack. This 2646 // bit is for returning to a known state during debug. The bit self-clears. 2647 // IPSR is not cleared by this operation. So, if used by an application, it 2648 // must only be used at the base level of activation, or within a system 2649 // handler whose active bit can be set. 2650 #define CPU_SCS_AIRCR_VECTCLRACTIVE 0x00000002 2651 #define CPU_SCS_AIRCR_VECTCLRACTIVE_BITN 1 2652 #define CPU_SCS_AIRCR_VECTCLRACTIVE_M 0x00000002 2653 #define CPU_SCS_AIRCR_VECTCLRACTIVE_S 1 2654 2655 // Field: [0] VECTRESET 2656 // 2657 // System Reset bit. Resets the system, with the exception of debug components. 2658 // This bit is reserved for debug use and can be written to 1 only when the 2659 // core is halted. The bit self-clears. Writing this bit to 1 while core is not 2660 // halted may result in unpredictable behavior. 2661 #define CPU_SCS_AIRCR_VECTRESET 0x00000001 2662 #define CPU_SCS_AIRCR_VECTRESET_BITN 0 2663 #define CPU_SCS_AIRCR_VECTRESET_M 0x00000001 2664 #define CPU_SCS_AIRCR_VECTRESET_S 0 2665 2666 //***************************************************************************** 2667 // 2668 // Register: CPU_SCS_O_SCR 2669 // 2670 //***************************************************************************** 2671 // Field: [4] SEVONPEND 2672 // 2673 // Send Event on Pending bit: 2674 // 2675 // 0: Only enabled interrupts or events can wakeup the processor, disabled 2676 // interrupts are excluded 2677 // 1: Enabled events and all interrupts, including disabled interrupts, can 2678 // wakeup the processor. 2679 // 2680 // When an event or interrupt enters pending state, the event signal wakes up 2681 // the processor from WFE. If 2682 // the processor is not waiting for an event, the event is registered and 2683 // affects the next WFE. 2684 // The processor also wakes up on execution of an SEV instruction. 2685 #define CPU_SCS_SCR_SEVONPEND 0x00000010 2686 #define CPU_SCS_SCR_SEVONPEND_BITN 4 2687 #define CPU_SCS_SCR_SEVONPEND_M 0x00000010 2688 #define CPU_SCS_SCR_SEVONPEND_S 4 2689 2690 // Field: [2] SLEEPDEEP 2691 // 2692 // Controls whether the processor uses sleep or deep sleep as its low power 2693 // mode 2694 // ENUMs: 2695 // DEEPSLEEP Deep sleep 2696 // SLEEP Sleep 2697 #define CPU_SCS_SCR_SLEEPDEEP 0x00000004 2698 #define CPU_SCS_SCR_SLEEPDEEP_BITN 2 2699 #define CPU_SCS_SCR_SLEEPDEEP_M 0x00000004 2700 #define CPU_SCS_SCR_SLEEPDEEP_S 2 2701 #define CPU_SCS_SCR_SLEEPDEEP_DEEPSLEEP 0x00000004 2702 #define CPU_SCS_SCR_SLEEPDEEP_SLEEP 0x00000000 2703 2704 // Field: [1] SLEEPONEXIT 2705 // 2706 // Sleep on exit when returning from Handler mode to Thread mode. Enables 2707 // interrupt driven applications to avoid returning to empty main application. 2708 // 2709 // 0: Do not sleep when returning to thread mode 2710 // 1: Sleep on ISR exit 2711 #define CPU_SCS_SCR_SLEEPONEXIT 0x00000002 2712 #define CPU_SCS_SCR_SLEEPONEXIT_BITN 1 2713 #define CPU_SCS_SCR_SLEEPONEXIT_M 0x00000002 2714 #define CPU_SCS_SCR_SLEEPONEXIT_S 1 2715 2716 //***************************************************************************** 2717 // 2718 // Register: CPU_SCS_O_CCR 2719 // 2720 //***************************************************************************** 2721 // Field: [9] STKALIGN 2722 // 2723 // Stack alignment bit. 2724 // 2725 // 0: Only 4-byte alignment is guaranteed for the SP used prior to the 2726 // exception on exception entry. 2727 // 1: On exception entry, the SP used prior to the exception is adjusted to be 2728 // 8-byte aligned and the context to restore it is saved. The SP is restored on 2729 // the associated exception return. 2730 #define CPU_SCS_CCR_STKALIGN 0x00000200 2731 #define CPU_SCS_CCR_STKALIGN_BITN 9 2732 #define CPU_SCS_CCR_STKALIGN_M 0x00000200 2733 #define CPU_SCS_CCR_STKALIGN_S 9 2734 2735 // Field: [8] BFHFNMIGN 2736 // 2737 // Enables handlers with priority -1 or -2 to ignore data BusFaults caused by 2738 // load and store instructions. This applies to the HardFault, NMI, and 2739 // FAULTMASK escalated handlers: 2740 // 2741 // 0: Data BusFaults caused by load and store instructions cause a lock-up 2742 // 1: Data BusFaults caused by load and store instructions are ignored. 2743 // 2744 // Set this bit to 1 only when the handler and its data are in absolutely safe 2745 // memory. The normal use 2746 // of this bit is to probe system devices and bridges to detect problems. 2747 #define CPU_SCS_CCR_BFHFNMIGN 0x00000100 2748 #define CPU_SCS_CCR_BFHFNMIGN_BITN 8 2749 #define CPU_SCS_CCR_BFHFNMIGN_M 0x00000100 2750 #define CPU_SCS_CCR_BFHFNMIGN_S 8 2751 2752 // Field: [4] DIV_0_TRP 2753 // 2754 // Enables faulting or halting when the processor executes an SDIV or UDIV 2755 // instruction with a divisor of 0: 2756 // 2757 // 0: Do not trap divide by 0. In this mode, a divide by zero returns a 2758 // quotient of 0. 2759 // 1: Trap divide by 0. The relevant Usage Fault Status Register bit is 2760 // CFSR.DIVBYZERO. 2761 #define CPU_SCS_CCR_DIV_0_TRP 0x00000010 2762 #define CPU_SCS_CCR_DIV_0_TRP_BITN 4 2763 #define CPU_SCS_CCR_DIV_0_TRP_M 0x00000010 2764 #define CPU_SCS_CCR_DIV_0_TRP_S 4 2765 2766 // Field: [3] UNALIGN_TRP 2767 // 2768 // Enables unaligned access traps: 2769 // 2770 // 0: Do not trap unaligned halfword and word accesses 2771 // 1: Trap unaligned halfword and word accesses. The relevant Usage Fault 2772 // Status Register bit is CFSR.UNALIGNED. 2773 // 2774 // If this bit is set to 1, an unaligned access generates a UsageFault. 2775 // Unaligned LDM, STM, LDRD, and STRD instructions always fault regardless of 2776 // the value in UNALIGN_TRP. 2777 #define CPU_SCS_CCR_UNALIGN_TRP 0x00000008 2778 #define CPU_SCS_CCR_UNALIGN_TRP_BITN 3 2779 #define CPU_SCS_CCR_UNALIGN_TRP_M 0x00000008 2780 #define CPU_SCS_CCR_UNALIGN_TRP_S 3 2781 2782 // Field: [1] USERSETMPEND 2783 // 2784 // Enables unprivileged software access to STIR: 2785 // 2786 // 0: User code is not allowed to write to the Software Trigger Interrupt 2787 // register (STIR). 2788 // 1: User code can write the Software Trigger Interrupt register (STIR) to 2789 // trigger (pend) a Main exception, which is associated with the Main stack 2790 // pointer. 2791 #define CPU_SCS_CCR_USERSETMPEND 0x00000002 2792 #define CPU_SCS_CCR_USERSETMPEND_BITN 1 2793 #define CPU_SCS_CCR_USERSETMPEND_M 0x00000002 2794 #define CPU_SCS_CCR_USERSETMPEND_S 1 2795 2796 // Field: [0] NONBASETHREDENA 2797 // 2798 // Indicates how the processor enters Thread mode: 2799 // 2800 // 0: Processor can enter Thread mode only when no exception is active. 2801 // 1: Processor can enter Thread mode from any level using the appropriate 2802 // return value (EXC_RETURN). 2803 // 2804 // Exception returns occur when one of the following instructions loads a value 2805 // of 0xFXXXXXXX into the PC while in Handler mode: 2806 // - POP/LDM which includes loading the PC. 2807 // - LDR with PC as a destination. 2808 // - BX with any register. 2809 // The value written to the PC is intercepted and is referred to as the 2810 // EXC_RETURN value. 2811 #define CPU_SCS_CCR_NONBASETHREDENA 0x00000001 2812 #define CPU_SCS_CCR_NONBASETHREDENA_BITN 0 2813 #define CPU_SCS_CCR_NONBASETHREDENA_M 0x00000001 2814 #define CPU_SCS_CCR_NONBASETHREDENA_S 0 2815 2816 //***************************************************************************** 2817 // 2818 // Register: CPU_SCS_O_SHPR1 2819 // 2820 //***************************************************************************** 2821 // Field: [23:16] PRI_6 2822 // 2823 // Priority of system handler 6. UsageFault 2824 #define CPU_SCS_SHPR1_PRI_6_W 8 2825 #define CPU_SCS_SHPR1_PRI_6_M 0x00FF0000 2826 #define CPU_SCS_SHPR1_PRI_6_S 16 2827 2828 // Field: [15:8] PRI_5 2829 // 2830 // Priority of system handler 5: BusFault 2831 #define CPU_SCS_SHPR1_PRI_5_W 8 2832 #define CPU_SCS_SHPR1_PRI_5_M 0x0000FF00 2833 #define CPU_SCS_SHPR1_PRI_5_S 8 2834 2835 // Field: [7:0] PRI_4 2836 // 2837 // Priority of system handler 4: MemManage 2838 #define CPU_SCS_SHPR1_PRI_4_W 8 2839 #define CPU_SCS_SHPR1_PRI_4_M 0x000000FF 2840 #define CPU_SCS_SHPR1_PRI_4_S 0 2841 2842 //***************************************************************************** 2843 // 2844 // Register: CPU_SCS_O_SHPR2 2845 // 2846 //***************************************************************************** 2847 // Field: [31:24] PRI_11 2848 // 2849 // Priority of system handler 11. SVCall 2850 #define CPU_SCS_SHPR2_PRI_11_W 8 2851 #define CPU_SCS_SHPR2_PRI_11_M 0xFF000000 2852 #define CPU_SCS_SHPR2_PRI_11_S 24 2853 2854 //***************************************************************************** 2855 // 2856 // Register: CPU_SCS_O_SHPR3 2857 // 2858 //***************************************************************************** 2859 // Field: [31:24] PRI_15 2860 // 2861 // Priority of system handler 15. SysTick exception 2862 #define CPU_SCS_SHPR3_PRI_15_W 8 2863 #define CPU_SCS_SHPR3_PRI_15_M 0xFF000000 2864 #define CPU_SCS_SHPR3_PRI_15_S 24 2865 2866 // Field: [23:16] PRI_14 2867 // 2868 // Priority of system handler 14. Pend SV 2869 #define CPU_SCS_SHPR3_PRI_14_W 8 2870 #define CPU_SCS_SHPR3_PRI_14_M 0x00FF0000 2871 #define CPU_SCS_SHPR3_PRI_14_S 16 2872 2873 // Field: [7:0] PRI_12 2874 // 2875 // Priority of system handler 12. Debug Monitor 2876 #define CPU_SCS_SHPR3_PRI_12_W 8 2877 #define CPU_SCS_SHPR3_PRI_12_M 0x000000FF 2878 #define CPU_SCS_SHPR3_PRI_12_S 0 2879 2880 //***************************************************************************** 2881 // 2882 // Register: CPU_SCS_O_SHCSR 2883 // 2884 //***************************************************************************** 2885 // Field: [18] USGFAULTENA 2886 // 2887 // Usage fault system handler enable 2888 // ENUMs: 2889 // EN Exception enabled 2890 // DIS Exception disabled 2891 #define CPU_SCS_SHCSR_USGFAULTENA 0x00040000 2892 #define CPU_SCS_SHCSR_USGFAULTENA_BITN 18 2893 #define CPU_SCS_SHCSR_USGFAULTENA_M 0x00040000 2894 #define CPU_SCS_SHCSR_USGFAULTENA_S 18 2895 #define CPU_SCS_SHCSR_USGFAULTENA_EN 0x00040000 2896 #define CPU_SCS_SHCSR_USGFAULTENA_DIS 0x00000000 2897 2898 // Field: [17] BUSFAULTENA 2899 // 2900 // Bus fault system handler enable 2901 // ENUMs: 2902 // EN Exception enabled 2903 // DIS Exception disabled 2904 #define CPU_SCS_SHCSR_BUSFAULTENA 0x00020000 2905 #define CPU_SCS_SHCSR_BUSFAULTENA_BITN 17 2906 #define CPU_SCS_SHCSR_BUSFAULTENA_M 0x00020000 2907 #define CPU_SCS_SHCSR_BUSFAULTENA_S 17 2908 #define CPU_SCS_SHCSR_BUSFAULTENA_EN 0x00020000 2909 #define CPU_SCS_SHCSR_BUSFAULTENA_DIS 0x00000000 2910 2911 // Field: [16] MEMFAULTENA 2912 // 2913 // MemManage fault system handler enable 2914 // ENUMs: 2915 // EN Exception enabled 2916 // DIS Exception disabled 2917 #define CPU_SCS_SHCSR_MEMFAULTENA 0x00010000 2918 #define CPU_SCS_SHCSR_MEMFAULTENA_BITN 16 2919 #define CPU_SCS_SHCSR_MEMFAULTENA_M 0x00010000 2920 #define CPU_SCS_SHCSR_MEMFAULTENA_S 16 2921 #define CPU_SCS_SHCSR_MEMFAULTENA_EN 0x00010000 2922 #define CPU_SCS_SHCSR_MEMFAULTENA_DIS 0x00000000 2923 2924 // Field: [15] SVCALLPENDED 2925 // 2926 // SVCall pending 2927 // ENUMs: 2928 // PENDING Exception is pending. 2929 // NOTPENDING Exception is not active 2930 #define CPU_SCS_SHCSR_SVCALLPENDED 0x00008000 2931 #define CPU_SCS_SHCSR_SVCALLPENDED_BITN 15 2932 #define CPU_SCS_SHCSR_SVCALLPENDED_M 0x00008000 2933 #define CPU_SCS_SHCSR_SVCALLPENDED_S 15 2934 #define CPU_SCS_SHCSR_SVCALLPENDED_PENDING 0x00008000 2935 #define CPU_SCS_SHCSR_SVCALLPENDED_NOTPENDING 0x00000000 2936 2937 // Field: [14] BUSFAULTPENDED 2938 // 2939 // BusFault pending 2940 // ENUMs: 2941 // PENDING Exception is pending. 2942 // NOTPENDING Exception is not active 2943 #define CPU_SCS_SHCSR_BUSFAULTPENDED 0x00004000 2944 #define CPU_SCS_SHCSR_BUSFAULTPENDED_BITN 14 2945 #define CPU_SCS_SHCSR_BUSFAULTPENDED_M 0x00004000 2946 #define CPU_SCS_SHCSR_BUSFAULTPENDED_S 14 2947 #define CPU_SCS_SHCSR_BUSFAULTPENDED_PENDING 0x00004000 2948 #define CPU_SCS_SHCSR_BUSFAULTPENDED_NOTPENDING 0x00000000 2949 2950 // Field: [13] MEMFAULTPENDED 2951 // 2952 // MemManage exception pending 2953 // ENUMs: 2954 // PENDING Exception is pending. 2955 // NOTPENDING Exception is not active 2956 #define CPU_SCS_SHCSR_MEMFAULTPENDED 0x00002000 2957 #define CPU_SCS_SHCSR_MEMFAULTPENDED_BITN 13 2958 #define CPU_SCS_SHCSR_MEMFAULTPENDED_M 0x00002000 2959 #define CPU_SCS_SHCSR_MEMFAULTPENDED_S 13 2960 #define CPU_SCS_SHCSR_MEMFAULTPENDED_PENDING 0x00002000 2961 #define CPU_SCS_SHCSR_MEMFAULTPENDED_NOTPENDING 0x00000000 2962 2963 // Field: [12] USGFAULTPENDED 2964 // 2965 // Usage fault pending 2966 // ENUMs: 2967 // PENDING Exception is pending. 2968 // NOTPENDING Exception is not active 2969 #define CPU_SCS_SHCSR_USGFAULTPENDED 0x00001000 2970 #define CPU_SCS_SHCSR_USGFAULTPENDED_BITN 12 2971 #define CPU_SCS_SHCSR_USGFAULTPENDED_M 0x00001000 2972 #define CPU_SCS_SHCSR_USGFAULTPENDED_S 12 2973 #define CPU_SCS_SHCSR_USGFAULTPENDED_PENDING 0x00001000 2974 #define CPU_SCS_SHCSR_USGFAULTPENDED_NOTPENDING 0x00000000 2975 2976 // Field: [11] SYSTICKACT 2977 // 2978 // SysTick active flag. 2979 // 2980 // 0x0: Not active 2981 // 0x1: Active 2982 // ENUMs: 2983 // ACTIVE Exception is active 2984 // NOTACTIVE Exception is not active 2985 #define CPU_SCS_SHCSR_SYSTICKACT 0x00000800 2986 #define CPU_SCS_SHCSR_SYSTICKACT_BITN 11 2987 #define CPU_SCS_SHCSR_SYSTICKACT_M 0x00000800 2988 #define CPU_SCS_SHCSR_SYSTICKACT_S 11 2989 #define CPU_SCS_SHCSR_SYSTICKACT_ACTIVE 0x00000800 2990 #define CPU_SCS_SHCSR_SYSTICKACT_NOTACTIVE 0x00000000 2991 2992 // Field: [10] PENDSVACT 2993 // 2994 // PendSV active 2995 // 2996 // 0x0: Not active 2997 // 0x1: Active 2998 #define CPU_SCS_SHCSR_PENDSVACT 0x00000400 2999 #define CPU_SCS_SHCSR_PENDSVACT_BITN 10 3000 #define CPU_SCS_SHCSR_PENDSVACT_M 0x00000400 3001 #define CPU_SCS_SHCSR_PENDSVACT_S 10 3002 3003 // Field: [8] MONITORACT 3004 // 3005 // Debug monitor active 3006 // ENUMs: 3007 // ACTIVE Exception is active 3008 // NOTACTIVE Exception is not active 3009 #define CPU_SCS_SHCSR_MONITORACT 0x00000100 3010 #define CPU_SCS_SHCSR_MONITORACT_BITN 8 3011 #define CPU_SCS_SHCSR_MONITORACT_M 0x00000100 3012 #define CPU_SCS_SHCSR_MONITORACT_S 8 3013 #define CPU_SCS_SHCSR_MONITORACT_ACTIVE 0x00000100 3014 #define CPU_SCS_SHCSR_MONITORACT_NOTACTIVE 0x00000000 3015 3016 // Field: [7] SVCALLACT 3017 // 3018 // SVCall active 3019 // ENUMs: 3020 // ACTIVE Exception is active 3021 // NOTACTIVE Exception is not active 3022 #define CPU_SCS_SHCSR_SVCALLACT 0x00000080 3023 #define CPU_SCS_SHCSR_SVCALLACT_BITN 7 3024 #define CPU_SCS_SHCSR_SVCALLACT_M 0x00000080 3025 #define CPU_SCS_SHCSR_SVCALLACT_S 7 3026 #define CPU_SCS_SHCSR_SVCALLACT_ACTIVE 0x00000080 3027 #define CPU_SCS_SHCSR_SVCALLACT_NOTACTIVE 0x00000000 3028 3029 // Field: [3] USGFAULTACT 3030 // 3031 // UsageFault exception active 3032 // ENUMs: 3033 // ACTIVE Exception is active 3034 // NOTACTIVE Exception is not active 3035 #define CPU_SCS_SHCSR_USGFAULTACT 0x00000008 3036 #define CPU_SCS_SHCSR_USGFAULTACT_BITN 3 3037 #define CPU_SCS_SHCSR_USGFAULTACT_M 0x00000008 3038 #define CPU_SCS_SHCSR_USGFAULTACT_S 3 3039 #define CPU_SCS_SHCSR_USGFAULTACT_ACTIVE 0x00000008 3040 #define CPU_SCS_SHCSR_USGFAULTACT_NOTACTIVE 0x00000000 3041 3042 // Field: [1] BUSFAULTACT 3043 // 3044 // BusFault exception active 3045 // ENUMs: 3046 // ACTIVE Exception is active 3047 // NOTACTIVE Exception is not active 3048 #define CPU_SCS_SHCSR_BUSFAULTACT 0x00000002 3049 #define CPU_SCS_SHCSR_BUSFAULTACT_BITN 1 3050 #define CPU_SCS_SHCSR_BUSFAULTACT_M 0x00000002 3051 #define CPU_SCS_SHCSR_BUSFAULTACT_S 1 3052 #define CPU_SCS_SHCSR_BUSFAULTACT_ACTIVE 0x00000002 3053 #define CPU_SCS_SHCSR_BUSFAULTACT_NOTACTIVE 0x00000000 3054 3055 // Field: [0] MEMFAULTACT 3056 // 3057 // MemManage exception active 3058 // ENUMs: 3059 // ACTIVE Exception is active 3060 // NOTACTIVE Exception is not active 3061 #define CPU_SCS_SHCSR_MEMFAULTACT 0x00000001 3062 #define CPU_SCS_SHCSR_MEMFAULTACT_BITN 0 3063 #define CPU_SCS_SHCSR_MEMFAULTACT_M 0x00000001 3064 #define CPU_SCS_SHCSR_MEMFAULTACT_S 0 3065 #define CPU_SCS_SHCSR_MEMFAULTACT_ACTIVE 0x00000001 3066 #define CPU_SCS_SHCSR_MEMFAULTACT_NOTACTIVE 0x00000000 3067 3068 //***************************************************************************** 3069 // 3070 // Register: CPU_SCS_O_CFSR 3071 // 3072 //***************************************************************************** 3073 // Field: [25] DIVBYZERO 3074 // 3075 // When CCR.DIV_0_TRP (see Configuration Control Register on page 8-26) is 3076 // enabled and an SDIV or UDIV instruction is used with a divisor of 0, this 3077 // fault occurs The instruction is executed and the return PC points to it. If 3078 // CCR.DIV_0_TRP is not set, then the divide returns a quotient of 0. 3079 #define CPU_SCS_CFSR_DIVBYZERO 0x02000000 3080 #define CPU_SCS_CFSR_DIVBYZERO_BITN 25 3081 #define CPU_SCS_CFSR_DIVBYZERO_M 0x02000000 3082 #define CPU_SCS_CFSR_DIVBYZERO_S 25 3083 3084 // Field: [24] UNALIGNED 3085 // 3086 // When CCR.UNALIGN_TRP is enabled, and there is an attempt to make an 3087 // unaligned memory access, then this fault occurs. Unaligned LDM/STM/LDRD/STRD 3088 // instructions always fault irrespective of the setting of CCR.UNALIGN_TRP. 3089 #define CPU_SCS_CFSR_UNALIGNED 0x01000000 3090 #define CPU_SCS_CFSR_UNALIGNED_BITN 24 3091 #define CPU_SCS_CFSR_UNALIGNED_M 0x01000000 3092 #define CPU_SCS_CFSR_UNALIGNED_S 24 3093 3094 // Field: [19] NOCP 3095 // 3096 // Attempt to use a coprocessor instruction. The processor does not support 3097 // coprocessor instructions. 3098 #define CPU_SCS_CFSR_NOCP 0x00080000 3099 #define CPU_SCS_CFSR_NOCP_BITN 19 3100 #define CPU_SCS_CFSR_NOCP_M 0x00080000 3101 #define CPU_SCS_CFSR_NOCP_S 19 3102 3103 // Field: [18] INVPC 3104 // 3105 // Attempt to load EXC_RETURN into PC illegally. Invalid instruction, invalid 3106 // context, invalid value. The return PC points to the instruction that tried 3107 // to set the PC. 3108 #define CPU_SCS_CFSR_INVPC 0x00040000 3109 #define CPU_SCS_CFSR_INVPC_BITN 18 3110 #define CPU_SCS_CFSR_INVPC_M 0x00040000 3111 #define CPU_SCS_CFSR_INVPC_S 18 3112 3113 // Field: [17] INVSTATE 3114 // 3115 // Indicates an attempt to execute in an invalid EPSR state (e.g. after a BX 3116 // type instruction has changed state). This includes state change after entry 3117 // to or return from exception, as well as from inter-working instructions. 3118 // Return PC points to faulting instruction, with the invalid state. 3119 #define CPU_SCS_CFSR_INVSTATE 0x00020000 3120 #define CPU_SCS_CFSR_INVSTATE_BITN 17 3121 #define CPU_SCS_CFSR_INVSTATE_M 0x00020000 3122 #define CPU_SCS_CFSR_INVSTATE_S 17 3123 3124 // Field: [16] UNDEFINSTR 3125 // 3126 // This bit is set when the processor attempts to execute an undefined 3127 // instruction. This is an instruction that the processor cannot decode. The 3128 // return PC points to the undefined instruction. 3129 #define CPU_SCS_CFSR_UNDEFINSTR 0x00010000 3130 #define CPU_SCS_CFSR_UNDEFINSTR_BITN 16 3131 #define CPU_SCS_CFSR_UNDEFINSTR_M 0x00010000 3132 #define CPU_SCS_CFSR_UNDEFINSTR_S 16 3133 3134 // Field: [15] BFARVALID 3135 // 3136 // This bit is set if the Bus Fault Address Register (BFAR) contains a valid 3137 // address. This is true after a bus fault where the address is known. Other 3138 // faults can clear this bit, such as a Mem Manage fault occurring later. If a 3139 // Bus fault occurs that is escalated to a Hard Fault because of priority, the 3140 // Hard Fault handler must clear this bit. This prevents problems if returning 3141 // to a stacked active Bus fault handler whose BFAR value has been overwritten. 3142 #define CPU_SCS_CFSR_BFARVALID 0x00008000 3143 #define CPU_SCS_CFSR_BFARVALID_BITN 15 3144 #define CPU_SCS_CFSR_BFARVALID_M 0x00008000 3145 #define CPU_SCS_CFSR_BFARVALID_S 15 3146 3147 // Field: [12] STKERR 3148 // 3149 // Stacking from exception has caused one or more bus faults. The SP is still 3150 // adjusted and the values in the context area on the stack might be incorrect. 3151 // BFAR is not written. 3152 #define CPU_SCS_CFSR_STKERR 0x00001000 3153 #define CPU_SCS_CFSR_STKERR_BITN 12 3154 #define CPU_SCS_CFSR_STKERR_M 0x00001000 3155 #define CPU_SCS_CFSR_STKERR_S 12 3156 3157 // Field: [11] UNSTKERR 3158 // 3159 // Unstack from exception return has caused one or more bus faults. This is 3160 // chained to the handler, so that the original return stack is still present. 3161 // SP is not adjusted from failing return and new save is not performed. BFAR 3162 // is not written. 3163 #define CPU_SCS_CFSR_UNSTKERR 0x00000800 3164 #define CPU_SCS_CFSR_UNSTKERR_BITN 11 3165 #define CPU_SCS_CFSR_UNSTKERR_M 0x00000800 3166 #define CPU_SCS_CFSR_UNSTKERR_S 11 3167 3168 // Field: [10] IMPRECISERR 3169 // 3170 // Imprecise data bus error. It is a BusFault, but the Return PC is not related 3171 // to the causing instruction. This is not a synchronous fault. So, if detected 3172 // when the priority of the current activation is higher than the Bus Fault, it 3173 // only pends. Bus fault activates when returning to a lower priority 3174 // activation. If a precise fault occurs before returning to a lower priority 3175 // exception, the handler detects both IMPRECISERR set and one of the precise 3176 // fault status bits set at the same time. BFAR is not written. 3177 #define CPU_SCS_CFSR_IMPRECISERR 0x00000400 3178 #define CPU_SCS_CFSR_IMPRECISERR_BITN 10 3179 #define CPU_SCS_CFSR_IMPRECISERR_M 0x00000400 3180 #define CPU_SCS_CFSR_IMPRECISERR_S 10 3181 3182 // Field: [9] PRECISERR 3183 // 3184 // Precise data bus error return. 3185 #define CPU_SCS_CFSR_PRECISERR 0x00000200 3186 #define CPU_SCS_CFSR_PRECISERR_BITN 9 3187 #define CPU_SCS_CFSR_PRECISERR_M 0x00000200 3188 #define CPU_SCS_CFSR_PRECISERR_S 9 3189 3190 // Field: [8] IBUSERR 3191 // 3192 // Instruction bus error flag. This flag is set by a prefetch error. The fault 3193 // stops on the instruction, so if the error occurs under a branch shadow, no 3194 // fault occurs. BFAR is not written. 3195 #define CPU_SCS_CFSR_IBUSERR 0x00000100 3196 #define CPU_SCS_CFSR_IBUSERR_BITN 8 3197 #define CPU_SCS_CFSR_IBUSERR_M 0x00000100 3198 #define CPU_SCS_CFSR_IBUSERR_S 8 3199 3200 // Field: [7] MMARVALID 3201 // 3202 // Memory Manage Address Register (MMFAR) address valid flag. A later-arriving 3203 // fault, such as a bus fault, can clear a memory manage fault.. If a MemManage 3204 // fault occurs that is escalated to a Hard Fault because of priority, the Hard 3205 // Fault handler must clear this bit. This prevents problems on return to a 3206 // stacked active MemManage handler whose MMFAR value has been overwritten. 3207 #define CPU_SCS_CFSR_MMARVALID 0x00000080 3208 #define CPU_SCS_CFSR_MMARVALID_BITN 7 3209 #define CPU_SCS_CFSR_MMARVALID_M 0x00000080 3210 #define CPU_SCS_CFSR_MMARVALID_S 7 3211 3212 // Field: [4] MSTKERR 3213 // 3214 // Stacking from exception has caused one or more access violations. The SP is 3215 // still adjusted and the values in the context area on the stack might be 3216 // incorrect. MMFAR is not written. 3217 #define CPU_SCS_CFSR_MSTKERR 0x00000010 3218 #define CPU_SCS_CFSR_MSTKERR_BITN 4 3219 #define CPU_SCS_CFSR_MSTKERR_M 0x00000010 3220 #define CPU_SCS_CFSR_MSTKERR_S 4 3221 3222 // Field: [3] MUNSTKERR 3223 // 3224 // Unstack from exception return has caused one or more access violations. This 3225 // is chained to the handler, so that the original return stack is still 3226 // present. SP is not adjusted from failing return and new save is not 3227 // performed. MMFAR is not written. 3228 #define CPU_SCS_CFSR_MUNSTKERR 0x00000008 3229 #define CPU_SCS_CFSR_MUNSTKERR_BITN 3 3230 #define CPU_SCS_CFSR_MUNSTKERR_M 0x00000008 3231 #define CPU_SCS_CFSR_MUNSTKERR_S 3 3232 3233 // Field: [1] DACCVIOL 3234 // 3235 // Data access violation flag. Attempting to load or store at a location that 3236 // does not permit the operation sets this flag. The return PC points to the 3237 // faulting instruction. This error loads MMFAR with the address of the 3238 // attempted access. 3239 #define CPU_SCS_CFSR_DACCVIOL 0x00000002 3240 #define CPU_SCS_CFSR_DACCVIOL_BITN 1 3241 #define CPU_SCS_CFSR_DACCVIOL_M 0x00000002 3242 #define CPU_SCS_CFSR_DACCVIOL_S 1 3243 3244 // Field: [0] IACCVIOL 3245 // 3246 // Instruction access violation flag. Attempting to fetch an instruction from a 3247 // location that does not permit execution sets this flag. This occurs on any 3248 // access to an XN region, even when the MPU is disabled or not present. The 3249 // return PC points to the faulting instruction. MMFAR is not written. 3250 #define CPU_SCS_CFSR_IACCVIOL 0x00000001 3251 #define CPU_SCS_CFSR_IACCVIOL_BITN 0 3252 #define CPU_SCS_CFSR_IACCVIOL_M 0x00000001 3253 #define CPU_SCS_CFSR_IACCVIOL_S 0 3254 3255 //***************************************************************************** 3256 // 3257 // Register: CPU_SCS_O_HFSR 3258 // 3259 //***************************************************************************** 3260 // Field: [31] DEBUGEVT 3261 // 3262 // This bit is set if there is a fault related to debug. This is only possible 3263 // when halting debug is not enabled. For monitor enabled debug, it only 3264 // happens for BKPT when the current priority is higher than the monitor. When 3265 // both halting and monitor debug are disabled, it only happens for debug 3266 // events that are not ignored (minimally, BKPT). The Debug Fault Status 3267 // Register is updated. 3268 #define CPU_SCS_HFSR_DEBUGEVT 0x80000000 3269 #define CPU_SCS_HFSR_DEBUGEVT_BITN 31 3270 #define CPU_SCS_HFSR_DEBUGEVT_M 0x80000000 3271 #define CPU_SCS_HFSR_DEBUGEVT_S 31 3272 3273 // Field: [30] FORCED 3274 // 3275 // Hard Fault activated because a Configurable Fault was received and cannot 3276 // activate because of priority or because the Configurable Fault is disabled. 3277 // The Hard Fault handler then has to read the other fault status registers to 3278 // determine cause. 3279 #define CPU_SCS_HFSR_FORCED 0x40000000 3280 #define CPU_SCS_HFSR_FORCED_BITN 30 3281 #define CPU_SCS_HFSR_FORCED_M 0x40000000 3282 #define CPU_SCS_HFSR_FORCED_S 30 3283 3284 // Field: [1] VECTTBL 3285 // 3286 // This bit is set if there is a fault because of vector table read on 3287 // exception processing (Bus Fault). This case is always a Hard Fault. The 3288 // return PC points to the pre-empted instruction. 3289 #define CPU_SCS_HFSR_VECTTBL 0x00000002 3290 #define CPU_SCS_HFSR_VECTTBL_BITN 1 3291 #define CPU_SCS_HFSR_VECTTBL_M 0x00000002 3292 #define CPU_SCS_HFSR_VECTTBL_S 1 3293 3294 //***************************************************************************** 3295 // 3296 // Register: CPU_SCS_O_DFSR 3297 // 3298 //***************************************************************************** 3299 // Field: [4] EXTERNAL 3300 // 3301 // External debug request flag. The processor stops on next instruction 3302 // boundary. 3303 // 3304 // 0x0: External debug request signal not asserted 3305 // 0x1: External debug request signal asserted 3306 #define CPU_SCS_DFSR_EXTERNAL 0x00000010 3307 #define CPU_SCS_DFSR_EXTERNAL_BITN 4 3308 #define CPU_SCS_DFSR_EXTERNAL_M 0x00000010 3309 #define CPU_SCS_DFSR_EXTERNAL_S 4 3310 3311 // Field: [3] VCATCH 3312 // 3313 // Vector catch flag. When this flag is set, a flag in one of the local fault 3314 // status registers is also set to indicate the type of fault. 3315 // 3316 // 0x0: No vector catch occurred 3317 // 0x1: Vector catch occurred 3318 #define CPU_SCS_DFSR_VCATCH 0x00000008 3319 #define CPU_SCS_DFSR_VCATCH_BITN 3 3320 #define CPU_SCS_DFSR_VCATCH_M 0x00000008 3321 #define CPU_SCS_DFSR_VCATCH_S 3 3322 3323 // Field: [2] DWTTRAP 3324 // 3325 // Data Watchpoint and Trace (DWT) flag. The processor stops at the current 3326 // instruction or at the next instruction. 3327 // 3328 // 0x0: No DWT match 3329 // 0x1: DWT match 3330 #define CPU_SCS_DFSR_DWTTRAP 0x00000004 3331 #define CPU_SCS_DFSR_DWTTRAP_BITN 2 3332 #define CPU_SCS_DFSR_DWTTRAP_M 0x00000004 3333 #define CPU_SCS_DFSR_DWTTRAP_S 2 3334 3335 // Field: [1] BKPT 3336 // 3337 // BKPT flag. The BKPT flag is set by a BKPT instruction in flash patch code, 3338 // and also by normal code. Return PC points to breakpoint containing 3339 // instruction. 3340 // 3341 // 0x0: No BKPT instruction execution 3342 // 0x1: BKPT instruction execution 3343 #define CPU_SCS_DFSR_BKPT 0x00000002 3344 #define CPU_SCS_DFSR_BKPT_BITN 1 3345 #define CPU_SCS_DFSR_BKPT_M 0x00000002 3346 #define CPU_SCS_DFSR_BKPT_S 1 3347 3348 // Field: [0] HALTED 3349 // 3350 // Halt request flag. The processor is halted on the next instruction. 3351 // 3352 // 0x0: No halt request 3353 // 0x1: Halt requested by NVIC, including step 3354 #define CPU_SCS_DFSR_HALTED 0x00000001 3355 #define CPU_SCS_DFSR_HALTED_BITN 0 3356 #define CPU_SCS_DFSR_HALTED_M 0x00000001 3357 #define CPU_SCS_DFSR_HALTED_S 0 3358 3359 //***************************************************************************** 3360 // 3361 // Register: CPU_SCS_O_MMFAR 3362 // 3363 //***************************************************************************** 3364 // Field: [31:0] ADDRESS 3365 // 3366 // Mem Manage fault address field. 3367 // This field is the data address of a faulted load or store attempt. When an 3368 // unaligned access faults, the address is the actual address that faulted. 3369 // Because an access can be split into multiple parts, each aligned, this 3370 // address can be any offset in the range of the requested size. Flags 3371 // CFSR.IACCVIOL, CFSR.DACCVIOL ,CFSR.MUNSTKERR and CFSR.MSTKERR in combination 3372 // with CFSR.MMARVALIDindicate the cause of the fault. 3373 #define CPU_SCS_MMFAR_ADDRESS_W 32 3374 #define CPU_SCS_MMFAR_ADDRESS_M 0xFFFFFFFF 3375 #define CPU_SCS_MMFAR_ADDRESS_S 0 3376 3377 //***************************************************************************** 3378 // 3379 // Register: CPU_SCS_O_BFAR 3380 // 3381 //***************************************************************************** 3382 // Field: [31:0] ADDRESS 3383 // 3384 // Bus fault address field. This field is the data address of a faulted load or 3385 // store attempt. When an unaligned access faults, the address is the address 3386 // requested by the instruction, even if that is not the address that faulted. 3387 // Flags CFSR.IBUSERR, CFSR.PRECISERR, CFSR.IMPRECISERR, CFSR.UNSTKERR and 3388 // CFSR.STKERR in combination with CFSR.BFARVALID indicate the cause of the 3389 // fault. 3390 #define CPU_SCS_BFAR_ADDRESS_W 32 3391 #define CPU_SCS_BFAR_ADDRESS_M 0xFFFFFFFF 3392 #define CPU_SCS_BFAR_ADDRESS_S 0 3393 3394 //***************************************************************************** 3395 // 3396 // Register: CPU_SCS_O_AFSR 3397 // 3398 //***************************************************************************** 3399 // Field: [31:0] IMPDEF 3400 // 3401 // Implementation defined. The bits map directly onto the signal assignment to 3402 // the auxiliary fault inputs. Tied to 0 3403 #define CPU_SCS_AFSR_IMPDEF_W 32 3404 #define CPU_SCS_AFSR_IMPDEF_M 0xFFFFFFFF 3405 #define CPU_SCS_AFSR_IMPDEF_S 0 3406 3407 //***************************************************************************** 3408 // 3409 // Register: CPU_SCS_O_ID_PFR0 3410 // 3411 //***************************************************************************** 3412 // Field: [7:4] STATE1 3413 // 3414 // State1 (T-bit == 1) 3415 // 3416 // 0x0: N/A 3417 // 0x1: N/A 3418 // 0x2: Thumb-2 encoding with the 16-bit basic instructions plus 32-bit 3419 // Buncond/BL but no other 32-bit basic instructions (Note non-basic 32-bit 3420 // instructions can be added using the appropriate instruction attribute, but 3421 // other 32-bit basic instructions cannot.) 3422 // 0x3: Thumb-2 encoding with all Thumb-2 basic instructions 3423 #define CPU_SCS_ID_PFR0_STATE1_W 4 3424 #define CPU_SCS_ID_PFR0_STATE1_M 0x000000F0 3425 #define CPU_SCS_ID_PFR0_STATE1_S 4 3426 3427 // Field: [3:0] STATE0 3428 // 3429 // State0 (T-bit == 0) 3430 // 3431 // 0x0: No ARM encoding 3432 // 0x1: N/A 3433 #define CPU_SCS_ID_PFR0_STATE0_W 4 3434 #define CPU_SCS_ID_PFR0_STATE0_M 0x0000000F 3435 #define CPU_SCS_ID_PFR0_STATE0_S 0 3436 3437 //***************************************************************************** 3438 // 3439 // Register: CPU_SCS_O_ID_PFR1 3440 // 3441 //***************************************************************************** 3442 // Field: [11:8] MICROCONTROLLER_PROGRAMMERS_MODEL 3443 // 3444 // Microcontroller programmer's model 3445 // 3446 // 0x0: Not supported 3447 // 0x2: Two-stack support 3448 #define CPU_SCS_ID_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_W 4 3449 #define CPU_SCS_ID_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_M 0x00000F00 3450 #define CPU_SCS_ID_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_S 8 3451 3452 //***************************************************************************** 3453 // 3454 // Register: CPU_SCS_O_ID_DFR0 3455 // 3456 //***************************************************************************** 3457 // Field: [23:20] MICROCONTROLLER_DEBUG_MODEL 3458 // 3459 // Microcontroller Debug Model - memory mapped 3460 // 3461 // 0x0: Not supported 3462 // 0x1: Microcontroller debug v1 (ITMv1 and DWTv1) 3463 #define CPU_SCS_ID_DFR0_MICROCONTROLLER_DEBUG_MODEL_W 4 3464 #define CPU_SCS_ID_DFR0_MICROCONTROLLER_DEBUG_MODEL_M 0x00F00000 3465 #define CPU_SCS_ID_DFR0_MICROCONTROLLER_DEBUG_MODEL_S 20 3466 3467 //***************************************************************************** 3468 // 3469 // Register: CPU_SCS_O_ID_AFR0 3470 // 3471 //***************************************************************************** 3472 //***************************************************************************** 3473 // 3474 // Register: CPU_SCS_O_ID_MMFR0 3475 // 3476 //***************************************************************************** 3477 //***************************************************************************** 3478 // 3479 // Register: CPU_SCS_O_ID_MMFR1 3480 // 3481 //***************************************************************************** 3482 //***************************************************************************** 3483 // 3484 // Register: CPU_SCS_O_ID_MMFR2 3485 // 3486 //***************************************************************************** 3487 // Field: [24] WAIT_FOR_INTERRUPT_STALLING 3488 // 3489 // wait for interrupt stalling 3490 // 3491 // 0x0: Not supported 3492 // 0x1: Wait for interrupt supported 3493 #define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING 0x01000000 3494 #define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING_BITN 24 3495 #define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING_M 0x01000000 3496 #define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING_S 24 3497 3498 //***************************************************************************** 3499 // 3500 // Register: CPU_SCS_O_ID_MMFR3 3501 // 3502 //***************************************************************************** 3503 //***************************************************************************** 3504 // 3505 // Register: CPU_SCS_O_ID_ISAR0 3506 // 3507 //***************************************************************************** 3508 //***************************************************************************** 3509 // 3510 // Register: CPU_SCS_O_ID_ISAR1 3511 // 3512 //***************************************************************************** 3513 //***************************************************************************** 3514 // 3515 // Register: CPU_SCS_O_ID_ISAR2 3516 // 3517 //***************************************************************************** 3518 //***************************************************************************** 3519 // 3520 // Register: CPU_SCS_O_ID_ISAR3 3521 // 3522 //***************************************************************************** 3523 //***************************************************************************** 3524 // 3525 // Register: CPU_SCS_O_ID_ISAR4 3526 // 3527 //***************************************************************************** 3528 //***************************************************************************** 3529 // 3530 // Register: CPU_SCS_O_CPACR 3531 // 3532 //***************************************************************************** 3533 //***************************************************************************** 3534 // 3535 // Register: CPU_SCS_O_DHCSR 3536 // 3537 //***************************************************************************** 3538 // Field: [25] S_RESET_ST 3539 // 3540 // Indicates that the core has been reset, or is now being reset, since the 3541 // last time this bit was read. This a sticky bit that clears on read. So, 3542 // reading twice and getting 1 then 0 means it was reset in the past. Reading 3543 // twice and getting 1 both times means that it is being reset now (held in 3544 // reset still). 3545 // When writing to this register, 0 must be written this bit-field, otherwise 3546 // the write operation is ignored and no bits are written into the register. 3547 #define CPU_SCS_DHCSR_S_RESET_ST 0x02000000 3548 #define CPU_SCS_DHCSR_S_RESET_ST_BITN 25 3549 #define CPU_SCS_DHCSR_S_RESET_ST_M 0x02000000 3550 #define CPU_SCS_DHCSR_S_RESET_ST_S 25 3551 3552 // Field: [24] S_RETIRE_ST 3553 // 3554 // Indicates that an instruction has completed since last read. This is a 3555 // sticky bit that clears on read. This determines if the core is stalled on a 3556 // load/store or fetch. 3557 // When writing to this register, 0 must be written this bit-field, otherwise 3558 // the write operation is ignored and no bits are written into the register. 3559 #define CPU_SCS_DHCSR_S_RETIRE_ST 0x01000000 3560 #define CPU_SCS_DHCSR_S_RETIRE_ST_BITN 24 3561 #define CPU_SCS_DHCSR_S_RETIRE_ST_M 0x01000000 3562 #define CPU_SCS_DHCSR_S_RETIRE_ST_S 24 3563 3564 // Field: [19] S_LOCKUP 3565 // 3566 // Reads as one if the core is running (not halted) and a lockup condition is 3567 // present. 3568 // When writing to this register, 1 must be written this bit-field, otherwise 3569 // the write operation is ignored and no bits are written into the register. 3570 #define CPU_SCS_DHCSR_S_LOCKUP 0x00080000 3571 #define CPU_SCS_DHCSR_S_LOCKUP_BITN 19 3572 #define CPU_SCS_DHCSR_S_LOCKUP_M 0x00080000 3573 #define CPU_SCS_DHCSR_S_LOCKUP_S 19 3574 3575 // Field: [18] S_SLEEP 3576 // 3577 // Indicates that the core is sleeping (WFI, WFE, or **SLEEP-ON-EXIT**). Must 3578 // use C_HALT to gain control or wait for interrupt to wake-up. 3579 // When writing to this register, 1 must be written this bit-field, otherwise 3580 // the write operation is ignored and no bits are written into the register. 3581 #define CPU_SCS_DHCSR_S_SLEEP 0x00040000 3582 #define CPU_SCS_DHCSR_S_SLEEP_BITN 18 3583 #define CPU_SCS_DHCSR_S_SLEEP_M 0x00040000 3584 #define CPU_SCS_DHCSR_S_SLEEP_S 18 3585 3586 // Field: [17] S_HALT 3587 // 3588 // The core is in debug state when this bit is set. 3589 // When writing to this register, 1 must be written this bit-field, otherwise 3590 // the write operation is ignored and no bits are written into the register. 3591 #define CPU_SCS_DHCSR_S_HALT 0x00020000 3592 #define CPU_SCS_DHCSR_S_HALT_BITN 17 3593 #define CPU_SCS_DHCSR_S_HALT_M 0x00020000 3594 #define CPU_SCS_DHCSR_S_HALT_S 17 3595 3596 // Field: [16] S_REGRDY 3597 // 3598 // Register Read/Write on the Debug Core Register Selector register is 3599 // available. Last transfer is complete. 3600 // When writing to this register, 1 must be written this bit-field, otherwise 3601 // the write operation is ignored and no bits are written into the register. 3602 #define CPU_SCS_DHCSR_S_REGRDY 0x00010000 3603 #define CPU_SCS_DHCSR_S_REGRDY_BITN 16 3604 #define CPU_SCS_DHCSR_S_REGRDY_M 0x00010000 3605 #define CPU_SCS_DHCSR_S_REGRDY_S 16 3606 3607 // Field: [5] C_SNAPSTALL 3608 // 3609 // If the core is stalled on a load/store operation the stall ceases and the 3610 // instruction is forced to complete. This enables Halting debug to gain 3611 // control of the core. It can only be set if: C_DEBUGEN = 1 and C_HALT = 1. 3612 // The core reads S_RETIRE_ST as 0. This indicates that no instruction has 3613 // advanced. This prevents misuse. The bus state is Unpredictable when this is 3614 // used. S_RETIRE_ST can detect core stalls on load/store operations. 3615 #define CPU_SCS_DHCSR_C_SNAPSTALL 0x00000020 3616 #define CPU_SCS_DHCSR_C_SNAPSTALL_BITN 5 3617 #define CPU_SCS_DHCSR_C_SNAPSTALL_M 0x00000020 3618 #define CPU_SCS_DHCSR_C_SNAPSTALL_S 5 3619 3620 // Field: [3] C_MASKINTS 3621 // 3622 // Mask interrupts when stepping or running in halted debug. This masking does 3623 // not affect NMI, fault exceptions and SVC caused by execution of the 3624 // instructions. This bit must only be modified when the processor is halted 3625 // (S_HALT == 1). C_MASKINTS must be set or cleared before halt is released 3626 // (i.e., the writes to set or clear C_MASKINTS and to set or clear C_HALT must 3627 // be separate). Modifying C_MASKINTS while the system is running with halting 3628 // debug support enabled (C_DEBUGEN = 1, S_HALT = 0) may cause unpredictable 3629 // behavior. 3630 #define CPU_SCS_DHCSR_C_MASKINTS 0x00000008 3631 #define CPU_SCS_DHCSR_C_MASKINTS_BITN 3 3632 #define CPU_SCS_DHCSR_C_MASKINTS_M 0x00000008 3633 #define CPU_SCS_DHCSR_C_MASKINTS_S 3 3634 3635 // Field: [2] C_STEP 3636 // 3637 // Steps the core in halted debug. When C_DEBUGEN = 0, this bit has no effect. 3638 // Must only be modified when the processor is halted (S_HALT == 1). 3639 // Modifying C_STEP while the system is running with halting debug support 3640 // enabled (C_DEBUGEN = 1, S_HALT = 0) may cause unpredictable behavior. 3641 #define CPU_SCS_DHCSR_C_STEP 0x00000004 3642 #define CPU_SCS_DHCSR_C_STEP_BITN 2 3643 #define CPU_SCS_DHCSR_C_STEP_M 0x00000004 3644 #define CPU_SCS_DHCSR_C_STEP_S 2 3645 3646 // Field: [1] C_HALT 3647 // 3648 // Halts the core. This bit is set automatically when the core Halts. For 3649 // example Breakpoint. This bit clears on core reset. 3650 #define CPU_SCS_DHCSR_C_HALT 0x00000002 3651 #define CPU_SCS_DHCSR_C_HALT_BITN 1 3652 #define CPU_SCS_DHCSR_C_HALT_M 0x00000002 3653 #define CPU_SCS_DHCSR_C_HALT_S 1 3654 3655 // Field: [0] C_DEBUGEN 3656 // 3657 // Enables debug. This can only be written by AHB-AP and not by the core. It is 3658 // ignored when written by the core, which cannot set or clear it. The core 3659 // must write a 1 to it when writing C_HALT to halt itself. 3660 // The values of C_HALT, C_STEP and C_MASKINTS are ignored by hardware when 3661 // C_DEBUGEN = 0. The read values for C_HALT, C_STEP and C_MASKINTS fields will 3662 // be unknown to software when C_DEBUGEN = 0. 3663 #define CPU_SCS_DHCSR_C_DEBUGEN 0x00000001 3664 #define CPU_SCS_DHCSR_C_DEBUGEN_BITN 0 3665 #define CPU_SCS_DHCSR_C_DEBUGEN_M 0x00000001 3666 #define CPU_SCS_DHCSR_C_DEBUGEN_S 0 3667 3668 //***************************************************************************** 3669 // 3670 // Register: CPU_SCS_O_DCRSR 3671 // 3672 //***************************************************************************** 3673 // Field: [16] REGWNR 3674 // 3675 // 1: Write 3676 // 0: Read 3677 #define CPU_SCS_DCRSR_REGWNR 0x00010000 3678 #define CPU_SCS_DCRSR_REGWNR_BITN 16 3679 #define CPU_SCS_DCRSR_REGWNR_M 0x00010000 3680 #define CPU_SCS_DCRSR_REGWNR_S 16 3681 3682 // Field: [4:0] REGSEL 3683 // 3684 // Register select 3685 // 3686 // 0x00: R0 3687 // 0x01: R1 3688 // 0x02: R2 3689 // 0x03: R3 3690 // 0x04: R4 3691 // 0x05: R5 3692 // 0x06: R6 3693 // 0x07: R7 3694 // 0x08: R8 3695 // 0x09: R9 3696 // 0x0A: R10 3697 // 0x0B: R11 3698 // 0x0C: R12 3699 // 0x0D: Current SP 3700 // 0x0E: LR 3701 // 0x0F: DebugReturnAddress 3702 // 0x10: XPSR/flags, execution state information, and exception number 3703 // 0x11: MSP (Main SP) 3704 // 0x12: PSP (Process SP) 3705 // 0x14: CONTROL<<24 | FAULTMASK<<16 | BASEPRI<<8 | PRIMASK 3706 #define CPU_SCS_DCRSR_REGSEL_W 5 3707 #define CPU_SCS_DCRSR_REGSEL_M 0x0000001F 3708 #define CPU_SCS_DCRSR_REGSEL_S 0 3709 3710 //***************************************************************************** 3711 // 3712 // Register: CPU_SCS_O_DCRDR 3713 // 3714 //***************************************************************************** 3715 // Field: [31:0] DCRDR 3716 // 3717 // This register holds data for reading and writing registers to and from the 3718 // processor. This is the data value written to the register selected by DCRSR. 3719 // When the processor receives a request from DCRSR, this register is read or 3720 // written by the processor using a normal load-store unit operation. If core 3721 // register transfers are not being performed, software-based debug monitors 3722 // can use this register for communication in non-halting debug. This enables 3723 // flags and bits to acknowledge state and indicate if commands have been 3724 // accepted to, replied to, or accepted and replied to. 3725 #define CPU_SCS_DCRDR_DCRDR_W 32 3726 #define CPU_SCS_DCRDR_DCRDR_M 0xFFFFFFFF 3727 #define CPU_SCS_DCRDR_DCRDR_S 0 3728 3729 //***************************************************************************** 3730 // 3731 // Register: CPU_SCS_O_DEMCR 3732 // 3733 //***************************************************************************** 3734 // Field: [24] TRCENA 3735 // 3736 // This bit must be set to 1 to enable use of the trace and debug blocks: DWT, 3737 // ITM, ETM and TPIU. This enables control of power usage unless tracing is 3738 // required. The application can enable this, for ITM use, or use by a 3739 // debugger. 3740 #define CPU_SCS_DEMCR_TRCENA 0x01000000 3741 #define CPU_SCS_DEMCR_TRCENA_BITN 24 3742 #define CPU_SCS_DEMCR_TRCENA_M 0x01000000 3743 #define CPU_SCS_DEMCR_TRCENA_S 24 3744 3745 // Field: [19] MON_REQ 3746 // 3747 // This enables the monitor to identify how it wakes up. This bit clears on a 3748 // Core Reset. 3749 // 3750 // 0x0: Woken up by debug exception. 3751 // 0x1: Woken up by MON_PEND 3752 #define CPU_SCS_DEMCR_MON_REQ 0x00080000 3753 #define CPU_SCS_DEMCR_MON_REQ_BITN 19 3754 #define CPU_SCS_DEMCR_MON_REQ_M 0x00080000 3755 #define CPU_SCS_DEMCR_MON_REQ_S 19 3756 3757 // Field: [18] MON_STEP 3758 // 3759 // When MON_EN = 1, this steps the core. When MON_EN = 0, this bit is ignored. 3760 // This is the equivalent to DHCSR.C_STEP. Interrupts are only stepped 3761 // according to the priority of the monitor and settings of PRIMASK, FAULTMASK, 3762 // or BASEPRI. 3763 #define CPU_SCS_DEMCR_MON_STEP 0x00040000 3764 #define CPU_SCS_DEMCR_MON_STEP_BITN 18 3765 #define CPU_SCS_DEMCR_MON_STEP_M 0x00040000 3766 #define CPU_SCS_DEMCR_MON_STEP_S 18 3767 3768 // Field: [17] MON_PEND 3769 // 3770 // Pend the monitor to activate when priority permits. This can wake up the 3771 // monitor through the AHB-AP port. It is the equivalent to DHCSR.C_HALT for 3772 // Monitor debug. This register does not reset on a system reset. It is only 3773 // reset by a power-on reset. Software in the reset handler or later, or by the 3774 // DAP must enable the debug monitor. 3775 #define CPU_SCS_DEMCR_MON_PEND 0x00020000 3776 #define CPU_SCS_DEMCR_MON_PEND_BITN 17 3777 #define CPU_SCS_DEMCR_MON_PEND_M 0x00020000 3778 #define CPU_SCS_DEMCR_MON_PEND_S 17 3779 3780 // Field: [16] MON_EN 3781 // 3782 // Enable the debug monitor. 3783 // When enabled, the System handler priority register controls its priority 3784 // level. If disabled, then all debug events go to Hard fault. DHCSR.C_DEBUGEN 3785 // overrides this bit. Vector catching is semi-synchronous. When a matching 3786 // event is seen, a Halt is requested. Because the processor can only halt on 3787 // an instruction boundary, it must wait until the next instruction boundary. 3788 // As a result, it stops on the first instruction of the exception handler. 3789 // However, two special cases exist when a vector catch has triggered: 1. If a 3790 // fault is taken during vectoring, vector read or stack push error, the halt 3791 // occurs on the corresponding fault handler, for the vector error or stack 3792 // push. 2. If a late arriving interrupt comes in during vectoring, it is not 3793 // taken. That is, an implementation that supports the late arrival 3794 // optimization must suppress it in this case. 3795 #define CPU_SCS_DEMCR_MON_EN 0x00010000 3796 #define CPU_SCS_DEMCR_MON_EN_BITN 16 3797 #define CPU_SCS_DEMCR_MON_EN_M 0x00010000 3798 #define CPU_SCS_DEMCR_MON_EN_S 16 3799 3800 // Field: [10] VC_HARDERR 3801 // 3802 // Debug trap on Hard Fault. Ignored when DHCSR.C_DEBUGEN is cleared. 3803 #define CPU_SCS_DEMCR_VC_HARDERR 0x00000400 3804 #define CPU_SCS_DEMCR_VC_HARDERR_BITN 10 3805 #define CPU_SCS_DEMCR_VC_HARDERR_M 0x00000400 3806 #define CPU_SCS_DEMCR_VC_HARDERR_S 10 3807 3808 // Field: [9] VC_INTERR 3809 // 3810 // Debug trap on a fault occurring during an exception entry or return 3811 // sequence. Ignored when DHCSR.C_DEBUGEN is cleared. 3812 #define CPU_SCS_DEMCR_VC_INTERR 0x00000200 3813 #define CPU_SCS_DEMCR_VC_INTERR_BITN 9 3814 #define CPU_SCS_DEMCR_VC_INTERR_M 0x00000200 3815 #define CPU_SCS_DEMCR_VC_INTERR_S 9 3816 3817 // Field: [8] VC_BUSERR 3818 // 3819 // Debug Trap on normal Bus error. Ignored when DHCSR.C_DEBUGEN is cleared. 3820 #define CPU_SCS_DEMCR_VC_BUSERR 0x00000100 3821 #define CPU_SCS_DEMCR_VC_BUSERR_BITN 8 3822 #define CPU_SCS_DEMCR_VC_BUSERR_M 0x00000100 3823 #define CPU_SCS_DEMCR_VC_BUSERR_S 8 3824 3825 // Field: [7] VC_STATERR 3826 // 3827 // Debug trap on Usage Fault state errors. Ignored when DHCSR.C_DEBUGEN is 3828 // cleared. 3829 #define CPU_SCS_DEMCR_VC_STATERR 0x00000080 3830 #define CPU_SCS_DEMCR_VC_STATERR_BITN 7 3831 #define CPU_SCS_DEMCR_VC_STATERR_M 0x00000080 3832 #define CPU_SCS_DEMCR_VC_STATERR_S 7 3833 3834 // Field: [6] VC_CHKERR 3835 // 3836 // Debug trap on Usage Fault enabled checking errors. Ignored when 3837 // DHCSR.C_DEBUGEN is cleared. 3838 #define CPU_SCS_DEMCR_VC_CHKERR 0x00000040 3839 #define CPU_SCS_DEMCR_VC_CHKERR_BITN 6 3840 #define CPU_SCS_DEMCR_VC_CHKERR_M 0x00000040 3841 #define CPU_SCS_DEMCR_VC_CHKERR_S 6 3842 3843 // Field: [5] VC_NOCPERR 3844 // 3845 // Debug trap on a UsageFault access to a Coprocessor. Ignored when 3846 // DHCSR.C_DEBUGEN is cleared. 3847 #define CPU_SCS_DEMCR_VC_NOCPERR 0x00000020 3848 #define CPU_SCS_DEMCR_VC_NOCPERR_BITN 5 3849 #define CPU_SCS_DEMCR_VC_NOCPERR_M 0x00000020 3850 #define CPU_SCS_DEMCR_VC_NOCPERR_S 5 3851 3852 // Field: [4] VC_MMERR 3853 // 3854 // Debug trap on Memory Management faults. Ignored when DHCSR.C_DEBUGEN is 3855 // cleared. 3856 #define CPU_SCS_DEMCR_VC_MMERR 0x00000010 3857 #define CPU_SCS_DEMCR_VC_MMERR_BITN 4 3858 #define CPU_SCS_DEMCR_VC_MMERR_M 0x00000010 3859 #define CPU_SCS_DEMCR_VC_MMERR_S 4 3860 3861 // Field: [0] VC_CORERESET 3862 // 3863 // Reset Vector Catch. Halt running system if Core reset occurs. Ignored when 3864 // DHCSR.C_DEBUGEN is cleared. 3865 #define CPU_SCS_DEMCR_VC_CORERESET 0x00000001 3866 #define CPU_SCS_DEMCR_VC_CORERESET_BITN 0 3867 #define CPU_SCS_DEMCR_VC_CORERESET_M 0x00000001 3868 #define CPU_SCS_DEMCR_VC_CORERESET_S 0 3869 3870 //***************************************************************************** 3871 // 3872 // Register: CPU_SCS_O_STIR 3873 // 3874 //***************************************************************************** 3875 // Field: [8:0] INTID 3876 // 3877 // Interrupt ID field. Writing a value to this bit-field is the same as 3878 // manually pending an interrupt by setting the corresponding interrupt bit in 3879 // an Interrupt Set Pending Register in NVIC_ISPR0 or NVIC_ISPR1. 3880 #define CPU_SCS_STIR_INTID_W 9 3881 #define CPU_SCS_STIR_INTID_M 0x000001FF 3882 #define CPU_SCS_STIR_INTID_S 0 3883 3884 3885 #endif // __CPU_SCS__ 3886