1 /****************************************************************************** 2 * Filename: hw_cpu_tpiu_h 3 * Revised: 2015-11-12 13:07:02 +0100 (Thu, 12 Nov 2015) 4 * Revision: 45056 5 * 6 * Copyright (c) 2015, Texas Instruments Incorporated 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions are met: 11 * 12 * 1) Redistributions of source code must retain the above copyright notice, 13 * this list of conditions and the following disclaimer. 14 * 15 * 2) Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 19 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may 20 * be used to endorse or promote products derived from this software without 21 * specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 * 35 ******************************************************************************/ 36 37 #ifndef __HW_CPU_TPIU_H__ 38 #define __HW_CPU_TPIU_H__ 39 40 //***************************************************************************** 41 // 42 // This section defines the register offsets of 43 // CPU_TPIU component 44 // 45 //***************************************************************************** 46 // Supported Sync Port Sizes 47 #define CPU_TPIU_O_SSPSR 0x00000000 48 49 // Current Sync Port Size 50 #define CPU_TPIU_O_CSPSR 0x00000004 51 52 // Async Clock Prescaler 53 #define CPU_TPIU_O_ACPR 0x00000010 54 55 // Selected Pin Protocol 56 #define CPU_TPIU_O_SPPR 0x000000F0 57 58 // Formatter and Flush Status 59 #define CPU_TPIU_O_FFSR 0x00000300 60 61 // Formatter and Flush Control 62 #define CPU_TPIU_O_FFCR 0x00000304 63 64 // Formatter Synchronization Counter 65 #define CPU_TPIU_O_FSCR 0x00000308 66 67 // Claim Tag Mask 68 #define CPU_TPIU_O_CLAIMMASK 0x00000FA0 69 70 // Claim Tag Set 71 #define CPU_TPIU_O_CLAIMSET 0x00000FA0 72 73 // Current Claim Tag 74 #define CPU_TPIU_O_CLAIMTAG 0x00000FA4 75 76 // Claim Tag Clear 77 #define CPU_TPIU_O_CLAIMCLR 0x00000FA4 78 79 // Device ID 80 #define CPU_TPIU_O_DEVID 0x00000FC8 81 82 //***************************************************************************** 83 // 84 // Register: CPU_TPIU_O_SSPSR 85 // 86 //***************************************************************************** 87 // Field: [3] FOUR 88 // 89 // 4-bit port size support 90 // 91 // 0x0: Not supported 92 // 0x1: Supported 93 #define CPU_TPIU_SSPSR_FOUR 0x00000008 94 #define CPU_TPIU_SSPSR_FOUR_BITN 3 95 #define CPU_TPIU_SSPSR_FOUR_M 0x00000008 96 #define CPU_TPIU_SSPSR_FOUR_S 3 97 98 // Field: [2] THREE 99 // 100 // 3-bit port size support 101 // 102 // 0x0: Not supported 103 // 0x1: Supported 104 #define CPU_TPIU_SSPSR_THREE 0x00000004 105 #define CPU_TPIU_SSPSR_THREE_BITN 2 106 #define CPU_TPIU_SSPSR_THREE_M 0x00000004 107 #define CPU_TPIU_SSPSR_THREE_S 2 108 109 // Field: [1] TWO 110 // 111 // 2-bit port size support 112 // 113 // 0x0: Not supported 114 // 0x1: Supported 115 #define CPU_TPIU_SSPSR_TWO 0x00000002 116 #define CPU_TPIU_SSPSR_TWO_BITN 1 117 #define CPU_TPIU_SSPSR_TWO_M 0x00000002 118 #define CPU_TPIU_SSPSR_TWO_S 1 119 120 // Field: [0] ONE 121 // 122 // 1-bit port size support 123 // 124 // 0x0: Not supported 125 // 0x1: Supported 126 #define CPU_TPIU_SSPSR_ONE 0x00000001 127 #define CPU_TPIU_SSPSR_ONE_BITN 0 128 #define CPU_TPIU_SSPSR_ONE_M 0x00000001 129 #define CPU_TPIU_SSPSR_ONE_S 0 130 131 //***************************************************************************** 132 // 133 // Register: CPU_TPIU_O_CSPSR 134 // 135 //***************************************************************************** 136 // Field: [3] FOUR 137 // 138 // 4-bit port enable 139 // Writing values with more than one bit set in CSPSR, or setting a bit that is 140 // not indicated as supported in SSPSR can cause Unpredictable behavior. 141 #define CPU_TPIU_CSPSR_FOUR 0x00000008 142 #define CPU_TPIU_CSPSR_FOUR_BITN 3 143 #define CPU_TPIU_CSPSR_FOUR_M 0x00000008 144 #define CPU_TPIU_CSPSR_FOUR_S 3 145 146 // Field: [2] THREE 147 // 148 // 3-bit port enable 149 // Writing values with more than one bit set in CSPSR, or setting a bit that is 150 // not indicated as supported in SSPSR can cause Unpredictable behavior. 151 #define CPU_TPIU_CSPSR_THREE 0x00000004 152 #define CPU_TPIU_CSPSR_THREE_BITN 2 153 #define CPU_TPIU_CSPSR_THREE_M 0x00000004 154 #define CPU_TPIU_CSPSR_THREE_S 2 155 156 // Field: [1] TWO 157 // 158 // 2-bit port enable 159 // Writing values with more than one bit set in CSPSR, or setting a bit that is 160 // not indicated as supported in SSPSR can cause Unpredictable behavior. 161 #define CPU_TPIU_CSPSR_TWO 0x00000002 162 #define CPU_TPIU_CSPSR_TWO_BITN 1 163 #define CPU_TPIU_CSPSR_TWO_M 0x00000002 164 #define CPU_TPIU_CSPSR_TWO_S 1 165 166 // Field: [0] ONE 167 // 168 // 1-bit port enable 169 // Writing values with more than one bit set in CSPSR, or setting a bit that is 170 // not indicated as supported in SSPSR can cause Unpredictable behavior. 171 #define CPU_TPIU_CSPSR_ONE 0x00000001 172 #define CPU_TPIU_CSPSR_ONE_BITN 0 173 #define CPU_TPIU_CSPSR_ONE_M 0x00000001 174 #define CPU_TPIU_CSPSR_ONE_S 0 175 176 //***************************************************************************** 177 // 178 // Register: CPU_TPIU_O_ACPR 179 // 180 //***************************************************************************** 181 // Field: [12:0] PRESCALER 182 // 183 // Divisor for input trace clock is (PRESCALER + 1). 184 #define CPU_TPIU_ACPR_PRESCALER_W 13 185 #define CPU_TPIU_ACPR_PRESCALER_M 0x00001FFF 186 #define CPU_TPIU_ACPR_PRESCALER_S 0 187 188 //***************************************************************************** 189 // 190 // Register: CPU_TPIU_O_SPPR 191 // 192 //***************************************************************************** 193 // Field: [1:0] PROTOCOL 194 // 195 // Trace output protocol 196 // ENUMs: 197 // SWO_NRZ SerialWire Output (NRZ) 198 // SWO_MANCHESTER SerialWire Output (Manchester). This is the reset 199 // value. 200 // TRACEPORT TracePort mode 201 #define CPU_TPIU_SPPR_PROTOCOL_W 2 202 #define CPU_TPIU_SPPR_PROTOCOL_M 0x00000003 203 #define CPU_TPIU_SPPR_PROTOCOL_S 0 204 #define CPU_TPIU_SPPR_PROTOCOL_SWO_NRZ 0x00000002 205 #define CPU_TPIU_SPPR_PROTOCOL_SWO_MANCHESTER 0x00000001 206 #define CPU_TPIU_SPPR_PROTOCOL_TRACEPORT 0x00000000 207 208 //***************************************************************************** 209 // 210 // Register: CPU_TPIU_O_FFSR 211 // 212 //***************************************************************************** 213 // Field: [3] FTNONSTOP 214 // 215 // 0: Formatter can be stopped 216 // 1: Formatter cannot be stopped 217 #define CPU_TPIU_FFSR_FTNONSTOP 0x00000008 218 #define CPU_TPIU_FFSR_FTNONSTOP_BITN 3 219 #define CPU_TPIU_FFSR_FTNONSTOP_M 0x00000008 220 #define CPU_TPIU_FFSR_FTNONSTOP_S 3 221 222 //***************************************************************************** 223 // 224 // Register: CPU_TPIU_O_FFCR 225 // 226 //***************************************************************************** 227 // Field: [8] TRIGIN 228 // 229 // Indicates that triggers are inserted when a trigger pin is asserted. 230 #define CPU_TPIU_FFCR_TRIGIN 0x00000100 231 #define CPU_TPIU_FFCR_TRIGIN_BITN 8 232 #define CPU_TPIU_FFCR_TRIGIN_M 0x00000100 233 #define CPU_TPIU_FFCR_TRIGIN_S 8 234 235 // Field: [1] ENFCONT 236 // 237 // Enable continuous formatting: 238 // 239 // 0: Continuous formatting disabled 240 // 1: Continuous formatting enabled 241 #define CPU_TPIU_FFCR_ENFCONT 0x00000002 242 #define CPU_TPIU_FFCR_ENFCONT_BITN 1 243 #define CPU_TPIU_FFCR_ENFCONT_M 0x00000002 244 #define CPU_TPIU_FFCR_ENFCONT_S 1 245 246 //***************************************************************************** 247 // 248 // Register: CPU_TPIU_O_FSCR 249 // 250 //***************************************************************************** 251 // Field: [31:0] FSCR 252 // 253 // The global synchronization trigger is generated by the Program Counter (PC) 254 // Sampler block. This means that there is no synchronization counter in the 255 // TPIU. 256 #define CPU_TPIU_FSCR_FSCR_W 32 257 #define CPU_TPIU_FSCR_FSCR_M 0xFFFFFFFF 258 #define CPU_TPIU_FSCR_FSCR_S 0 259 260 //***************************************************************************** 261 // 262 // Register: CPU_TPIU_O_CLAIMMASK 263 // 264 //***************************************************************************** 265 // Field: [31:0] CLAIMMASK 266 // 267 // This register forms one half of the Claim Tag value. When reading this 268 // register returns the number of bits that can be set (each bit is considered 269 // separately): 270 // 271 // 0: This claim tag bit is not implemented 272 // 1: This claim tag bit is not implemented 273 // 274 // The behavior when writing to this register is described in CLAIMSET. 275 #define CPU_TPIU_CLAIMMASK_CLAIMMASK_W 32 276 #define CPU_TPIU_CLAIMMASK_CLAIMMASK_M 0xFFFFFFFF 277 #define CPU_TPIU_CLAIMMASK_CLAIMMASK_S 0 278 279 //***************************************************************************** 280 // 281 // Register: CPU_TPIU_O_CLAIMSET 282 // 283 //***************************************************************************** 284 // Field: [31:0] CLAIMSET 285 // 286 // This register forms one half of the Claim Tag value. Writing to this 287 // location allows individual bits to be set (each bit is considered 288 // separately): 289 // 290 // 0: No effect 291 // 1: Set this bit in the claim tag 292 // 293 // The behavior when reading from this location is described in CLAIMMASK. 294 #define CPU_TPIU_CLAIMSET_CLAIMSET_W 32 295 #define CPU_TPIU_CLAIMSET_CLAIMSET_M 0xFFFFFFFF 296 #define CPU_TPIU_CLAIMSET_CLAIMSET_S 0 297 298 //***************************************************************************** 299 // 300 // Register: CPU_TPIU_O_CLAIMTAG 301 // 302 //***************************************************************************** 303 // Field: [31:0] CLAIMTAG 304 // 305 // This register forms one half of the Claim Tag value. Reading this register 306 // returns the current Claim Tag value. 307 // Reading CLAIMMASK determines how many bits from this register must be used. 308 // 309 // The behavior when writing to this register is described in CLAIMCLR. 310 #define CPU_TPIU_CLAIMTAG_CLAIMTAG_W 32 311 #define CPU_TPIU_CLAIMTAG_CLAIMTAG_M 0xFFFFFFFF 312 #define CPU_TPIU_CLAIMTAG_CLAIMTAG_S 0 313 314 //***************************************************************************** 315 // 316 // Register: CPU_TPIU_O_CLAIMCLR 317 // 318 //***************************************************************************** 319 // Field: [31:0] CLAIMCLR 320 // 321 // This register forms one half of the Claim Tag value. Writing to this 322 // location enables individual bits to be cleared (each bit is considered 323 // separately): 324 // 325 // 0: No effect 326 // 1: Clear this bit in the claim tag. 327 // 328 // The behavior when reading from this location is described in CLAIMTAG. 329 #define CPU_TPIU_CLAIMCLR_CLAIMCLR_W 32 330 #define CPU_TPIU_CLAIMCLR_CLAIMCLR_M 0xFFFFFFFF 331 #define CPU_TPIU_CLAIMCLR_CLAIMCLR_S 0 332 333 //***************************************************************************** 334 // 335 // Register: CPU_TPIU_O_DEVID 336 // 337 //***************************************************************************** 338 // Field: [31:0] DEVID 339 // 340 // This field returns: 0xCA1 if there is an ETM present. 0xCA0 if there is no 341 // ETM present. 342 #define CPU_TPIU_DEVID_DEVID_W 32 343 #define CPU_TPIU_DEVID_DEVID_M 0xFFFFFFFF 344 #define CPU_TPIU_DEVID_DEVID_S 0 345 346 347 #endif // __CPU_TPIU__ 348