1 /****************************************************************************** 2 * Filename: hw_fcfg1_h 3 * Revised: 2015-11-17 15:22:29 +0100 (Tue, 17 Nov 2015) 4 * Revision: 45119 5 * 6 * Copyright (c) 2015, Texas Instruments Incorporated 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions are met: 11 * 12 * 1) Redistributions of source code must retain the above copyright notice, 13 * this list of conditions and the following disclaimer. 14 * 15 * 2) Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 19 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may 20 * be used to endorse or promote products derived from this software without 21 * specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 * 35 ******************************************************************************/ 36 37 #ifndef __HW_FCFG1_H__ 38 #define __HW_FCFG1_H__ 39 40 //***************************************************************************** 41 // 42 // This section defines the register offsets of 43 // FCFG1 component 44 // 45 //***************************************************************************** 46 // Misc configurations 47 #define FCFG1_O_MISC_CONF_1 0x000000A0 48 49 // Internal 50 #define FCFG1_O_MISC_CONF_2 0x000000A4 51 52 // Internal 53 #define FCFG1_O_CONFIG_RF_FRONTEND_DIV5 0x000000C4 54 55 // Internal 56 #define FCFG1_O_CONFIG_RF_FRONTEND_DIV6 0x000000C8 57 58 // Internal 59 #define FCFG1_O_CONFIG_RF_FRONTEND_DIV10 0x000000CC 60 61 // Internal 62 #define FCFG1_O_CONFIG_RF_FRONTEND_DIV12 0x000000D0 63 64 // Internal 65 #define FCFG1_O_CONFIG_RF_FRONTEND_DIV15 0x000000D4 66 67 // Internal 68 #define FCFG1_O_CONFIG_RF_FRONTEND_DIV30 0x000000D8 69 70 // Internal 71 #define FCFG1_O_CONFIG_SYNTH_DIV5 0x000000DC 72 73 // Internal 74 #define FCFG1_O_CONFIG_SYNTH_DIV6 0x000000E0 75 76 // Internal 77 #define FCFG1_O_CONFIG_SYNTH_DIV10 0x000000E4 78 79 // Internal 80 #define FCFG1_O_CONFIG_SYNTH_DIV12 0x000000E8 81 82 // Internal 83 #define FCFG1_O_CONFIG_SYNTH_DIV15 0x000000EC 84 85 // Internal 86 #define FCFG1_O_CONFIG_SYNTH_DIV30 0x000000F0 87 88 // Internal 89 #define FCFG1_O_CONFIG_MISC_ADC_DIV5 0x000000F4 90 91 // Internal 92 #define FCFG1_O_CONFIG_MISC_ADC_DIV6 0x000000F8 93 94 // Internal 95 #define FCFG1_O_CONFIG_MISC_ADC_DIV10 0x000000FC 96 97 // Internal 98 #define FCFG1_O_CONFIG_MISC_ADC_DIV12 0x00000100 99 100 // Internal 101 #define FCFG1_O_CONFIG_MISC_ADC_DIV15 0x00000104 102 103 // Internal 104 #define FCFG1_O_CONFIG_MISC_ADC_DIV30 0x00000108 105 106 // Shadow of EFUSE:DIE_ID_0 107 #define FCFG1_O_SHDW_DIE_ID_0 0x00000118 108 109 // Shadow of EFUSE:DIE_ID_1 110 #define FCFG1_O_SHDW_DIE_ID_1 0x0000011C 111 112 // Shadow of EFUSE:DIE_ID_2 113 #define FCFG1_O_SHDW_DIE_ID_2 0x00000120 114 115 // Shadow of EFUSE:DIE_ID_3 116 #define FCFG1_O_SHDW_DIE_ID_3 0x00000124 117 118 // Internal 119 #define FCFG1_O_SHDW_OSC_BIAS_LDO_TRIM 0x00000138 120 121 // Internal 122 #define FCFG1_O_SHDW_ANA_TRIM 0x0000013C 123 124 #define FCFG1_O_FLASH_NUMBER 0x00000164 125 126 #define FCFG1_O_FLASH_COORDINATE 0x0000016C 127 128 // Internal 129 #define FCFG1_O_FLASH_E_P 0x00000170 130 131 // Internal 132 #define FCFG1_O_FLASH_C_E_P_R 0x00000174 133 134 // Internal 135 #define FCFG1_O_FLASH_P_R_PV 0x00000178 136 137 // Internal 138 #define FCFG1_O_FLASH_EH_SEQ 0x0000017C 139 140 // Internal 141 #define FCFG1_O_FLASH_VHV_E 0x00000180 142 143 // Internal 144 #define FCFG1_O_FLASH_PP 0x00000184 145 146 // Internal 147 #define FCFG1_O_FLASH_PROG_EP 0x00000188 148 149 // Internal 150 #define FCFG1_O_FLASH_ERA_PW 0x0000018C 151 152 // Internal 153 #define FCFG1_O_FLASH_VHV 0x00000190 154 155 // Internal 156 #define FCFG1_O_FLASH_VHV_PV 0x00000194 157 158 // Internal 159 #define FCFG1_O_FLASH_V 0x00000198 160 161 // User Identification. 162 #define FCFG1_O_USER_ID 0x00000294 163 164 // Internal 165 #define FCFG1_O_FLASH_OTP_DATA3 0x000002B0 166 167 // Internal 168 #define FCFG1_O_ANA2_TRIM 0x000002B4 169 170 // Internal 171 #define FCFG1_O_LDO_TRIM 0x000002B8 172 173 // MAC BLE Address 0 174 #define FCFG1_O_MAC_BLE_0 0x000002E8 175 176 // MAC BLE Address 1 177 #define FCFG1_O_MAC_BLE_1 0x000002EC 178 179 // MAC IEEE 802.15.4 Address 0 180 #define FCFG1_O_MAC_15_4_0 0x000002F0 181 182 // MAC IEEE 802.15.4 Address 1 183 #define FCFG1_O_MAC_15_4_1 0x000002F4 184 185 // Internal 186 #define FCFG1_O_FLASH_OTP_DATA4 0x00000308 187 188 // Miscellaneous Trim Parameters 189 #define FCFG1_O_MISC_TRIM 0x0000030C 190 191 // Internal 192 #define FCFG1_O_RCOSC_HF_TEMPCOMP 0x00000310 193 194 // IcePick Device Identification 195 #define FCFG1_O_ICEPICK_DEVICE_ID 0x00000318 196 197 // Factory Configuration (FCFG1) Revision 198 #define FCFG1_O_FCFG1_REVISION 0x0000031C 199 200 // Misc OTP Data 201 #define FCFG1_O_MISC_OTP_DATA 0x00000320 202 203 // IO Configuration 204 #define FCFG1_O_IOCONF 0x00000344 205 206 // Internal 207 #define FCFG1_O_CONFIG_IF_ADC 0x0000034C 208 209 // Internal 210 #define FCFG1_O_CONFIG_OSC_TOP 0x00000350 211 212 // Internal 213 #define FCFG1_O_CONFIG_RF_FRONTEND 0x00000354 214 215 // Internal 216 #define FCFG1_O_CONFIG_SYNTH 0x00000358 217 218 // AUX_ADC Gain in Absolute Reference Mode 219 #define FCFG1_O_SOC_ADC_ABS_GAIN 0x0000035C 220 221 // AUX_ADC Gain in Relative Reference Mode 222 #define FCFG1_O_SOC_ADC_REL_GAIN 0x00000360 223 224 // AUX_ADC Temperature Offsets in Absolute Reference Mode 225 #define FCFG1_O_SOC_ADC_OFFSET_INT 0x00000368 226 227 // Internal 228 #define FCFG1_O_SOC_ADC_REF_TRIM_AND_OFFSET_EXT 0x0000036C 229 230 // Internal 231 #define FCFG1_O_AMPCOMP_TH1 0x00000370 232 233 // Internal 234 #define FCFG1_O_AMPCOMP_TH2 0x00000374 235 236 // Internal 237 #define FCFG1_O_AMPCOMP_CTRL1 0x00000378 238 239 // Internal 240 #define FCFG1_O_ANABYPASS_VALUE2 0x0000037C 241 242 // Internal 243 #define FCFG1_O_CONFIG_MISC_ADC 0x00000380 244 245 // Internal 246 #define FCFG1_O_VOLT_TRIM 0x00000388 247 248 // OSC Configuration 249 #define FCFG1_O_OSC_CONF 0x0000038C 250 251 // Internal 252 #define FCFG1_O_FREQ_OFFSET 0x00000390 253 254 // Internal 255 #define FCFG1_O_CAP_TRIM 0x00000394 256 257 // Internal 258 #define FCFG1_O_MISC_OTP_DATA_1 0x00000398 259 260 // Power Down Current Control 20C 261 #define FCFG1_O_PWD_CURR_20C 0x0000039C 262 263 // Power Down Current Control 35C 264 #define FCFG1_O_PWD_CURR_35C 0x000003A0 265 266 // Power Down Current Control 50C 267 #define FCFG1_O_PWD_CURR_50C 0x000003A4 268 269 // Power Down Current Control 65C 270 #define FCFG1_O_PWD_CURR_65C 0x000003A8 271 272 // Power Down Current Control 80C 273 #define FCFG1_O_PWD_CURR_80C 0x000003AC 274 275 // Power Down Current Control 95C 276 #define FCFG1_O_PWD_CURR_95C 0x000003B0 277 278 // Power Down Current Control 110C 279 #define FCFG1_O_PWD_CURR_110C 0x000003B4 280 281 // Power Down Current Control 125C 282 #define FCFG1_O_PWD_CURR_125C 0x000003B8 283 284 //***************************************************************************** 285 // 286 // Register: FCFG1_O_MISC_CONF_1 287 // 288 //***************************************************************************** 289 // Field: [7:0] DEVICE_MINOR_REV 290 // 291 // HW minor revision number (a value of 0xFF shall be treated equally to 0x00). 292 // Any test of this field by SW should be implemented as a 'greater or equal' 293 // comparison as signed integer. 294 // Value may change without warning. 295 #define FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_W 8 296 #define FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_M 0x000000FF 297 #define FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_S 0 298 299 //***************************************************************************** 300 // 301 // Register: FCFG1_O_MISC_CONF_2 302 // 303 //***************************************************************************** 304 // Field: [7:0] HPOSC_COMP_P3 305 // 306 // Internal. Only to be used through TI provided API. 307 #define FCFG1_MISC_CONF_2_HPOSC_COMP_P3_W 8 308 #define FCFG1_MISC_CONF_2_HPOSC_COMP_P3_M 0x000000FF 309 #define FCFG1_MISC_CONF_2_HPOSC_COMP_P3_S 0 310 311 //***************************************************************************** 312 // 313 // Register: FCFG1_O_CONFIG_RF_FRONTEND_DIV5 314 // 315 //***************************************************************************** 316 // Field: [31:28] IFAMP_IB 317 // 318 // Internal. Only to be used through TI provided API. 319 #define FCFG1_CONFIG_RF_FRONTEND_DIV5_IFAMP_IB_W 4 320 #define FCFG1_CONFIG_RF_FRONTEND_DIV5_IFAMP_IB_M 0xF0000000 321 #define FCFG1_CONFIG_RF_FRONTEND_DIV5_IFAMP_IB_S 28 322 323 // Field: [27:24] LNA_IB 324 // 325 // Internal. Only to be used through TI provided API. 326 #define FCFG1_CONFIG_RF_FRONTEND_DIV5_LNA_IB_W 4 327 #define FCFG1_CONFIG_RF_FRONTEND_DIV5_LNA_IB_M 0x0F000000 328 #define FCFG1_CONFIG_RF_FRONTEND_DIV5_LNA_IB_S 24 329 330 // Field: [23:19] IFAMP_TRIM 331 // 332 // Internal. Only to be used through TI provided API. 333 #define FCFG1_CONFIG_RF_FRONTEND_DIV5_IFAMP_TRIM_W 5 334 #define FCFG1_CONFIG_RF_FRONTEND_DIV5_IFAMP_TRIM_M 0x00F80000 335 #define FCFG1_CONFIG_RF_FRONTEND_DIV5_IFAMP_TRIM_S 19 336 337 // Field: [18:14] CTL_PA0_TRIM 338 // 339 // Internal. Only to be used through TI provided API. 340 #define FCFG1_CONFIG_RF_FRONTEND_DIV5_CTL_PA0_TRIM_W 5 341 #define FCFG1_CONFIG_RF_FRONTEND_DIV5_CTL_PA0_TRIM_M 0x0007C000 342 #define FCFG1_CONFIG_RF_FRONTEND_DIV5_CTL_PA0_TRIM_S 14 343 344 // Field: [6:0] RFLDO_TRIM_OUTPUT 345 // 346 // Internal. Only to be used through TI provided API. 347 #define FCFG1_CONFIG_RF_FRONTEND_DIV5_RFLDO_TRIM_OUTPUT_W 7 348 #define FCFG1_CONFIG_RF_FRONTEND_DIV5_RFLDO_TRIM_OUTPUT_M 0x0000007F 349 #define FCFG1_CONFIG_RF_FRONTEND_DIV5_RFLDO_TRIM_OUTPUT_S 0 350 351 //***************************************************************************** 352 // 353 // Register: FCFG1_O_CONFIG_RF_FRONTEND_DIV6 354 // 355 //***************************************************************************** 356 // Field: [31:28] IFAMP_IB 357 // 358 // Internal. Only to be used through TI provided API. 359 #define FCFG1_CONFIG_RF_FRONTEND_DIV6_IFAMP_IB_W 4 360 #define FCFG1_CONFIG_RF_FRONTEND_DIV6_IFAMP_IB_M 0xF0000000 361 #define FCFG1_CONFIG_RF_FRONTEND_DIV6_IFAMP_IB_S 28 362 363 // Field: [27:24] LNA_IB 364 // 365 // Internal. Only to be used through TI provided API. 366 #define FCFG1_CONFIG_RF_FRONTEND_DIV6_LNA_IB_W 4 367 #define FCFG1_CONFIG_RF_FRONTEND_DIV6_LNA_IB_M 0x0F000000 368 #define FCFG1_CONFIG_RF_FRONTEND_DIV6_LNA_IB_S 24 369 370 // Field: [23:19] IFAMP_TRIM 371 // 372 // Internal. Only to be used through TI provided API. 373 #define FCFG1_CONFIG_RF_FRONTEND_DIV6_IFAMP_TRIM_W 5 374 #define FCFG1_CONFIG_RF_FRONTEND_DIV6_IFAMP_TRIM_M 0x00F80000 375 #define FCFG1_CONFIG_RF_FRONTEND_DIV6_IFAMP_TRIM_S 19 376 377 // Field: [18:14] CTL_PA0_TRIM 378 // 379 // Internal. Only to be used through TI provided API. 380 #define FCFG1_CONFIG_RF_FRONTEND_DIV6_CTL_PA0_TRIM_W 5 381 #define FCFG1_CONFIG_RF_FRONTEND_DIV6_CTL_PA0_TRIM_M 0x0007C000 382 #define FCFG1_CONFIG_RF_FRONTEND_DIV6_CTL_PA0_TRIM_S 14 383 384 // Field: [6:0] RFLDO_TRIM_OUTPUT 385 // 386 // Internal. Only to be used through TI provided API. 387 #define FCFG1_CONFIG_RF_FRONTEND_DIV6_RFLDO_TRIM_OUTPUT_W 7 388 #define FCFG1_CONFIG_RF_FRONTEND_DIV6_RFLDO_TRIM_OUTPUT_M 0x0000007F 389 #define FCFG1_CONFIG_RF_FRONTEND_DIV6_RFLDO_TRIM_OUTPUT_S 0 390 391 //***************************************************************************** 392 // 393 // Register: FCFG1_O_CONFIG_RF_FRONTEND_DIV10 394 // 395 //***************************************************************************** 396 // Field: [31:28] IFAMP_IB 397 // 398 // Internal. Only to be used through TI provided API. 399 #define FCFG1_CONFIG_RF_FRONTEND_DIV10_IFAMP_IB_W 4 400 #define FCFG1_CONFIG_RF_FRONTEND_DIV10_IFAMP_IB_M 0xF0000000 401 #define FCFG1_CONFIG_RF_FRONTEND_DIV10_IFAMP_IB_S 28 402 403 // Field: [27:24] LNA_IB 404 // 405 // Internal. Only to be used through TI provided API. 406 #define FCFG1_CONFIG_RF_FRONTEND_DIV10_LNA_IB_W 4 407 #define FCFG1_CONFIG_RF_FRONTEND_DIV10_LNA_IB_M 0x0F000000 408 #define FCFG1_CONFIG_RF_FRONTEND_DIV10_LNA_IB_S 24 409 410 // Field: [23:19] IFAMP_TRIM 411 // 412 // Internal. Only to be used through TI provided API. 413 #define FCFG1_CONFIG_RF_FRONTEND_DIV10_IFAMP_TRIM_W 5 414 #define FCFG1_CONFIG_RF_FRONTEND_DIV10_IFAMP_TRIM_M 0x00F80000 415 #define FCFG1_CONFIG_RF_FRONTEND_DIV10_IFAMP_TRIM_S 19 416 417 // Field: [18:14] CTL_PA0_TRIM 418 // 419 // Internal. Only to be used through TI provided API. 420 #define FCFG1_CONFIG_RF_FRONTEND_DIV10_CTL_PA0_TRIM_W 5 421 #define FCFG1_CONFIG_RF_FRONTEND_DIV10_CTL_PA0_TRIM_M 0x0007C000 422 #define FCFG1_CONFIG_RF_FRONTEND_DIV10_CTL_PA0_TRIM_S 14 423 424 // Field: [6:0] RFLDO_TRIM_OUTPUT 425 // 426 // Internal. Only to be used through TI provided API. 427 #define FCFG1_CONFIG_RF_FRONTEND_DIV10_RFLDO_TRIM_OUTPUT_W 7 428 #define FCFG1_CONFIG_RF_FRONTEND_DIV10_RFLDO_TRIM_OUTPUT_M 0x0000007F 429 #define FCFG1_CONFIG_RF_FRONTEND_DIV10_RFLDO_TRIM_OUTPUT_S 0 430 431 //***************************************************************************** 432 // 433 // Register: FCFG1_O_CONFIG_RF_FRONTEND_DIV12 434 // 435 //***************************************************************************** 436 // Field: [31:28] IFAMP_IB 437 // 438 // Internal. Only to be used through TI provided API. 439 #define FCFG1_CONFIG_RF_FRONTEND_DIV12_IFAMP_IB_W 4 440 #define FCFG1_CONFIG_RF_FRONTEND_DIV12_IFAMP_IB_M 0xF0000000 441 #define FCFG1_CONFIG_RF_FRONTEND_DIV12_IFAMP_IB_S 28 442 443 // Field: [27:24] LNA_IB 444 // 445 // Internal. Only to be used through TI provided API. 446 #define FCFG1_CONFIG_RF_FRONTEND_DIV12_LNA_IB_W 4 447 #define FCFG1_CONFIG_RF_FRONTEND_DIV12_LNA_IB_M 0x0F000000 448 #define FCFG1_CONFIG_RF_FRONTEND_DIV12_LNA_IB_S 24 449 450 // Field: [23:19] IFAMP_TRIM 451 // 452 // Internal. Only to be used through TI provided API. 453 #define FCFG1_CONFIG_RF_FRONTEND_DIV12_IFAMP_TRIM_W 5 454 #define FCFG1_CONFIG_RF_FRONTEND_DIV12_IFAMP_TRIM_M 0x00F80000 455 #define FCFG1_CONFIG_RF_FRONTEND_DIV12_IFAMP_TRIM_S 19 456 457 // Field: [18:14] CTL_PA0_TRIM 458 // 459 // Internal. Only to be used through TI provided API. 460 #define FCFG1_CONFIG_RF_FRONTEND_DIV12_CTL_PA0_TRIM_W 5 461 #define FCFG1_CONFIG_RF_FRONTEND_DIV12_CTL_PA0_TRIM_M 0x0007C000 462 #define FCFG1_CONFIG_RF_FRONTEND_DIV12_CTL_PA0_TRIM_S 14 463 464 // Field: [6:0] RFLDO_TRIM_OUTPUT 465 // 466 // Internal. Only to be used through TI provided API. 467 #define FCFG1_CONFIG_RF_FRONTEND_DIV12_RFLDO_TRIM_OUTPUT_W 7 468 #define FCFG1_CONFIG_RF_FRONTEND_DIV12_RFLDO_TRIM_OUTPUT_M 0x0000007F 469 #define FCFG1_CONFIG_RF_FRONTEND_DIV12_RFLDO_TRIM_OUTPUT_S 0 470 471 //***************************************************************************** 472 // 473 // Register: FCFG1_O_CONFIG_RF_FRONTEND_DIV15 474 // 475 //***************************************************************************** 476 // Field: [31:28] IFAMP_IB 477 // 478 // Internal. Only to be used through TI provided API. 479 #define FCFG1_CONFIG_RF_FRONTEND_DIV15_IFAMP_IB_W 4 480 #define FCFG1_CONFIG_RF_FRONTEND_DIV15_IFAMP_IB_M 0xF0000000 481 #define FCFG1_CONFIG_RF_FRONTEND_DIV15_IFAMP_IB_S 28 482 483 // Field: [27:24] LNA_IB 484 // 485 // Internal. Only to be used through TI provided API. 486 #define FCFG1_CONFIG_RF_FRONTEND_DIV15_LNA_IB_W 4 487 #define FCFG1_CONFIG_RF_FRONTEND_DIV15_LNA_IB_M 0x0F000000 488 #define FCFG1_CONFIG_RF_FRONTEND_DIV15_LNA_IB_S 24 489 490 // Field: [23:19] IFAMP_TRIM 491 // 492 // Internal. Only to be used through TI provided API. 493 #define FCFG1_CONFIG_RF_FRONTEND_DIV15_IFAMP_TRIM_W 5 494 #define FCFG1_CONFIG_RF_FRONTEND_DIV15_IFAMP_TRIM_M 0x00F80000 495 #define FCFG1_CONFIG_RF_FRONTEND_DIV15_IFAMP_TRIM_S 19 496 497 // Field: [18:14] CTL_PA0_TRIM 498 // 499 // Internal. Only to be used through TI provided API. 500 #define FCFG1_CONFIG_RF_FRONTEND_DIV15_CTL_PA0_TRIM_W 5 501 #define FCFG1_CONFIG_RF_FRONTEND_DIV15_CTL_PA0_TRIM_M 0x0007C000 502 #define FCFG1_CONFIG_RF_FRONTEND_DIV15_CTL_PA0_TRIM_S 14 503 504 // Field: [6:0] RFLDO_TRIM_OUTPUT 505 // 506 // Internal. Only to be used through TI provided API. 507 #define FCFG1_CONFIG_RF_FRONTEND_DIV15_RFLDO_TRIM_OUTPUT_W 7 508 #define FCFG1_CONFIG_RF_FRONTEND_DIV15_RFLDO_TRIM_OUTPUT_M 0x0000007F 509 #define FCFG1_CONFIG_RF_FRONTEND_DIV15_RFLDO_TRIM_OUTPUT_S 0 510 511 //***************************************************************************** 512 // 513 // Register: FCFG1_O_CONFIG_RF_FRONTEND_DIV30 514 // 515 //***************************************************************************** 516 // Field: [31:28] IFAMP_IB 517 // 518 // Internal. Only to be used through TI provided API. 519 #define FCFG1_CONFIG_RF_FRONTEND_DIV30_IFAMP_IB_W 4 520 #define FCFG1_CONFIG_RF_FRONTEND_DIV30_IFAMP_IB_M 0xF0000000 521 #define FCFG1_CONFIG_RF_FRONTEND_DIV30_IFAMP_IB_S 28 522 523 // Field: [27:24] LNA_IB 524 // 525 // Internal. Only to be used through TI provided API. 526 #define FCFG1_CONFIG_RF_FRONTEND_DIV30_LNA_IB_W 4 527 #define FCFG1_CONFIG_RF_FRONTEND_DIV30_LNA_IB_M 0x0F000000 528 #define FCFG1_CONFIG_RF_FRONTEND_DIV30_LNA_IB_S 24 529 530 // Field: [23:19] IFAMP_TRIM 531 // 532 // Internal. Only to be used through TI provided API. 533 #define FCFG1_CONFIG_RF_FRONTEND_DIV30_IFAMP_TRIM_W 5 534 #define FCFG1_CONFIG_RF_FRONTEND_DIV30_IFAMP_TRIM_M 0x00F80000 535 #define FCFG1_CONFIG_RF_FRONTEND_DIV30_IFAMP_TRIM_S 19 536 537 // Field: [18:14] CTL_PA0_TRIM 538 // 539 // Internal. Only to be used through TI provided API. 540 #define FCFG1_CONFIG_RF_FRONTEND_DIV30_CTL_PA0_TRIM_W 5 541 #define FCFG1_CONFIG_RF_FRONTEND_DIV30_CTL_PA0_TRIM_M 0x0007C000 542 #define FCFG1_CONFIG_RF_FRONTEND_DIV30_CTL_PA0_TRIM_S 14 543 544 // Field: [6:0] RFLDO_TRIM_OUTPUT 545 // 546 // Internal. Only to be used through TI provided API. 547 #define FCFG1_CONFIG_RF_FRONTEND_DIV30_RFLDO_TRIM_OUTPUT_W 7 548 #define FCFG1_CONFIG_RF_FRONTEND_DIV30_RFLDO_TRIM_OUTPUT_M 0x0000007F 549 #define FCFG1_CONFIG_RF_FRONTEND_DIV30_RFLDO_TRIM_OUTPUT_S 0 550 551 //***************************************************************************** 552 // 553 // Register: FCFG1_O_CONFIG_SYNTH_DIV5 554 // 555 //***************************************************************************** 556 // Field: [27:12] RFC_MDM_DEMIQMC0 557 // 558 // Trim value for RF Core. 559 // Value is read by RF Core ROM FW during RF Core initialization. 560 #define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_W 16 561 #define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_M 0x0FFFF000 562 #define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_S 12 563 564 // Field: [11:6] LDOVCO_TRIM_OUTPUT 565 // 566 // Internal. Only to be used through TI provided API. 567 #define FCFG1_CONFIG_SYNTH_DIV5_LDOVCO_TRIM_OUTPUT_W 6 568 #define FCFG1_CONFIG_SYNTH_DIV5_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 569 #define FCFG1_CONFIG_SYNTH_DIV5_LDOVCO_TRIM_OUTPUT_S 6 570 571 // Field: [5:0] SLDO_TRIM_OUTPUT 572 // 573 // Internal. Only to be used through TI provided API. 574 #define FCFG1_CONFIG_SYNTH_DIV5_SLDO_TRIM_OUTPUT_W 6 575 #define FCFG1_CONFIG_SYNTH_DIV5_SLDO_TRIM_OUTPUT_M 0x0000003F 576 #define FCFG1_CONFIG_SYNTH_DIV5_SLDO_TRIM_OUTPUT_S 0 577 578 //***************************************************************************** 579 // 580 // Register: FCFG1_O_CONFIG_SYNTH_DIV6 581 // 582 //***************************************************************************** 583 // Field: [27:12] RFC_MDM_DEMIQMC0 584 // 585 // Trim value for RF Core. 586 // Value is read by RF Core ROM FW during RF Core initialization. 587 #define FCFG1_CONFIG_SYNTH_DIV6_RFC_MDM_DEMIQMC0_W 16 588 #define FCFG1_CONFIG_SYNTH_DIV6_RFC_MDM_DEMIQMC0_M 0x0FFFF000 589 #define FCFG1_CONFIG_SYNTH_DIV6_RFC_MDM_DEMIQMC0_S 12 590 591 // Field: [11:6] LDOVCO_TRIM_OUTPUT 592 // 593 // Internal. Only to be used through TI provided API. 594 #define FCFG1_CONFIG_SYNTH_DIV6_LDOVCO_TRIM_OUTPUT_W 6 595 #define FCFG1_CONFIG_SYNTH_DIV6_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 596 #define FCFG1_CONFIG_SYNTH_DIV6_LDOVCO_TRIM_OUTPUT_S 6 597 598 // Field: [5:0] SLDO_TRIM_OUTPUT 599 // 600 // Internal. Only to be used through TI provided API. 601 #define FCFG1_CONFIG_SYNTH_DIV6_SLDO_TRIM_OUTPUT_W 6 602 #define FCFG1_CONFIG_SYNTH_DIV6_SLDO_TRIM_OUTPUT_M 0x0000003F 603 #define FCFG1_CONFIG_SYNTH_DIV6_SLDO_TRIM_OUTPUT_S 0 604 605 //***************************************************************************** 606 // 607 // Register: FCFG1_O_CONFIG_SYNTH_DIV10 608 // 609 //***************************************************************************** 610 // Field: [27:12] RFC_MDM_DEMIQMC0 611 // 612 // Trim value for RF Core. 613 // Value is read by RF Core ROM FW during RF Core initialization. 614 #define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_W 16 615 #define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_M 0x0FFFF000 616 #define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_S 12 617 618 // Field: [11:6] LDOVCO_TRIM_OUTPUT 619 // 620 // Internal. Only to be used through TI provided API. 621 #define FCFG1_CONFIG_SYNTH_DIV10_LDOVCO_TRIM_OUTPUT_W 6 622 #define FCFG1_CONFIG_SYNTH_DIV10_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 623 #define FCFG1_CONFIG_SYNTH_DIV10_LDOVCO_TRIM_OUTPUT_S 6 624 625 // Field: [5:0] SLDO_TRIM_OUTPUT 626 // 627 // Internal. Only to be used through TI provided API. 628 #define FCFG1_CONFIG_SYNTH_DIV10_SLDO_TRIM_OUTPUT_W 6 629 #define FCFG1_CONFIG_SYNTH_DIV10_SLDO_TRIM_OUTPUT_M 0x0000003F 630 #define FCFG1_CONFIG_SYNTH_DIV10_SLDO_TRIM_OUTPUT_S 0 631 632 //***************************************************************************** 633 // 634 // Register: FCFG1_O_CONFIG_SYNTH_DIV12 635 // 636 //***************************************************************************** 637 // Field: [27:12] RFC_MDM_DEMIQMC0 638 // 639 // Trim value for RF Core. 640 // Value is read by RF Core ROM FW during RF Core initialization. 641 #define FCFG1_CONFIG_SYNTH_DIV12_RFC_MDM_DEMIQMC0_W 16 642 #define FCFG1_CONFIG_SYNTH_DIV12_RFC_MDM_DEMIQMC0_M 0x0FFFF000 643 #define FCFG1_CONFIG_SYNTH_DIV12_RFC_MDM_DEMIQMC0_S 12 644 645 // Field: [11:6] LDOVCO_TRIM_OUTPUT 646 // 647 // Internal. Only to be used through TI provided API. 648 #define FCFG1_CONFIG_SYNTH_DIV12_LDOVCO_TRIM_OUTPUT_W 6 649 #define FCFG1_CONFIG_SYNTH_DIV12_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 650 #define FCFG1_CONFIG_SYNTH_DIV12_LDOVCO_TRIM_OUTPUT_S 6 651 652 // Field: [5:0] SLDO_TRIM_OUTPUT 653 // 654 // Internal. Only to be used through TI provided API. 655 #define FCFG1_CONFIG_SYNTH_DIV12_SLDO_TRIM_OUTPUT_W 6 656 #define FCFG1_CONFIG_SYNTH_DIV12_SLDO_TRIM_OUTPUT_M 0x0000003F 657 #define FCFG1_CONFIG_SYNTH_DIV12_SLDO_TRIM_OUTPUT_S 0 658 659 //***************************************************************************** 660 // 661 // Register: FCFG1_O_CONFIG_SYNTH_DIV15 662 // 663 //***************************************************************************** 664 // Field: [27:12] RFC_MDM_DEMIQMC0 665 // 666 // Trim value for RF Core. 667 // Value is read by RF Core ROM FW during RF Core initialization. 668 #define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_W 16 669 #define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_M 0x0FFFF000 670 #define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_S 12 671 672 // Field: [11:6] LDOVCO_TRIM_OUTPUT 673 // 674 // Internal. Only to be used through TI provided API. 675 #define FCFG1_CONFIG_SYNTH_DIV15_LDOVCO_TRIM_OUTPUT_W 6 676 #define FCFG1_CONFIG_SYNTH_DIV15_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 677 #define FCFG1_CONFIG_SYNTH_DIV15_LDOVCO_TRIM_OUTPUT_S 6 678 679 // Field: [5:0] SLDO_TRIM_OUTPUT 680 // 681 // Internal. Only to be used through TI provided API. 682 #define FCFG1_CONFIG_SYNTH_DIV15_SLDO_TRIM_OUTPUT_W 6 683 #define FCFG1_CONFIG_SYNTH_DIV15_SLDO_TRIM_OUTPUT_M 0x0000003F 684 #define FCFG1_CONFIG_SYNTH_DIV15_SLDO_TRIM_OUTPUT_S 0 685 686 //***************************************************************************** 687 // 688 // Register: FCFG1_O_CONFIG_SYNTH_DIV30 689 // 690 //***************************************************************************** 691 // Field: [27:12] RFC_MDM_DEMIQMC0 692 // 693 // Trim value for RF Core. 694 // Value is read by RF Core ROM FW during RF Core initialization. 695 #define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_W 16 696 #define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_M 0x0FFFF000 697 #define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_S 12 698 699 // Field: [11:6] LDOVCO_TRIM_OUTPUT 700 // 701 // Internal. Only to be used through TI provided API. 702 #define FCFG1_CONFIG_SYNTH_DIV30_LDOVCO_TRIM_OUTPUT_W 6 703 #define FCFG1_CONFIG_SYNTH_DIV30_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 704 #define FCFG1_CONFIG_SYNTH_DIV30_LDOVCO_TRIM_OUTPUT_S 6 705 706 // Field: [5:0] SLDO_TRIM_OUTPUT 707 // 708 // Internal. Only to be used through TI provided API. 709 #define FCFG1_CONFIG_SYNTH_DIV30_SLDO_TRIM_OUTPUT_W 6 710 #define FCFG1_CONFIG_SYNTH_DIV30_SLDO_TRIM_OUTPUT_M 0x0000003F 711 #define FCFG1_CONFIG_SYNTH_DIV30_SLDO_TRIM_OUTPUT_S 0 712 713 //***************************************************************************** 714 // 715 // Register: FCFG1_O_CONFIG_MISC_ADC_DIV5 716 // 717 //***************************************************************************** 718 // Field: [16:9] RSSI_OFFSET 719 // 720 // Internal. Only to be used through TI provided API. 721 #define FCFG1_CONFIG_MISC_ADC_DIV5_RSSI_OFFSET_W 8 722 #define FCFG1_CONFIG_MISC_ADC_DIV5_RSSI_OFFSET_M 0x0001FE00 723 #define FCFG1_CONFIG_MISC_ADC_DIV5_RSSI_OFFSET_S 9 724 725 // Field: [8:6] QUANTCTLTHRES 726 // 727 // Internal. Only to be used through TI provided API. 728 #define FCFG1_CONFIG_MISC_ADC_DIV5_QUANTCTLTHRES_W 3 729 #define FCFG1_CONFIG_MISC_ADC_DIV5_QUANTCTLTHRES_M 0x000001C0 730 #define FCFG1_CONFIG_MISC_ADC_DIV5_QUANTCTLTHRES_S 6 731 732 // Field: [5:0] DACTRIM 733 // 734 // Internal. Only to be used through TI provided API. 735 #define FCFG1_CONFIG_MISC_ADC_DIV5_DACTRIM_W 6 736 #define FCFG1_CONFIG_MISC_ADC_DIV5_DACTRIM_M 0x0000003F 737 #define FCFG1_CONFIG_MISC_ADC_DIV5_DACTRIM_S 0 738 739 //***************************************************************************** 740 // 741 // Register: FCFG1_O_CONFIG_MISC_ADC_DIV6 742 // 743 //***************************************************************************** 744 // Field: [16:9] RSSI_OFFSET 745 // 746 // Internal. Only to be used through TI provided API. 747 #define FCFG1_CONFIG_MISC_ADC_DIV6_RSSI_OFFSET_W 8 748 #define FCFG1_CONFIG_MISC_ADC_DIV6_RSSI_OFFSET_M 0x0001FE00 749 #define FCFG1_CONFIG_MISC_ADC_DIV6_RSSI_OFFSET_S 9 750 751 // Field: [8:6] QUANTCTLTHRES 752 // 753 // Internal. Only to be used through TI provided API. 754 #define FCFG1_CONFIG_MISC_ADC_DIV6_QUANTCTLTHRES_W 3 755 #define FCFG1_CONFIG_MISC_ADC_DIV6_QUANTCTLTHRES_M 0x000001C0 756 #define FCFG1_CONFIG_MISC_ADC_DIV6_QUANTCTLTHRES_S 6 757 758 // Field: [5:0] DACTRIM 759 // 760 // Internal. Only to be used through TI provided API. 761 #define FCFG1_CONFIG_MISC_ADC_DIV6_DACTRIM_W 6 762 #define FCFG1_CONFIG_MISC_ADC_DIV6_DACTRIM_M 0x0000003F 763 #define FCFG1_CONFIG_MISC_ADC_DIV6_DACTRIM_S 0 764 765 //***************************************************************************** 766 // 767 // Register: FCFG1_O_CONFIG_MISC_ADC_DIV10 768 // 769 //***************************************************************************** 770 // Field: [16:9] RSSI_OFFSET 771 // 772 // Internal. Only to be used through TI provided API. 773 #define FCFG1_CONFIG_MISC_ADC_DIV10_RSSI_OFFSET_W 8 774 #define FCFG1_CONFIG_MISC_ADC_DIV10_RSSI_OFFSET_M 0x0001FE00 775 #define FCFG1_CONFIG_MISC_ADC_DIV10_RSSI_OFFSET_S 9 776 777 // Field: [8:6] QUANTCTLTHRES 778 // 779 // Internal. Only to be used through TI provided API. 780 #define FCFG1_CONFIG_MISC_ADC_DIV10_QUANTCTLTHRES_W 3 781 #define FCFG1_CONFIG_MISC_ADC_DIV10_QUANTCTLTHRES_M 0x000001C0 782 #define FCFG1_CONFIG_MISC_ADC_DIV10_QUANTCTLTHRES_S 6 783 784 // Field: [5:0] DACTRIM 785 // 786 // Internal. Only to be used through TI provided API. 787 #define FCFG1_CONFIG_MISC_ADC_DIV10_DACTRIM_W 6 788 #define FCFG1_CONFIG_MISC_ADC_DIV10_DACTRIM_M 0x0000003F 789 #define FCFG1_CONFIG_MISC_ADC_DIV10_DACTRIM_S 0 790 791 //***************************************************************************** 792 // 793 // Register: FCFG1_O_CONFIG_MISC_ADC_DIV12 794 // 795 //***************************************************************************** 796 // Field: [16:9] RSSI_OFFSET 797 // 798 // Internal. Only to be used through TI provided API. 799 #define FCFG1_CONFIG_MISC_ADC_DIV12_RSSI_OFFSET_W 8 800 #define FCFG1_CONFIG_MISC_ADC_DIV12_RSSI_OFFSET_M 0x0001FE00 801 #define FCFG1_CONFIG_MISC_ADC_DIV12_RSSI_OFFSET_S 9 802 803 // Field: [8:6] QUANTCTLTHRES 804 // 805 // Internal. Only to be used through TI provided API. 806 #define FCFG1_CONFIG_MISC_ADC_DIV12_QUANTCTLTHRES_W 3 807 #define FCFG1_CONFIG_MISC_ADC_DIV12_QUANTCTLTHRES_M 0x000001C0 808 #define FCFG1_CONFIG_MISC_ADC_DIV12_QUANTCTLTHRES_S 6 809 810 // Field: [5:0] DACTRIM 811 // 812 // Internal. Only to be used through TI provided API. 813 #define FCFG1_CONFIG_MISC_ADC_DIV12_DACTRIM_W 6 814 #define FCFG1_CONFIG_MISC_ADC_DIV12_DACTRIM_M 0x0000003F 815 #define FCFG1_CONFIG_MISC_ADC_DIV12_DACTRIM_S 0 816 817 //***************************************************************************** 818 // 819 // Register: FCFG1_O_CONFIG_MISC_ADC_DIV15 820 // 821 //***************************************************************************** 822 // Field: [16:9] RSSI_OFFSET 823 // 824 // Internal. Only to be used through TI provided API. 825 #define FCFG1_CONFIG_MISC_ADC_DIV15_RSSI_OFFSET_W 8 826 #define FCFG1_CONFIG_MISC_ADC_DIV15_RSSI_OFFSET_M 0x0001FE00 827 #define FCFG1_CONFIG_MISC_ADC_DIV15_RSSI_OFFSET_S 9 828 829 // Field: [8:6] QUANTCTLTHRES 830 // 831 // Internal. Only to be used through TI provided API. 832 #define FCFG1_CONFIG_MISC_ADC_DIV15_QUANTCTLTHRES_W 3 833 #define FCFG1_CONFIG_MISC_ADC_DIV15_QUANTCTLTHRES_M 0x000001C0 834 #define FCFG1_CONFIG_MISC_ADC_DIV15_QUANTCTLTHRES_S 6 835 836 // Field: [5:0] DACTRIM 837 // 838 // Internal. Only to be used through TI provided API. 839 #define FCFG1_CONFIG_MISC_ADC_DIV15_DACTRIM_W 6 840 #define FCFG1_CONFIG_MISC_ADC_DIV15_DACTRIM_M 0x0000003F 841 #define FCFG1_CONFIG_MISC_ADC_DIV15_DACTRIM_S 0 842 843 //***************************************************************************** 844 // 845 // Register: FCFG1_O_CONFIG_MISC_ADC_DIV30 846 // 847 //***************************************************************************** 848 // Field: [16:9] RSSI_OFFSET 849 // 850 // Internal. Only to be used through TI provided API. 851 #define FCFG1_CONFIG_MISC_ADC_DIV30_RSSI_OFFSET_W 8 852 #define FCFG1_CONFIG_MISC_ADC_DIV30_RSSI_OFFSET_M 0x0001FE00 853 #define FCFG1_CONFIG_MISC_ADC_DIV30_RSSI_OFFSET_S 9 854 855 // Field: [8:6] QUANTCTLTHRES 856 // 857 // Internal. Only to be used through TI provided API. 858 #define FCFG1_CONFIG_MISC_ADC_DIV30_QUANTCTLTHRES_W 3 859 #define FCFG1_CONFIG_MISC_ADC_DIV30_QUANTCTLTHRES_M 0x000001C0 860 #define FCFG1_CONFIG_MISC_ADC_DIV30_QUANTCTLTHRES_S 6 861 862 // Field: [5:0] DACTRIM 863 // 864 // Internal. Only to be used through TI provided API. 865 #define FCFG1_CONFIG_MISC_ADC_DIV30_DACTRIM_W 6 866 #define FCFG1_CONFIG_MISC_ADC_DIV30_DACTRIM_M 0x0000003F 867 #define FCFG1_CONFIG_MISC_ADC_DIV30_DACTRIM_S 0 868 869 //***************************************************************************** 870 // 871 // Register: FCFG1_O_SHDW_DIE_ID_0 872 // 873 //***************************************************************************** 874 // Field: [31:0] ID_31_0 875 // 876 // Shadow of the DIE_ID_0 register in eFuse row number 3 877 #define FCFG1_SHDW_DIE_ID_0_ID_31_0_W 32 878 #define FCFG1_SHDW_DIE_ID_0_ID_31_0_M 0xFFFFFFFF 879 #define FCFG1_SHDW_DIE_ID_0_ID_31_0_S 0 880 881 //***************************************************************************** 882 // 883 // Register: FCFG1_O_SHDW_DIE_ID_1 884 // 885 //***************************************************************************** 886 // Field: [31:0] ID_63_32 887 // 888 // Shadow of the DIE_ID_1 register in eFuse row number 4 889 #define FCFG1_SHDW_DIE_ID_1_ID_63_32_W 32 890 #define FCFG1_SHDW_DIE_ID_1_ID_63_32_M 0xFFFFFFFF 891 #define FCFG1_SHDW_DIE_ID_1_ID_63_32_S 0 892 893 //***************************************************************************** 894 // 895 // Register: FCFG1_O_SHDW_DIE_ID_2 896 // 897 //***************************************************************************** 898 // Field: [31:0] ID_95_64 899 // 900 // Shadow of the DIE_ID_2 register in eFuse row number 5 901 #define FCFG1_SHDW_DIE_ID_2_ID_95_64_W 32 902 #define FCFG1_SHDW_DIE_ID_2_ID_95_64_M 0xFFFFFFFF 903 #define FCFG1_SHDW_DIE_ID_2_ID_95_64_S 0 904 905 //***************************************************************************** 906 // 907 // Register: FCFG1_O_SHDW_DIE_ID_3 908 // 909 //***************************************************************************** 910 // Field: [31:0] ID_127_96 911 // 912 // Shadow of the DIE_ID_3 register in eFuse row number 6 913 #define FCFG1_SHDW_DIE_ID_3_ID_127_96_W 32 914 #define FCFG1_SHDW_DIE_ID_3_ID_127_96_M 0xFFFFFFFF 915 #define FCFG1_SHDW_DIE_ID_3_ID_127_96_S 0 916 917 //***************************************************************************** 918 // 919 // Register: FCFG1_O_SHDW_OSC_BIAS_LDO_TRIM 920 // 921 //***************************************************************************** 922 // Field: [28:27] SET_RCOSC_HF_COARSE_RESISTOR 923 // 924 // Internal. Only to be used through TI provided API. 925 #define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_SET_RCOSC_HF_COARSE_RESISTOR_W \ 926 2 927 #define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_SET_RCOSC_HF_COARSE_RESISTOR_M \ 928 0x18000000 929 #define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_SET_RCOSC_HF_COARSE_RESISTOR_S \ 930 27 931 932 // Field: [26:23] TRIMMAG 933 // 934 // Internal. Only to be used through TI provided API. 935 #define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMMAG_W 4 936 #define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMMAG_M 0x07800000 937 #define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMMAG_S 23 938 939 // Field: [22:18] TRIMIREF 940 // 941 // Internal. Only to be used through TI provided API. 942 #define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMIREF_W 5 943 #define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMIREF_M 0x007C0000 944 #define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMIREF_S 18 945 946 // Field: [17:16] ITRIM_DIG_LDO 947 // 948 // Internal. Only to be used through TI provided API. 949 #define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_ITRIM_DIG_LDO_W 2 950 #define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_ITRIM_DIG_LDO_M 0x00030000 951 #define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_ITRIM_DIG_LDO_S 16 952 953 // Field: [15:12] VTRIM_DIG 954 // 955 // Internal. Only to be used through TI provided API. 956 #define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_DIG_W 4 957 #define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_DIG_M 0x0000F000 958 #define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_DIG_S 12 959 960 // Field: [11:8] VTRIM_COARSE 961 // 962 // Internal. Only to be used through TI provided API. 963 #define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_COARSE_W 4 964 #define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_COARSE_M 0x00000F00 965 #define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_COARSE_S 8 966 967 // Field: [7:0] RCOSCHF_CTRIM 968 // 969 // Internal. Only to be used through TI provided API. 970 #define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_RCOSCHF_CTRIM_W 8 971 #define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_RCOSCHF_CTRIM_M 0x000000FF 972 #define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_RCOSCHF_CTRIM_S 0 973 974 //***************************************************************************** 975 // 976 // Register: FCFG1_O_SHDW_ANA_TRIM 977 // 978 //***************************************************************************** 979 // Field: [26:25] BOD_BANDGAP_TRIM_CNF 980 // 981 // Internal. Only to be used through TI provided API. 982 #define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_W 2 983 #define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_M 0x06000000 984 #define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_S 25 985 986 // Field: [24] VDDR_ENABLE_PG1 987 // 988 // Internal. Only to be used through TI provided API. 989 #define FCFG1_SHDW_ANA_TRIM_VDDR_ENABLE_PG1 0x01000000 990 #define FCFG1_SHDW_ANA_TRIM_VDDR_ENABLE_PG1_BITN 24 991 #define FCFG1_SHDW_ANA_TRIM_VDDR_ENABLE_PG1_M 0x01000000 992 #define FCFG1_SHDW_ANA_TRIM_VDDR_ENABLE_PG1_S 24 993 994 // Field: [23] VDDR_OK_HYS 995 // 996 // Internal. Only to be used through TI provided API. 997 #define FCFG1_SHDW_ANA_TRIM_VDDR_OK_HYS 0x00800000 998 #define FCFG1_SHDW_ANA_TRIM_VDDR_OK_HYS_BITN 23 999 #define FCFG1_SHDW_ANA_TRIM_VDDR_OK_HYS_M 0x00800000 1000 #define FCFG1_SHDW_ANA_TRIM_VDDR_OK_HYS_S 23 1001 1002 // Field: [22:21] IPTAT_TRIM 1003 // 1004 // Internal. Only to be used through TI provided API. 1005 #define FCFG1_SHDW_ANA_TRIM_IPTAT_TRIM_W 2 1006 #define FCFG1_SHDW_ANA_TRIM_IPTAT_TRIM_M 0x00600000 1007 #define FCFG1_SHDW_ANA_TRIM_IPTAT_TRIM_S 21 1008 1009 // Field: [20:16] VDDR_TRIM 1010 // 1011 // Internal. Only to be used through TI provided API. 1012 #define FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_W 5 1013 #define FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_M 0x001F0000 1014 #define FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_S 16 1015 1016 // Field: [15:11] TRIMBOD_INTMODE 1017 // 1018 // Internal. Only to be used through TI provided API. 1019 #define FCFG1_SHDW_ANA_TRIM_TRIMBOD_INTMODE_W 5 1020 #define FCFG1_SHDW_ANA_TRIM_TRIMBOD_INTMODE_M 0x0000F800 1021 #define FCFG1_SHDW_ANA_TRIM_TRIMBOD_INTMODE_S 11 1022 1023 // Field: [10:6] TRIMBOD_EXTMODE 1024 // 1025 // Internal. Only to be used through TI provided API. 1026 #define FCFG1_SHDW_ANA_TRIM_TRIMBOD_EXTMODE_W 5 1027 #define FCFG1_SHDW_ANA_TRIM_TRIMBOD_EXTMODE_M 0x000007C0 1028 #define FCFG1_SHDW_ANA_TRIM_TRIMBOD_EXTMODE_S 6 1029 1030 // Field: [5:0] TRIMTEMP 1031 // 1032 // Internal. Only to be used through TI provided API. 1033 #define FCFG1_SHDW_ANA_TRIM_TRIMTEMP_W 6 1034 #define FCFG1_SHDW_ANA_TRIM_TRIMTEMP_M 0x0000003F 1035 #define FCFG1_SHDW_ANA_TRIM_TRIMTEMP_S 0 1036 1037 //***************************************************************************** 1038 // 1039 // Register: FCFG1_O_FLASH_NUMBER 1040 // 1041 //***************************************************************************** 1042 // Field: [31:0] LOT_NUMBER 1043 // 1044 // Number of the manufacturing lot that produced this unit. 1045 #define FCFG1_FLASH_NUMBER_LOT_NUMBER_W 32 1046 #define FCFG1_FLASH_NUMBER_LOT_NUMBER_M 0xFFFFFFFF 1047 #define FCFG1_FLASH_NUMBER_LOT_NUMBER_S 0 1048 1049 //***************************************************************************** 1050 // 1051 // Register: FCFG1_O_FLASH_COORDINATE 1052 // 1053 //***************************************************************************** 1054 // Field: [31:16] XCOORDINATE 1055 // 1056 // X coordinate of this unit on the wafer. 1057 #define FCFG1_FLASH_COORDINATE_XCOORDINATE_W 16 1058 #define FCFG1_FLASH_COORDINATE_XCOORDINATE_M 0xFFFF0000 1059 #define FCFG1_FLASH_COORDINATE_XCOORDINATE_S 16 1060 1061 // Field: [15:0] YCOORDINATE 1062 // 1063 // Y coordinate of this unit on the wafer. 1064 #define FCFG1_FLASH_COORDINATE_YCOORDINATE_W 16 1065 #define FCFG1_FLASH_COORDINATE_YCOORDINATE_M 0x0000FFFF 1066 #define FCFG1_FLASH_COORDINATE_YCOORDINATE_S 0 1067 1068 //***************************************************************************** 1069 // 1070 // Register: FCFG1_O_FLASH_E_P 1071 // 1072 //***************************************************************************** 1073 // Field: [31:24] PSU 1074 // 1075 // Internal. Only to be used through TI provided API. 1076 #define FCFG1_FLASH_E_P_PSU_W 8 1077 #define FCFG1_FLASH_E_P_PSU_M 0xFF000000 1078 #define FCFG1_FLASH_E_P_PSU_S 24 1079 1080 // Field: [23:16] ESU 1081 // 1082 // Internal. Only to be used through TI provided API. 1083 #define FCFG1_FLASH_E_P_ESU_W 8 1084 #define FCFG1_FLASH_E_P_ESU_M 0x00FF0000 1085 #define FCFG1_FLASH_E_P_ESU_S 16 1086 1087 // Field: [15:8] PVSU 1088 // 1089 // Internal. Only to be used through TI provided API. 1090 #define FCFG1_FLASH_E_P_PVSU_W 8 1091 #define FCFG1_FLASH_E_P_PVSU_M 0x0000FF00 1092 #define FCFG1_FLASH_E_P_PVSU_S 8 1093 1094 // Field: [7:0] EVSU 1095 // 1096 // Internal. Only to be used through TI provided API. 1097 #define FCFG1_FLASH_E_P_EVSU_W 8 1098 #define FCFG1_FLASH_E_P_EVSU_M 0x000000FF 1099 #define FCFG1_FLASH_E_P_EVSU_S 0 1100 1101 //***************************************************************************** 1102 // 1103 // Register: FCFG1_O_FLASH_C_E_P_R 1104 // 1105 //***************************************************************************** 1106 // Field: [31:24] RVSU 1107 // 1108 // Internal. Only to be used through TI provided API. 1109 #define FCFG1_FLASH_C_E_P_R_RVSU_W 8 1110 #define FCFG1_FLASH_C_E_P_R_RVSU_M 0xFF000000 1111 #define FCFG1_FLASH_C_E_P_R_RVSU_S 24 1112 1113 // Field: [23:16] PV_ACCESS 1114 // 1115 // Internal. Only to be used through TI provided API. 1116 #define FCFG1_FLASH_C_E_P_R_PV_ACCESS_W 8 1117 #define FCFG1_FLASH_C_E_P_R_PV_ACCESS_M 0x00FF0000 1118 #define FCFG1_FLASH_C_E_P_R_PV_ACCESS_S 16 1119 1120 // Field: [15:12] A_EXEZ_SETUP 1121 // 1122 // Internal. Only to be used through TI provided API. 1123 #define FCFG1_FLASH_C_E_P_R_A_EXEZ_SETUP_W 4 1124 #define FCFG1_FLASH_C_E_P_R_A_EXEZ_SETUP_M 0x0000F000 1125 #define FCFG1_FLASH_C_E_P_R_A_EXEZ_SETUP_S 12 1126 1127 // Field: [11:0] CVSU 1128 // 1129 // Internal. Only to be used through TI provided API. 1130 #define FCFG1_FLASH_C_E_P_R_CVSU_W 12 1131 #define FCFG1_FLASH_C_E_P_R_CVSU_M 0x00000FFF 1132 #define FCFG1_FLASH_C_E_P_R_CVSU_S 0 1133 1134 //***************************************************************************** 1135 // 1136 // Register: FCFG1_O_FLASH_P_R_PV 1137 // 1138 //***************************************************************************** 1139 // Field: [31:24] PH 1140 // 1141 // Internal. Only to be used through TI provided API. 1142 #define FCFG1_FLASH_P_R_PV_PH_W 8 1143 #define FCFG1_FLASH_P_R_PV_PH_M 0xFF000000 1144 #define FCFG1_FLASH_P_R_PV_PH_S 24 1145 1146 // Field: [23:16] RH 1147 // 1148 // Internal. Only to be used through TI provided API. 1149 #define FCFG1_FLASH_P_R_PV_RH_W 8 1150 #define FCFG1_FLASH_P_R_PV_RH_M 0x00FF0000 1151 #define FCFG1_FLASH_P_R_PV_RH_S 16 1152 1153 // Field: [15:8] PVH 1154 // 1155 // Internal. Only to be used through TI provided API. 1156 #define FCFG1_FLASH_P_R_PV_PVH_W 8 1157 #define FCFG1_FLASH_P_R_PV_PVH_M 0x0000FF00 1158 #define FCFG1_FLASH_P_R_PV_PVH_S 8 1159 1160 // Field: [7:0] PVH2 1161 // 1162 // Internal. Only to be used through TI provided API. 1163 #define FCFG1_FLASH_P_R_PV_PVH2_W 8 1164 #define FCFG1_FLASH_P_R_PV_PVH2_M 0x000000FF 1165 #define FCFG1_FLASH_P_R_PV_PVH2_S 0 1166 1167 //***************************************************************************** 1168 // 1169 // Register: FCFG1_O_FLASH_EH_SEQ 1170 // 1171 //***************************************************************************** 1172 // Field: [31:24] EH 1173 // 1174 // Internal. Only to be used through TI provided API. 1175 #define FCFG1_FLASH_EH_SEQ_EH_W 8 1176 #define FCFG1_FLASH_EH_SEQ_EH_M 0xFF000000 1177 #define FCFG1_FLASH_EH_SEQ_EH_S 24 1178 1179 // Field: [23:16] SEQ 1180 // 1181 // Internal. Only to be used through TI provided API. 1182 #define FCFG1_FLASH_EH_SEQ_SEQ_W 8 1183 #define FCFG1_FLASH_EH_SEQ_SEQ_M 0x00FF0000 1184 #define FCFG1_FLASH_EH_SEQ_SEQ_S 16 1185 1186 // Field: [15:12] VSTAT 1187 // 1188 // Internal. Only to be used through TI provided API. 1189 #define FCFG1_FLASH_EH_SEQ_VSTAT_W 4 1190 #define FCFG1_FLASH_EH_SEQ_VSTAT_M 0x0000F000 1191 #define FCFG1_FLASH_EH_SEQ_VSTAT_S 12 1192 1193 // Field: [11:0] SM_FREQUENCY 1194 // 1195 // Internal. Only to be used through TI provided API. 1196 #define FCFG1_FLASH_EH_SEQ_SM_FREQUENCY_W 12 1197 #define FCFG1_FLASH_EH_SEQ_SM_FREQUENCY_M 0x00000FFF 1198 #define FCFG1_FLASH_EH_SEQ_SM_FREQUENCY_S 0 1199 1200 //***************************************************************************** 1201 // 1202 // Register: FCFG1_O_FLASH_VHV_E 1203 // 1204 //***************************************************************************** 1205 // Field: [31:16] VHV_E_START 1206 // 1207 // Internal. Only to be used through TI provided API. 1208 #define FCFG1_FLASH_VHV_E_VHV_E_START_W 16 1209 #define FCFG1_FLASH_VHV_E_VHV_E_START_M 0xFFFF0000 1210 #define FCFG1_FLASH_VHV_E_VHV_E_START_S 16 1211 1212 // Field: [15:0] VHV_E_STEP_HIGHT 1213 // 1214 // Internal. Only to be used through TI provided API. 1215 #define FCFG1_FLASH_VHV_E_VHV_E_STEP_HIGHT_W 16 1216 #define FCFG1_FLASH_VHV_E_VHV_E_STEP_HIGHT_M 0x0000FFFF 1217 #define FCFG1_FLASH_VHV_E_VHV_E_STEP_HIGHT_S 0 1218 1219 //***************************************************************************** 1220 // 1221 // Register: FCFG1_O_FLASH_PP 1222 // 1223 //***************************************************************************** 1224 // Field: [31:24] PUMP_SU 1225 // 1226 // Internal. Only to be used through TI provided API. 1227 #define FCFG1_FLASH_PP_PUMP_SU_W 8 1228 #define FCFG1_FLASH_PP_PUMP_SU_M 0xFF000000 1229 #define FCFG1_FLASH_PP_PUMP_SU_S 24 1230 1231 // Field: [15:0] MAX_PP 1232 // 1233 // Internal. Only to be used through TI provided API. 1234 #define FCFG1_FLASH_PP_MAX_PP_W 16 1235 #define FCFG1_FLASH_PP_MAX_PP_M 0x0000FFFF 1236 #define FCFG1_FLASH_PP_MAX_PP_S 0 1237 1238 //***************************************************************************** 1239 // 1240 // Register: FCFG1_O_FLASH_PROG_EP 1241 // 1242 //***************************************************************************** 1243 // Field: [31:16] MAX_EP 1244 // 1245 // Internal. Only to be used through TI provided API. 1246 #define FCFG1_FLASH_PROG_EP_MAX_EP_W 16 1247 #define FCFG1_FLASH_PROG_EP_MAX_EP_M 0xFFFF0000 1248 #define FCFG1_FLASH_PROG_EP_MAX_EP_S 16 1249 1250 // Field: [15:0] PROGRAM_PW 1251 // 1252 // Internal. Only to be used through TI provided API. 1253 #define FCFG1_FLASH_PROG_EP_PROGRAM_PW_W 16 1254 #define FCFG1_FLASH_PROG_EP_PROGRAM_PW_M 0x0000FFFF 1255 #define FCFG1_FLASH_PROG_EP_PROGRAM_PW_S 0 1256 1257 //***************************************************************************** 1258 // 1259 // Register: FCFG1_O_FLASH_ERA_PW 1260 // 1261 //***************************************************************************** 1262 // Field: [31:0] ERASE_PW 1263 // 1264 // Internal. Only to be used through TI provided API. 1265 #define FCFG1_FLASH_ERA_PW_ERASE_PW_W 32 1266 #define FCFG1_FLASH_ERA_PW_ERASE_PW_M 0xFFFFFFFF 1267 #define FCFG1_FLASH_ERA_PW_ERASE_PW_S 0 1268 1269 //***************************************************************************** 1270 // 1271 // Register: FCFG1_O_FLASH_VHV 1272 // 1273 //***************************************************************************** 1274 // Field: [27:24] TRIM13_P 1275 // 1276 // Internal. Only to be used through TI provided API. 1277 #define FCFG1_FLASH_VHV_TRIM13_P_W 4 1278 #define FCFG1_FLASH_VHV_TRIM13_P_M 0x0F000000 1279 #define FCFG1_FLASH_VHV_TRIM13_P_S 24 1280 1281 // Field: [19:16] VHV_P 1282 // 1283 // Internal. Only to be used through TI provided API. 1284 #define FCFG1_FLASH_VHV_VHV_P_W 4 1285 #define FCFG1_FLASH_VHV_VHV_P_M 0x000F0000 1286 #define FCFG1_FLASH_VHV_VHV_P_S 16 1287 1288 // Field: [11:8] TRIM13_E 1289 // 1290 // Internal. Only to be used through TI provided API. 1291 #define FCFG1_FLASH_VHV_TRIM13_E_W 4 1292 #define FCFG1_FLASH_VHV_TRIM13_E_M 0x00000F00 1293 #define FCFG1_FLASH_VHV_TRIM13_E_S 8 1294 1295 // Field: [3:0] VHV_E 1296 // 1297 // Internal. Only to be used through TI provided API. 1298 #define FCFG1_FLASH_VHV_VHV_E_W 4 1299 #define FCFG1_FLASH_VHV_VHV_E_M 0x0000000F 1300 #define FCFG1_FLASH_VHV_VHV_E_S 0 1301 1302 //***************************************************************************** 1303 // 1304 // Register: FCFG1_O_FLASH_VHV_PV 1305 // 1306 //***************************************************************************** 1307 // Field: [27:24] TRIM13_PV 1308 // 1309 // Internal. Only to be used through TI provided API. 1310 #define FCFG1_FLASH_VHV_PV_TRIM13_PV_W 4 1311 #define FCFG1_FLASH_VHV_PV_TRIM13_PV_M 0x0F000000 1312 #define FCFG1_FLASH_VHV_PV_TRIM13_PV_S 24 1313 1314 // Field: [19:16] VHV_PV 1315 // 1316 // Internal. Only to be used through TI provided API. 1317 #define FCFG1_FLASH_VHV_PV_VHV_PV_W 4 1318 #define FCFG1_FLASH_VHV_PV_VHV_PV_M 0x000F0000 1319 #define FCFG1_FLASH_VHV_PV_VHV_PV_S 16 1320 1321 // Field: [15:8] VCG2P5 1322 // 1323 // Internal. Only to be used through TI provided API. 1324 #define FCFG1_FLASH_VHV_PV_VCG2P5_W 8 1325 #define FCFG1_FLASH_VHV_PV_VCG2P5_M 0x0000FF00 1326 #define FCFG1_FLASH_VHV_PV_VCG2P5_S 8 1327 1328 // Field: [7:0] VINH 1329 // 1330 // Internal. Only to be used through TI provided API. 1331 #define FCFG1_FLASH_VHV_PV_VINH_W 8 1332 #define FCFG1_FLASH_VHV_PV_VINH_M 0x000000FF 1333 #define FCFG1_FLASH_VHV_PV_VINH_S 0 1334 1335 //***************************************************************************** 1336 // 1337 // Register: FCFG1_O_FLASH_V 1338 // 1339 //***************************************************************************** 1340 // Field: [31:24] VSL_P 1341 // 1342 // Internal. Only to be used through TI provided API. 1343 #define FCFG1_FLASH_V_VSL_P_W 8 1344 #define FCFG1_FLASH_V_VSL_P_M 0xFF000000 1345 #define FCFG1_FLASH_V_VSL_P_S 24 1346 1347 // Field: [23:16] VWL_P 1348 // 1349 // Internal. Only to be used through TI provided API. 1350 #define FCFG1_FLASH_V_VWL_P_W 8 1351 #define FCFG1_FLASH_V_VWL_P_M 0x00FF0000 1352 #define FCFG1_FLASH_V_VWL_P_S 16 1353 1354 // Field: [15:8] V_READ 1355 // 1356 // Internal. Only to be used through TI provided API. 1357 #define FCFG1_FLASH_V_V_READ_W 8 1358 #define FCFG1_FLASH_V_V_READ_M 0x0000FF00 1359 #define FCFG1_FLASH_V_V_READ_S 8 1360 1361 //***************************************************************************** 1362 // 1363 // Register: FCFG1_O_USER_ID 1364 // 1365 //***************************************************************************** 1366 // Field: [31:28] PG_REV 1367 // 1368 // Field used to distinguish revisions of the device. 1369 #define FCFG1_USER_ID_PG_REV_W 4 1370 #define FCFG1_USER_ID_PG_REV_M 0xF0000000 1371 #define FCFG1_USER_ID_PG_REV_S 28 1372 1373 // Field: [27:26] VER 1374 // 1375 // Version number. 1376 // 1377 // 0x0: Bits [25:12] of this register has the stated meaning. 1378 // 1379 // Any other setting indicate a different encoding of these bits. 1380 #define FCFG1_USER_ID_VER_W 2 1381 #define FCFG1_USER_ID_VER_M 0x0C000000 1382 #define FCFG1_USER_ID_VER_S 26 1383 1384 // Field: [22:19] SEQUENCE 1385 // 1386 // Sequence. 1387 // 1388 // Used to differentiate between marketing/orderable product where other fields 1389 // of USER_ID is the same (temp range, flash size, voltage range etc) 1390 #define FCFG1_USER_ID_SEQUENCE_W 4 1391 #define FCFG1_USER_ID_SEQUENCE_M 0x00780000 1392 #define FCFG1_USER_ID_SEQUENCE_S 19 1393 1394 // Field: [18:16] PKG 1395 // 1396 // Package type. 1397 // 1398 // 0x0: 4x4mm 1399 // 0x1: 5x5mm 1400 // 0x2: 7x7mm 1401 // 1402 // Others values are reserved for future use. 1403 #define FCFG1_USER_ID_PKG_W 3 1404 #define FCFG1_USER_ID_PKG_M 0x00070000 1405 #define FCFG1_USER_ID_PKG_S 16 1406 1407 // Field: [15:12] PROTOCOL 1408 // 1409 // Protocols supported. 1410 // 1411 // 0x1: BLE 1412 // 0x2: RF4CE 1413 // 0x4: Zigbee/6lowpan 1414 // 0x8: Proprietary 1415 // 1416 // More than one protocol can be supported on same device - values above are 1417 // then combined. 1418 #define FCFG1_USER_ID_PROTOCOL_W 4 1419 #define FCFG1_USER_ID_PROTOCOL_M 0x0000F000 1420 #define FCFG1_USER_ID_PROTOCOL_S 12 1421 1422 //***************************************************************************** 1423 // 1424 // Register: FCFG1_O_FLASH_OTP_DATA3 1425 // 1426 //***************************************************************************** 1427 // Field: [31:23] EC_STEP_SIZE 1428 // 1429 // Internal. Only to be used through TI provided API. 1430 #define FCFG1_FLASH_OTP_DATA3_EC_STEP_SIZE_W 9 1431 #define FCFG1_FLASH_OTP_DATA3_EC_STEP_SIZE_M 0xFF800000 1432 #define FCFG1_FLASH_OTP_DATA3_EC_STEP_SIZE_S 23 1433 1434 // Field: [22] DO_PRECOND 1435 // 1436 // Internal. Only to be used through TI provided API. 1437 #define FCFG1_FLASH_OTP_DATA3_DO_PRECOND 0x00400000 1438 #define FCFG1_FLASH_OTP_DATA3_DO_PRECOND_BITN 22 1439 #define FCFG1_FLASH_OTP_DATA3_DO_PRECOND_M 0x00400000 1440 #define FCFG1_FLASH_OTP_DATA3_DO_PRECOND_S 22 1441 1442 // Field: [21:18] MAX_EC_LEVEL 1443 // 1444 // Internal. Only to be used through TI provided API. 1445 #define FCFG1_FLASH_OTP_DATA3_MAX_EC_LEVEL_W 4 1446 #define FCFG1_FLASH_OTP_DATA3_MAX_EC_LEVEL_M 0x003C0000 1447 #define FCFG1_FLASH_OTP_DATA3_MAX_EC_LEVEL_S 18 1448 1449 // Field: [17:16] TRIM_1P7 1450 // 1451 // Internal. Only to be used through TI provided API. 1452 #define FCFG1_FLASH_OTP_DATA3_TRIM_1P7_W 2 1453 #define FCFG1_FLASH_OTP_DATA3_TRIM_1P7_M 0x00030000 1454 #define FCFG1_FLASH_OTP_DATA3_TRIM_1P7_S 16 1455 1456 // Field: [15:8] FLASH_SIZE 1457 // 1458 // Internal. Only to be used through TI provided API. 1459 #define FCFG1_FLASH_OTP_DATA3_FLASH_SIZE_W 8 1460 #define FCFG1_FLASH_OTP_DATA3_FLASH_SIZE_M 0x0000FF00 1461 #define FCFG1_FLASH_OTP_DATA3_FLASH_SIZE_S 8 1462 1463 // Field: [7:0] WAIT_SYSCODE 1464 // 1465 // Internal. Only to be used through TI provided API. 1466 #define FCFG1_FLASH_OTP_DATA3_WAIT_SYSCODE_W 8 1467 #define FCFG1_FLASH_OTP_DATA3_WAIT_SYSCODE_M 0x000000FF 1468 #define FCFG1_FLASH_OTP_DATA3_WAIT_SYSCODE_S 0 1469 1470 //***************************************************************************** 1471 // 1472 // Register: FCFG1_O_ANA2_TRIM 1473 // 1474 //***************************************************************************** 1475 // Field: [31] RCOSCHFCTRIMFRACT_EN 1476 // 1477 // Internal. Only to be used through TI provided API. 1478 #define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_EN 0x80000000 1479 #define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_EN_BITN 31 1480 #define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_EN_M 0x80000000 1481 #define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_EN_S 31 1482 1483 // Field: [30:26] RCOSCHFCTRIMFRACT 1484 // 1485 // Internal. Only to be used through TI provided API. 1486 #define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_W 5 1487 #define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_M 0x7C000000 1488 #define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_S 26 1489 1490 // Field: [24:23] SET_RCOSC_HF_FINE_RESISTOR 1491 // 1492 // Internal. Only to be used through TI provided API. 1493 #define FCFG1_ANA2_TRIM_SET_RCOSC_HF_FINE_RESISTOR_W 2 1494 #define FCFG1_ANA2_TRIM_SET_RCOSC_HF_FINE_RESISTOR_M 0x01800000 1495 #define FCFG1_ANA2_TRIM_SET_RCOSC_HF_FINE_RESISTOR_S 23 1496 1497 // Field: [22] ATESTLF_UDIGLDO_IBIAS_TRIM 1498 // 1499 // Internal. Only to be used through TI provided API. 1500 #define FCFG1_ANA2_TRIM_ATESTLF_UDIGLDO_IBIAS_TRIM 0x00400000 1501 #define FCFG1_ANA2_TRIM_ATESTLF_UDIGLDO_IBIAS_TRIM_BITN 22 1502 #define FCFG1_ANA2_TRIM_ATESTLF_UDIGLDO_IBIAS_TRIM_M 0x00400000 1503 #define FCFG1_ANA2_TRIM_ATESTLF_UDIGLDO_IBIAS_TRIM_S 22 1504 1505 // Field: [21:16] NANOAMP_RES_TRIM 1506 // 1507 // Internal. Only to be used through TI provided API. 1508 #define FCFG1_ANA2_TRIM_NANOAMP_RES_TRIM_W 6 1509 #define FCFG1_ANA2_TRIM_NANOAMP_RES_TRIM_M 0x003F0000 1510 #define FCFG1_ANA2_TRIM_NANOAMP_RES_TRIM_S 16 1511 1512 // Field: [11] DITHER_EN 1513 // 1514 // Internal. Only to be used through TI provided API. 1515 #define FCFG1_ANA2_TRIM_DITHER_EN 0x00000800 1516 #define FCFG1_ANA2_TRIM_DITHER_EN_BITN 11 1517 #define FCFG1_ANA2_TRIM_DITHER_EN_M 0x00000800 1518 #define FCFG1_ANA2_TRIM_DITHER_EN_S 11 1519 1520 // Field: [10:8] DCDC_IPEAK 1521 // 1522 // Internal. Only to be used through TI provided API. 1523 #define FCFG1_ANA2_TRIM_DCDC_IPEAK_W 3 1524 #define FCFG1_ANA2_TRIM_DCDC_IPEAK_M 0x00000700 1525 #define FCFG1_ANA2_TRIM_DCDC_IPEAK_S 8 1526 1527 // Field: [7:6] DEAD_TIME_TRIM 1528 // 1529 // Internal. Only to be used through TI provided API. 1530 #define FCFG1_ANA2_TRIM_DEAD_TIME_TRIM_W 2 1531 #define FCFG1_ANA2_TRIM_DEAD_TIME_TRIM_M 0x000000C0 1532 #define FCFG1_ANA2_TRIM_DEAD_TIME_TRIM_S 6 1533 1534 // Field: [5:3] DCDC_LOW_EN_SEL 1535 // 1536 // Internal. Only to be used through TI provided API. 1537 #define FCFG1_ANA2_TRIM_DCDC_LOW_EN_SEL_W 3 1538 #define FCFG1_ANA2_TRIM_DCDC_LOW_EN_SEL_M 0x00000038 1539 #define FCFG1_ANA2_TRIM_DCDC_LOW_EN_SEL_S 3 1540 1541 // Field: [2:0] DCDC_HIGH_EN_SEL 1542 // 1543 // Internal. Only to be used through TI provided API. 1544 #define FCFG1_ANA2_TRIM_DCDC_HIGH_EN_SEL_W 3 1545 #define FCFG1_ANA2_TRIM_DCDC_HIGH_EN_SEL_M 0x00000007 1546 #define FCFG1_ANA2_TRIM_DCDC_HIGH_EN_SEL_S 0 1547 1548 //***************************************************************************** 1549 // 1550 // Register: FCFG1_O_LDO_TRIM 1551 // 1552 //***************************************************************************** 1553 // Field: [28:24] VDDR_TRIM_SLEEP 1554 // 1555 // Internal. Only to be used through TI provided API. 1556 #define FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_W 5 1557 #define FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_M 0x1F000000 1558 #define FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_S 24 1559 1560 // Field: [18:16] GLDO_CURSRC 1561 // 1562 // Internal. Only to be used through TI provided API. 1563 #define FCFG1_LDO_TRIM_GLDO_CURSRC_W 3 1564 #define FCFG1_LDO_TRIM_GLDO_CURSRC_M 0x00070000 1565 #define FCFG1_LDO_TRIM_GLDO_CURSRC_S 16 1566 1567 // Field: [12:11] ITRIM_DIGLDO_LOAD 1568 // 1569 // Internal. Only to be used through TI provided API. 1570 #define FCFG1_LDO_TRIM_ITRIM_DIGLDO_LOAD_W 2 1571 #define FCFG1_LDO_TRIM_ITRIM_DIGLDO_LOAD_M 0x00001800 1572 #define FCFG1_LDO_TRIM_ITRIM_DIGLDO_LOAD_S 11 1573 1574 // Field: [10:8] ITRIM_UDIGLDO 1575 // 1576 // Internal. Only to be used through TI provided API. 1577 #define FCFG1_LDO_TRIM_ITRIM_UDIGLDO_W 3 1578 #define FCFG1_LDO_TRIM_ITRIM_UDIGLDO_M 0x00000700 1579 #define FCFG1_LDO_TRIM_ITRIM_UDIGLDO_S 8 1580 1581 // Field: [2:0] VTRIM_DELTA 1582 // 1583 // Internal. Only to be used through TI provided API. 1584 #define FCFG1_LDO_TRIM_VTRIM_DELTA_W 3 1585 #define FCFG1_LDO_TRIM_VTRIM_DELTA_M 0x00000007 1586 #define FCFG1_LDO_TRIM_VTRIM_DELTA_S 0 1587 1588 //***************************************************************************** 1589 // 1590 // Register: FCFG1_O_MAC_BLE_0 1591 // 1592 //***************************************************************************** 1593 // Field: [31:0] ADDR_0_31 1594 // 1595 // The first 32-bits of the 64-bit MAC BLE address 1596 #define FCFG1_MAC_BLE_0_ADDR_0_31_W 32 1597 #define FCFG1_MAC_BLE_0_ADDR_0_31_M 0xFFFFFFFF 1598 #define FCFG1_MAC_BLE_0_ADDR_0_31_S 0 1599 1600 //***************************************************************************** 1601 // 1602 // Register: FCFG1_O_MAC_BLE_1 1603 // 1604 //***************************************************************************** 1605 // Field: [31:0] ADDR_32_63 1606 // 1607 // The last 32-bits of the 64-bit MAC BLE address 1608 #define FCFG1_MAC_BLE_1_ADDR_32_63_W 32 1609 #define FCFG1_MAC_BLE_1_ADDR_32_63_M 0xFFFFFFFF 1610 #define FCFG1_MAC_BLE_1_ADDR_32_63_S 0 1611 1612 //***************************************************************************** 1613 // 1614 // Register: FCFG1_O_MAC_15_4_0 1615 // 1616 //***************************************************************************** 1617 // Field: [31:0] ADDR_0_31 1618 // 1619 // The first 32-bits of the 64-bit MAC 15.4 address 1620 #define FCFG1_MAC_15_4_0_ADDR_0_31_W 32 1621 #define FCFG1_MAC_15_4_0_ADDR_0_31_M 0xFFFFFFFF 1622 #define FCFG1_MAC_15_4_0_ADDR_0_31_S 0 1623 1624 //***************************************************************************** 1625 // 1626 // Register: FCFG1_O_MAC_15_4_1 1627 // 1628 //***************************************************************************** 1629 // Field: [31:0] ADDR_32_63 1630 // 1631 // The last 32-bits of the 64-bit MAC 15.4 address 1632 #define FCFG1_MAC_15_4_1_ADDR_32_63_W 32 1633 #define FCFG1_MAC_15_4_1_ADDR_32_63_M 0xFFFFFFFF 1634 #define FCFG1_MAC_15_4_1_ADDR_32_63_S 0 1635 1636 //***************************************************************************** 1637 // 1638 // Register: FCFG1_O_FLASH_OTP_DATA4 1639 // 1640 //***************************************************************************** 1641 // Field: [31] STANDBY_MODE_SEL_INT_WRT 1642 // 1643 // Internal. Only to be used through TI provided API. 1644 #define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT 0x80000000 1645 #define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_BITN 31 1646 #define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_M 0x80000000 1647 #define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_S 31 1648 1649 // Field: [30:29] STANDBY_PW_SEL_INT_WRT 1650 // 1651 // Internal. Only to be used through TI provided API. 1652 #define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_W 2 1653 #define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_M 0x60000000 1654 #define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_S 29 1655 1656 // Field: [28] DIS_STANDBY_INT_WRT 1657 // 1658 // Internal. Only to be used through TI provided API. 1659 #define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT 0x10000000 1660 #define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT_BITN 28 1661 #define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT_M 0x10000000 1662 #define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT_S 28 1663 1664 // Field: [27] DIS_IDLE_INT_WRT 1665 // 1666 // Internal. Only to be used through TI provided API. 1667 #define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT 0x08000000 1668 #define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT_BITN 27 1669 #define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT_M 0x08000000 1670 #define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT_S 27 1671 1672 // Field: [26:24] VIN_AT_X_INT_WRT 1673 // 1674 // Internal. Only to be used through TI provided API. 1675 #define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_W 3 1676 #define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_M 0x07000000 1677 #define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_S 24 1678 1679 // Field: [23] STANDBY_MODE_SEL_EXT_WRT 1680 // 1681 // Internal. Only to be used through TI provided API. 1682 #define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT 0x00800000 1683 #define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_BITN 23 1684 #define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_M 0x00800000 1685 #define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_S 23 1686 1687 // Field: [22:21] STANDBY_PW_SEL_EXT_WRT 1688 // 1689 // Internal. Only to be used through TI provided API. 1690 #define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_W 2 1691 #define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_M 0x00600000 1692 #define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_S 21 1693 1694 // Field: [20] DIS_STANDBY_EXT_WRT 1695 // 1696 // Internal. Only to be used through TI provided API. 1697 #define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT 0x00100000 1698 #define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT_BITN 20 1699 #define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT_M 0x00100000 1700 #define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT_S 20 1701 1702 // Field: [19] DIS_IDLE_EXT_WRT 1703 // 1704 // Internal. Only to be used through TI provided API. 1705 #define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT 0x00080000 1706 #define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT_BITN 19 1707 #define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT_M 0x00080000 1708 #define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT_S 19 1709 1710 // Field: [18:16] VIN_AT_X_EXT_WRT 1711 // 1712 // Internal. Only to be used through TI provided API. 1713 #define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_W 3 1714 #define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_M 0x00070000 1715 #define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_S 16 1716 1717 // Field: [15] STANDBY_MODE_SEL_INT_RD 1718 // 1719 // Internal. Only to be used through TI provided API. 1720 #define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD 0x00008000 1721 #define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_BITN 15 1722 #define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_M 0x00008000 1723 #define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_S 15 1724 1725 // Field: [14:13] STANDBY_PW_SEL_INT_RD 1726 // 1727 // Internal. Only to be used through TI provided API. 1728 #define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_W 2 1729 #define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_M 0x00006000 1730 #define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_S 13 1731 1732 // Field: [12] DIS_STANDBY_INT_RD 1733 // 1734 // Internal. Only to be used through TI provided API. 1735 #define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD 0x00001000 1736 #define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_BITN 12 1737 #define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_M 0x00001000 1738 #define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_S 12 1739 1740 // Field: [11] DIS_IDLE_INT_RD 1741 // 1742 // Internal. Only to be used through TI provided API. 1743 #define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD 0x00000800 1744 #define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_BITN 11 1745 #define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_M 0x00000800 1746 #define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_S 11 1747 1748 // Field: [10:8] VIN_AT_X_INT_RD 1749 // 1750 // Internal. Only to be used through TI provided API. 1751 #define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_W 3 1752 #define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_M 0x00000700 1753 #define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_S 8 1754 1755 // Field: [7] STANDBY_MODE_SEL_EXT_RD 1756 // 1757 // Internal. Only to be used through TI provided API. 1758 #define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD 0x00000080 1759 #define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_BITN 7 1760 #define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_M 0x00000080 1761 #define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_S 7 1762 1763 // Field: [6:5] STANDBY_PW_SEL_EXT_RD 1764 // 1765 // Internal. Only to be used through TI provided API. 1766 #define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_W 2 1767 #define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_M 0x00000060 1768 #define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_S 5 1769 1770 // Field: [4] DIS_STANDBY_EXT_RD 1771 // 1772 // Internal. Only to be used through TI provided API. 1773 #define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD 0x00000010 1774 #define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_BITN 4 1775 #define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_M 0x00000010 1776 #define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_S 4 1777 1778 // Field: [3] DIS_IDLE_EXT_RD 1779 // 1780 // Internal. Only to be used through TI provided API. 1781 #define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD 0x00000008 1782 #define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_BITN 3 1783 #define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_M 0x00000008 1784 #define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_S 3 1785 1786 // Field: [2:0] VIN_AT_X_EXT_RD 1787 // 1788 // Internal. Only to be used through TI provided API. 1789 #define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_W 3 1790 #define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_M 0x00000007 1791 #define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_S 0 1792 1793 //***************************************************************************** 1794 // 1795 // Register: FCFG1_O_MISC_TRIM 1796 // 1797 //***************************************************************************** 1798 // Field: [7:0] TEMPVSLOPE 1799 // 1800 // Signed byte value representing the TEMP slope with battery voltage, in 1801 // degrees C / V, with four fractional bits. 1802 #define FCFG1_MISC_TRIM_TEMPVSLOPE_W 8 1803 #define FCFG1_MISC_TRIM_TEMPVSLOPE_M 0x000000FF 1804 #define FCFG1_MISC_TRIM_TEMPVSLOPE_S 0 1805 1806 //***************************************************************************** 1807 // 1808 // Register: FCFG1_O_RCOSC_HF_TEMPCOMP 1809 // 1810 //***************************************************************************** 1811 // Field: [31:24] FINE_RESISTOR 1812 // 1813 // Internal. Only to be used through TI provided API. 1814 #define FCFG1_RCOSC_HF_TEMPCOMP_FINE_RESISTOR_W 8 1815 #define FCFG1_RCOSC_HF_TEMPCOMP_FINE_RESISTOR_M 0xFF000000 1816 #define FCFG1_RCOSC_HF_TEMPCOMP_FINE_RESISTOR_S 24 1817 1818 // Field: [23:16] CTRIM 1819 // 1820 // Internal. Only to be used through TI provided API. 1821 #define FCFG1_RCOSC_HF_TEMPCOMP_CTRIM_W 8 1822 #define FCFG1_RCOSC_HF_TEMPCOMP_CTRIM_M 0x00FF0000 1823 #define FCFG1_RCOSC_HF_TEMPCOMP_CTRIM_S 16 1824 1825 // Field: [15:8] CTRIMFRACT_QUAD 1826 // 1827 // Internal. Only to be used through TI provided API. 1828 #define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_QUAD_W 8 1829 #define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_QUAD_M 0x0000FF00 1830 #define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_QUAD_S 8 1831 1832 // Field: [7:0] CTRIMFRACT_SLOPE 1833 // 1834 // Internal. Only to be used through TI provided API. 1835 #define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_SLOPE_W 8 1836 #define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_SLOPE_M 0x000000FF 1837 #define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_SLOPE_S 0 1838 1839 //***************************************************************************** 1840 // 1841 // Register: FCFG1_O_ICEPICK_DEVICE_ID 1842 // 1843 //***************************************************************************** 1844 // Field: [31:28] PG_REV 1845 // 1846 // Field used to distinguish revisions of the device. 1847 #define FCFG1_ICEPICK_DEVICE_ID_PG_REV_W 4 1848 #define FCFG1_ICEPICK_DEVICE_ID_PG_REV_M 0xF0000000 1849 #define FCFG1_ICEPICK_DEVICE_ID_PG_REV_S 28 1850 1851 // Field: [27:12] WAFER_ID 1852 // 1853 // Field used to identify silicon die. 1854 #define FCFG1_ICEPICK_DEVICE_ID_WAFER_ID_W 16 1855 #define FCFG1_ICEPICK_DEVICE_ID_WAFER_ID_M 0x0FFFF000 1856 #define FCFG1_ICEPICK_DEVICE_ID_WAFER_ID_S 12 1857 1858 // Field: [11:0] MANUFACTURER_ID 1859 // 1860 // Manufacturer code. 1861 // 1862 // 0x02F: Texas Instruments 1863 #define FCFG1_ICEPICK_DEVICE_ID_MANUFACTURER_ID_W 12 1864 #define FCFG1_ICEPICK_DEVICE_ID_MANUFACTURER_ID_M 0x00000FFF 1865 #define FCFG1_ICEPICK_DEVICE_ID_MANUFACTURER_ID_S 0 1866 1867 //***************************************************************************** 1868 // 1869 // Register: FCFG1_O_FCFG1_REVISION 1870 // 1871 //***************************************************************************** 1872 // Field: [31:0] REV 1873 // 1874 // The revision number of the FCFG1 layout. This value will be read by 1875 // application SW in order to determine which FCFG1 parameters that have valid 1876 // values. This revision number must be incremented by 1 before any devices are 1877 // to be produced if the FCFG1 layout has changed since the previous production 1878 // of devices. 1879 // Value migth change without warning. 1880 #define FCFG1_FCFG1_REVISION_REV_W 32 1881 #define FCFG1_FCFG1_REVISION_REV_M 0xFFFFFFFF 1882 #define FCFG1_FCFG1_REVISION_REV_S 0 1883 1884 //***************************************************************************** 1885 // 1886 // Register: FCFG1_O_MISC_OTP_DATA 1887 // 1888 //***************************************************************************** 1889 // Field: [31:28] RCOSC_HF_ITUNE 1890 // 1891 // Internal. Only to be used through TI provided API. 1892 #define FCFG1_MISC_OTP_DATA_RCOSC_HF_ITUNE_W 4 1893 #define FCFG1_MISC_OTP_DATA_RCOSC_HF_ITUNE_M 0xF0000000 1894 #define FCFG1_MISC_OTP_DATA_RCOSC_HF_ITUNE_S 28 1895 1896 // Field: [27:20] RCOSC_HF_CRIM 1897 // 1898 // Internal. Only to be used through TI provided API. 1899 #define FCFG1_MISC_OTP_DATA_RCOSC_HF_CRIM_W 8 1900 #define FCFG1_MISC_OTP_DATA_RCOSC_HF_CRIM_M 0x0FF00000 1901 #define FCFG1_MISC_OTP_DATA_RCOSC_HF_CRIM_S 20 1902 1903 // Field: [19:15] PER_M 1904 // 1905 // Internal. Only to be used through TI provided API. 1906 #define FCFG1_MISC_OTP_DATA_PER_M_W 5 1907 #define FCFG1_MISC_OTP_DATA_PER_M_M 0x000F8000 1908 #define FCFG1_MISC_OTP_DATA_PER_M_S 15 1909 1910 // Field: [14:12] PER_E 1911 // 1912 // Internal. Only to be used through TI provided API. 1913 #define FCFG1_MISC_OTP_DATA_PER_E_W 3 1914 #define FCFG1_MISC_OTP_DATA_PER_E_M 0x00007000 1915 #define FCFG1_MISC_OTP_DATA_PER_E_S 12 1916 1917 // Field: [11:8] PO_TAIL_RES_TRIM 1918 // 1919 // Internal. Only to be used through TI provided API. 1920 #define FCFG1_MISC_OTP_DATA_PO_TAIL_RES_TRIM_W 4 1921 #define FCFG1_MISC_OTP_DATA_PO_TAIL_RES_TRIM_M 0x00000F00 1922 #define FCFG1_MISC_OTP_DATA_PO_TAIL_RES_TRIM_S 8 1923 1924 // Field: [7:0] TEST_PROGRAM_REV 1925 // 1926 // The revision of the test program used in the production process when FCFG1 1927 // was programmed. 1928 // Value migth change without warning. 1929 #define FCFG1_MISC_OTP_DATA_TEST_PROGRAM_REV_W 8 1930 #define FCFG1_MISC_OTP_DATA_TEST_PROGRAM_REV_M 0x000000FF 1931 #define FCFG1_MISC_OTP_DATA_TEST_PROGRAM_REV_S 0 1932 1933 //***************************************************************************** 1934 // 1935 // Register: FCFG1_O_IOCONF 1936 // 1937 //***************************************************************************** 1938 // Field: [6:0] GPIO_CNT 1939 // 1940 // This value is written to IOC:CFG.GPIO_CNT by boot FW while in safezone. 1941 #define FCFG1_IOCONF_GPIO_CNT_W 7 1942 #define FCFG1_IOCONF_GPIO_CNT_M 0x0000007F 1943 #define FCFG1_IOCONF_GPIO_CNT_S 0 1944 1945 //***************************************************************************** 1946 // 1947 // Register: FCFG1_O_CONFIG_IF_ADC 1948 // 1949 //***************************************************************************** 1950 // Field: [31:28] FF2ADJ 1951 // 1952 // Internal. Only to be used through TI provided API. 1953 #define FCFG1_CONFIG_IF_ADC_FF2ADJ_W 4 1954 #define FCFG1_CONFIG_IF_ADC_FF2ADJ_M 0xF0000000 1955 #define FCFG1_CONFIG_IF_ADC_FF2ADJ_S 28 1956 1957 // Field: [27:24] FF3ADJ 1958 // 1959 // Internal. Only to be used through TI provided API. 1960 #define FCFG1_CONFIG_IF_ADC_FF3ADJ_W 4 1961 #define FCFG1_CONFIG_IF_ADC_FF3ADJ_M 0x0F000000 1962 #define FCFG1_CONFIG_IF_ADC_FF3ADJ_S 24 1963 1964 // Field: [23:20] INT3ADJ 1965 // 1966 // Internal. Only to be used through TI provided API. 1967 #define FCFG1_CONFIG_IF_ADC_INT3ADJ_W 4 1968 #define FCFG1_CONFIG_IF_ADC_INT3ADJ_M 0x00F00000 1969 #define FCFG1_CONFIG_IF_ADC_INT3ADJ_S 20 1970 1971 // Field: [19:16] FF1ADJ 1972 // 1973 // Internal. Only to be used through TI provided API. 1974 #define FCFG1_CONFIG_IF_ADC_FF1ADJ_W 4 1975 #define FCFG1_CONFIG_IF_ADC_FF1ADJ_M 0x000F0000 1976 #define FCFG1_CONFIG_IF_ADC_FF1ADJ_S 16 1977 1978 // Field: [15:14] AAFCAP 1979 // 1980 // Internal. Only to be used through TI provided API. 1981 #define FCFG1_CONFIG_IF_ADC_AAFCAP_W 2 1982 #define FCFG1_CONFIG_IF_ADC_AAFCAP_M 0x0000C000 1983 #define FCFG1_CONFIG_IF_ADC_AAFCAP_S 14 1984 1985 // Field: [13:10] INT2ADJ 1986 // 1987 // Internal. Only to be used through TI provided API. 1988 #define FCFG1_CONFIG_IF_ADC_INT2ADJ_W 4 1989 #define FCFG1_CONFIG_IF_ADC_INT2ADJ_M 0x00003C00 1990 #define FCFG1_CONFIG_IF_ADC_INT2ADJ_S 10 1991 1992 // Field: [9:5] IFDIGLDO_TRIM_OUTPUT 1993 // 1994 // Internal. Only to be used through TI provided API. 1995 #define FCFG1_CONFIG_IF_ADC_IFDIGLDO_TRIM_OUTPUT_W 5 1996 #define FCFG1_CONFIG_IF_ADC_IFDIGLDO_TRIM_OUTPUT_M 0x000003E0 1997 #define FCFG1_CONFIG_IF_ADC_IFDIGLDO_TRIM_OUTPUT_S 5 1998 1999 // Field: [4:0] IFANALDO_TRIM_OUTPUT 2000 // 2001 // Internal. Only to be used through TI provided API. 2002 #define FCFG1_CONFIG_IF_ADC_IFANALDO_TRIM_OUTPUT_W 5 2003 #define FCFG1_CONFIG_IF_ADC_IFANALDO_TRIM_OUTPUT_M 0x0000001F 2004 #define FCFG1_CONFIG_IF_ADC_IFANALDO_TRIM_OUTPUT_S 0 2005 2006 //***************************************************************************** 2007 // 2008 // Register: FCFG1_O_CONFIG_OSC_TOP 2009 // 2010 //***************************************************************************** 2011 // Field: [29:26] XOSC_HF_ROW_Q12 2012 // 2013 // Internal. Only to be used through TI provided API. 2014 #define FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_W 4 2015 #define FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_M 0x3C000000 2016 #define FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_S 26 2017 2018 // Field: [25:10] XOSC_HF_COLUMN_Q12 2019 // 2020 // Internal. Only to be used through TI provided API. 2021 #define FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_W 16 2022 #define FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_M 0x03FFFC00 2023 #define FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_S 10 2024 2025 // Field: [9:2] RCOSCLF_CTUNE_TRIM 2026 // 2027 // Internal. Only to be used through TI provided API. 2028 #define FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_W 8 2029 #define FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_M 0x000003FC 2030 #define FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_S 2 2031 2032 // Field: [1:0] RCOSCLF_RTUNE_TRIM 2033 // 2034 // Internal. Only to be used through TI provided API. 2035 #define FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_W 2 2036 #define FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_M 0x00000003 2037 #define FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_S 0 2038 2039 //***************************************************************************** 2040 // 2041 // Register: FCFG1_O_CONFIG_RF_FRONTEND 2042 // 2043 //***************************************************************************** 2044 // Field: [31:28] IFAMP_IB 2045 // 2046 // Internal. Only to be used through TI provided API. 2047 #define FCFG1_CONFIG_RF_FRONTEND_IFAMP_IB_W 4 2048 #define FCFG1_CONFIG_RF_FRONTEND_IFAMP_IB_M 0xF0000000 2049 #define FCFG1_CONFIG_RF_FRONTEND_IFAMP_IB_S 28 2050 2051 // Field: [27:24] LNA_IB 2052 // 2053 // Internal. Only to be used through TI provided API. 2054 #define FCFG1_CONFIG_RF_FRONTEND_LNA_IB_W 4 2055 #define FCFG1_CONFIG_RF_FRONTEND_LNA_IB_M 0x0F000000 2056 #define FCFG1_CONFIG_RF_FRONTEND_LNA_IB_S 24 2057 2058 // Field: [23:19] IFAMP_TRIM 2059 // 2060 // Internal. Only to be used through TI provided API. 2061 #define FCFG1_CONFIG_RF_FRONTEND_IFAMP_TRIM_W 5 2062 #define FCFG1_CONFIG_RF_FRONTEND_IFAMP_TRIM_M 0x00F80000 2063 #define FCFG1_CONFIG_RF_FRONTEND_IFAMP_TRIM_S 19 2064 2065 // Field: [18:14] CTL_PA0_TRIM 2066 // 2067 // Internal. Only to be used through TI provided API. 2068 #define FCFG1_CONFIG_RF_FRONTEND_CTL_PA0_TRIM_W 5 2069 #define FCFG1_CONFIG_RF_FRONTEND_CTL_PA0_TRIM_M 0x0007C000 2070 #define FCFG1_CONFIG_RF_FRONTEND_CTL_PA0_TRIM_S 14 2071 2072 // Field: [13] PATRIMCOMPLETE_N 2073 // 2074 // Internal. Only to be used through TI provided API. 2075 #define FCFG1_CONFIG_RF_FRONTEND_PATRIMCOMPLETE_N 0x00002000 2076 #define FCFG1_CONFIG_RF_FRONTEND_PATRIMCOMPLETE_N_BITN 13 2077 #define FCFG1_CONFIG_RF_FRONTEND_PATRIMCOMPLETE_N_M 0x00002000 2078 #define FCFG1_CONFIG_RF_FRONTEND_PATRIMCOMPLETE_N_S 13 2079 2080 // Field: [6:0] RFLDO_TRIM_OUTPUT 2081 // 2082 // Internal. Only to be used through TI provided API. 2083 #define FCFG1_CONFIG_RF_FRONTEND_RFLDO_TRIM_OUTPUT_W 7 2084 #define FCFG1_CONFIG_RF_FRONTEND_RFLDO_TRIM_OUTPUT_M 0x0000007F 2085 #define FCFG1_CONFIG_RF_FRONTEND_RFLDO_TRIM_OUTPUT_S 0 2086 2087 //***************************************************************************** 2088 // 2089 // Register: FCFG1_O_CONFIG_SYNTH 2090 // 2091 //***************************************************************************** 2092 // Field: [27:12] RFC_MDM_DEMIQMC0 2093 // 2094 // Trim value for RF Core. 2095 // Value is read by RF Core ROM FW during RF Core initialization only on 2096 // cc13xx. 2097 #define FCFG1_CONFIG_SYNTH_RFC_MDM_DEMIQMC0_W 16 2098 #define FCFG1_CONFIG_SYNTH_RFC_MDM_DEMIQMC0_M 0x0FFFF000 2099 #define FCFG1_CONFIG_SYNTH_RFC_MDM_DEMIQMC0_S 12 2100 2101 // Field: [11:6] LDOVCO_TRIM_OUTPUT 2102 // 2103 // Internal. Only to be used through TI provided API. 2104 #define FCFG1_CONFIG_SYNTH_LDOVCO_TRIM_OUTPUT_W 6 2105 #define FCFG1_CONFIG_SYNTH_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 2106 #define FCFG1_CONFIG_SYNTH_LDOVCO_TRIM_OUTPUT_S 6 2107 2108 // Field: [5:0] SLDO_TRIM_OUTPUT 2109 // 2110 // Internal. Only to be used through TI provided API. 2111 #define FCFG1_CONFIG_SYNTH_SLDO_TRIM_OUTPUT_W 6 2112 #define FCFG1_CONFIG_SYNTH_SLDO_TRIM_OUTPUT_M 0x0000003F 2113 #define FCFG1_CONFIG_SYNTH_SLDO_TRIM_OUTPUT_S 0 2114 2115 //***************************************************************************** 2116 // 2117 // Register: FCFG1_O_SOC_ADC_ABS_GAIN 2118 // 2119 //***************************************************************************** 2120 // Field: [15:0] SOC_ADC_ABS_GAIN_TEMP1 2121 // 2122 // SOC_ADC gain in absolute reference mode at temperature 1 (30C). Calculated 2123 // in production test.. 2124 #define FCFG1_SOC_ADC_ABS_GAIN_SOC_ADC_ABS_GAIN_TEMP1_W 16 2125 #define FCFG1_SOC_ADC_ABS_GAIN_SOC_ADC_ABS_GAIN_TEMP1_M 0x0000FFFF 2126 #define FCFG1_SOC_ADC_ABS_GAIN_SOC_ADC_ABS_GAIN_TEMP1_S 0 2127 2128 //***************************************************************************** 2129 // 2130 // Register: FCFG1_O_SOC_ADC_REL_GAIN 2131 // 2132 //***************************************************************************** 2133 // Field: [15:0] SOC_ADC_REL_GAIN_TEMP1 2134 // 2135 // SOC_ADC gain in relative reference mode at temperature 1 (30C). Calculated 2136 // in production test.. 2137 #define FCFG1_SOC_ADC_REL_GAIN_SOC_ADC_REL_GAIN_TEMP1_W 16 2138 #define FCFG1_SOC_ADC_REL_GAIN_SOC_ADC_REL_GAIN_TEMP1_M 0x0000FFFF 2139 #define FCFG1_SOC_ADC_REL_GAIN_SOC_ADC_REL_GAIN_TEMP1_S 0 2140 2141 //***************************************************************************** 2142 // 2143 // Register: FCFG1_O_SOC_ADC_OFFSET_INT 2144 // 2145 //***************************************************************************** 2146 // Field: [23:16] SOC_ADC_REL_OFFSET_TEMP1 2147 // 2148 // SOC_ADC offset in relative reference mode at temperature 1 (30C). Signed 2149 // 8-bit number. Calculated in production test.. 2150 #define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_REL_OFFSET_TEMP1_W 8 2151 #define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_REL_OFFSET_TEMP1_M 0x00FF0000 2152 #define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_REL_OFFSET_TEMP1_S 16 2153 2154 // Field: [7:0] SOC_ADC_ABS_OFFSET_TEMP1 2155 // 2156 // SOC_ADC offset in absolute reference mode at temperature 1 (30C). Signed 2157 // 8-bit number. Calculated in production test.. 2158 #define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_ABS_OFFSET_TEMP1_W 8 2159 #define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_ABS_OFFSET_TEMP1_M 0x000000FF 2160 #define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_ABS_OFFSET_TEMP1_S 0 2161 2162 //***************************************************************************** 2163 // 2164 // Register: FCFG1_O_SOC_ADC_REF_TRIM_AND_OFFSET_EXT 2165 // 2166 //***************************************************************************** 2167 // Field: [5:0] SOC_ADC_REF_VOLTAGE_TRIM_TEMP1 2168 // 2169 // Internal. Only to be used through TI provided API. 2170 #define FCFG1_SOC_ADC_REF_TRIM_AND_OFFSET_EXT_SOC_ADC_REF_VOLTAGE_TRIM_TEMP1_W \ 2171 6 2172 #define FCFG1_SOC_ADC_REF_TRIM_AND_OFFSET_EXT_SOC_ADC_REF_VOLTAGE_TRIM_TEMP1_M \ 2173 0x0000003F 2174 #define FCFG1_SOC_ADC_REF_TRIM_AND_OFFSET_EXT_SOC_ADC_REF_VOLTAGE_TRIM_TEMP1_S \ 2175 0 2176 2177 //***************************************************************************** 2178 // 2179 // Register: FCFG1_O_AMPCOMP_TH1 2180 // 2181 //***************************************************************************** 2182 // Field: [23:18] HPMRAMP3_LTH 2183 // 2184 // Internal. Only to be used through TI provided API. 2185 #define FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_W 6 2186 #define FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_M 0x00FC0000 2187 #define FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_S 18 2188 2189 // Field: [15:10] HPMRAMP3_HTH 2190 // 2191 // Internal. Only to be used through TI provided API. 2192 #define FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_W 6 2193 #define FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_M 0x0000FC00 2194 #define FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_S 10 2195 2196 // Field: [9:6] IBIASCAP_LPTOHP_OL_CNT 2197 // 2198 // Internal. Only to be used through TI provided API. 2199 #define FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_W 4 2200 #define FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_M 0x000003C0 2201 #define FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_S 6 2202 2203 // Field: [5:0] HPMRAMP1_TH 2204 // 2205 // Internal. Only to be used through TI provided API. 2206 #define FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_W 6 2207 #define FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_M 0x0000003F 2208 #define FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_S 0 2209 2210 //***************************************************************************** 2211 // 2212 // Register: FCFG1_O_AMPCOMP_TH2 2213 // 2214 //***************************************************************************** 2215 // Field: [31:26] LPMUPDATE_LTH 2216 // 2217 // Internal. Only to be used through TI provided API. 2218 #define FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_W 6 2219 #define FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_M 0xFC000000 2220 #define FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_S 26 2221 2222 // Field: [23:18] LPMUPDATE_HTM 2223 // 2224 // Internal. Only to be used through TI provided API. 2225 #define FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_W 6 2226 #define FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_M 0x00FC0000 2227 #define FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_S 18 2228 2229 // Field: [15:10] ADC_COMP_AMPTH_LPM 2230 // 2231 // Internal. Only to be used through TI provided API. 2232 #define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_W 6 2233 #define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_M 0x0000FC00 2234 #define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_S 10 2235 2236 // Field: [7:2] ADC_COMP_AMPTH_HPM 2237 // 2238 // Internal. Only to be used through TI provided API. 2239 #define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_W 6 2240 #define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_M 0x000000FC 2241 #define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_S 2 2242 2243 //***************************************************************************** 2244 // 2245 // Register: FCFG1_O_AMPCOMP_CTRL1 2246 // 2247 //***************************************************************************** 2248 // Field: [30] AMPCOMP_REQ_MODE 2249 // 2250 // Internal. Only to be used through TI provided API. 2251 #define FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE 0x40000000 2252 #define FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_BITN 30 2253 #define FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_M 0x40000000 2254 #define FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_S 30 2255 2256 // Field: [23:20] IBIAS_OFFSET 2257 // 2258 // Internal. Only to be used through TI provided API. 2259 #define FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_W 4 2260 #define FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_M 0x00F00000 2261 #define FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_S 20 2262 2263 // Field: [19:16] IBIAS_INIT 2264 // 2265 // Internal. Only to be used through TI provided API. 2266 #define FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_W 4 2267 #define FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_M 0x000F0000 2268 #define FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_S 16 2269 2270 // Field: [15:8] LPM_IBIAS_WAIT_CNT_FINAL 2271 // 2272 // Internal. Only to be used through TI provided API. 2273 #define FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_W 8 2274 #define FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_M 0x0000FF00 2275 #define FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_S 8 2276 2277 // Field: [7:4] CAP_STEP 2278 // 2279 // Internal. Only to be used through TI provided API. 2280 #define FCFG1_AMPCOMP_CTRL1_CAP_STEP_W 4 2281 #define FCFG1_AMPCOMP_CTRL1_CAP_STEP_M 0x000000F0 2282 #define FCFG1_AMPCOMP_CTRL1_CAP_STEP_S 4 2283 2284 // Field: [3:0] IBIASCAP_HPTOLP_OL_CNT 2285 // 2286 // Internal. Only to be used through TI provided API. 2287 #define FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_W 4 2288 #define FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_M 0x0000000F 2289 #define FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_S 0 2290 2291 //***************************************************************************** 2292 // 2293 // Register: FCFG1_O_ANABYPASS_VALUE2 2294 // 2295 //***************************************************************************** 2296 // Field: [13:0] XOSC_HF_IBIASTHERM 2297 // 2298 // Internal. Only to be used through TI provided API. 2299 #define FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_W 14 2300 #define FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_M 0x00003FFF 2301 #define FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_S 0 2302 2303 //***************************************************************************** 2304 // 2305 // Register: FCFG1_O_CONFIG_MISC_ADC 2306 // 2307 //***************************************************************************** 2308 // Field: [17] RSSITRIMCOMPLETE_N 2309 // 2310 // Internal. Only to be used through TI provided API. 2311 #define FCFG1_CONFIG_MISC_ADC_RSSITRIMCOMPLETE_N 0x00020000 2312 #define FCFG1_CONFIG_MISC_ADC_RSSITRIMCOMPLETE_N_BITN 17 2313 #define FCFG1_CONFIG_MISC_ADC_RSSITRIMCOMPLETE_N_M 0x00020000 2314 #define FCFG1_CONFIG_MISC_ADC_RSSITRIMCOMPLETE_N_S 17 2315 2316 // Field: [16:9] RSSI_OFFSET 2317 // 2318 // Internal. Only to be used through TI provided API. 2319 #define FCFG1_CONFIG_MISC_ADC_RSSI_OFFSET_W 8 2320 #define FCFG1_CONFIG_MISC_ADC_RSSI_OFFSET_M 0x0001FE00 2321 #define FCFG1_CONFIG_MISC_ADC_RSSI_OFFSET_S 9 2322 2323 // Field: [8:6] QUANTCTLTHRES 2324 // 2325 // Internal. Only to be used through TI provided API. 2326 #define FCFG1_CONFIG_MISC_ADC_QUANTCTLTHRES_W 3 2327 #define FCFG1_CONFIG_MISC_ADC_QUANTCTLTHRES_M 0x000001C0 2328 #define FCFG1_CONFIG_MISC_ADC_QUANTCTLTHRES_S 6 2329 2330 // Field: [5:0] DACTRIM 2331 // 2332 // Internal. Only to be used through TI provided API. 2333 #define FCFG1_CONFIG_MISC_ADC_DACTRIM_W 6 2334 #define FCFG1_CONFIG_MISC_ADC_DACTRIM_M 0x0000003F 2335 #define FCFG1_CONFIG_MISC_ADC_DACTRIM_S 0 2336 2337 //***************************************************************************** 2338 // 2339 // Register: FCFG1_O_VOLT_TRIM 2340 // 2341 //***************************************************************************** 2342 // Field: [28:24] VDDR_TRIM_HH 2343 // 2344 // Internal. Only to be used through TI provided API. 2345 #define FCFG1_VOLT_TRIM_VDDR_TRIM_HH_W 5 2346 #define FCFG1_VOLT_TRIM_VDDR_TRIM_HH_M 0x1F000000 2347 #define FCFG1_VOLT_TRIM_VDDR_TRIM_HH_S 24 2348 2349 // Field: [20:16] VDDR_TRIM_H 2350 // 2351 // Internal. Only to be used through TI provided API. 2352 #define FCFG1_VOLT_TRIM_VDDR_TRIM_H_W 5 2353 #define FCFG1_VOLT_TRIM_VDDR_TRIM_H_M 0x001F0000 2354 #define FCFG1_VOLT_TRIM_VDDR_TRIM_H_S 16 2355 2356 // Field: [12:8] VDDR_TRIM_SLEEP_H 2357 // 2358 // Internal. Only to be used through TI provided API. 2359 #define FCFG1_VOLT_TRIM_VDDR_TRIM_SLEEP_H_W 5 2360 #define FCFG1_VOLT_TRIM_VDDR_TRIM_SLEEP_H_M 0x00001F00 2361 #define FCFG1_VOLT_TRIM_VDDR_TRIM_SLEEP_H_S 8 2362 2363 // Field: [4:0] TRIMBOD_H 2364 // 2365 // Internal. Only to be used through TI provided API. 2366 #define FCFG1_VOLT_TRIM_TRIMBOD_H_W 5 2367 #define FCFG1_VOLT_TRIM_TRIMBOD_H_M 0x0000001F 2368 #define FCFG1_VOLT_TRIM_TRIMBOD_H_S 0 2369 2370 //***************************************************************************** 2371 // 2372 // Register: FCFG1_O_OSC_CONF 2373 // 2374 //***************************************************************************** 2375 // Field: [29] ADC_SH_VBUF_EN 2376 // 2377 // Trim value for DDI_0_OSC:ADCDOUBLERNANOAMPCTL.ADC_SH_VBUF_EN. 2378 #define FCFG1_OSC_CONF_ADC_SH_VBUF_EN 0x20000000 2379 #define FCFG1_OSC_CONF_ADC_SH_VBUF_EN_BITN 29 2380 #define FCFG1_OSC_CONF_ADC_SH_VBUF_EN_M 0x20000000 2381 #define FCFG1_OSC_CONF_ADC_SH_VBUF_EN_S 29 2382 2383 // Field: [28] ADC_SH_MODE_EN 2384 // 2385 // Trim value for DDI_0_OSC:ADCDOUBLERNANOAMPCTL.ADC_SH_MODE_EN. 2386 #define FCFG1_OSC_CONF_ADC_SH_MODE_EN 0x10000000 2387 #define FCFG1_OSC_CONF_ADC_SH_MODE_EN_BITN 28 2388 #define FCFG1_OSC_CONF_ADC_SH_MODE_EN_M 0x10000000 2389 #define FCFG1_OSC_CONF_ADC_SH_MODE_EN_S 28 2390 2391 // Field: [27] ATESTLF_RCOSCLF_IBIAS_TRIM 2392 // 2393 // Trim value for DDI_0_OSC:ATESTCTL.ATESTLF_RCOSCLF_IBIAS_TRIM. 2394 #define FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM 0x08000000 2395 #define FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_BITN 27 2396 #define FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_M 0x08000000 2397 #define FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_S 27 2398 2399 // Field: [26:25] XOSCLF_REGULATOR_TRIM 2400 // 2401 // Trim value for DDI_0_OSC:LFOSCCTL.XOSCLF_REGULATOR_TRIM. 2402 #define FCFG1_OSC_CONF_XOSCLF_REGULATOR_TRIM_W 2 2403 #define FCFG1_OSC_CONF_XOSCLF_REGULATOR_TRIM_M 0x06000000 2404 #define FCFG1_OSC_CONF_XOSCLF_REGULATOR_TRIM_S 25 2405 2406 // Field: [24:21] XOSCLF_CMIRRWR_RATIO 2407 // 2408 // Trim value for DDI_0_OSC:LFOSCCTL.XOSCLF_CMIRRWR_RATIO. 2409 #define FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_W 4 2410 #define FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_M 0x01E00000 2411 #define FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_S 21 2412 2413 // Field: [20:19] XOSC_HF_FAST_START 2414 // 2415 // Trim value for DDI_0_OSC:CTL1.XOSC_HF_FAST_START. 2416 #define FCFG1_OSC_CONF_XOSC_HF_FAST_START_W 2 2417 #define FCFG1_OSC_CONF_XOSC_HF_FAST_START_M 0x00180000 2418 #define FCFG1_OSC_CONF_XOSC_HF_FAST_START_S 19 2419 2420 // Field: [18] XOSC_OPTION 2421 // 2422 // 0: XOSC_HF unavailable (may not be bonded out) 2423 // 1: XOSC_HF available (default) 2424 #define FCFG1_OSC_CONF_XOSC_OPTION 0x00040000 2425 #define FCFG1_OSC_CONF_XOSC_OPTION_BITN 18 2426 #define FCFG1_OSC_CONF_XOSC_OPTION_M 0x00040000 2427 #define FCFG1_OSC_CONF_XOSC_OPTION_S 18 2428 2429 // Field: [17] HPOSC_OPTION 2430 // 2431 // Internal. Only to be used through TI provided API. 2432 #define FCFG1_OSC_CONF_HPOSC_OPTION 0x00020000 2433 #define FCFG1_OSC_CONF_HPOSC_OPTION_BITN 17 2434 #define FCFG1_OSC_CONF_HPOSC_OPTION_M 0x00020000 2435 #define FCFG1_OSC_CONF_HPOSC_OPTION_S 17 2436 2437 // Field: [16] HPOSC_BIAS_HOLD_MODE_EN 2438 // 2439 // Internal. Only to be used through TI provided API. 2440 #define FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN 0x00010000 2441 #define FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_BITN 16 2442 #define FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_M 0x00010000 2443 #define FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_S 16 2444 2445 // Field: [15:12] HPOSC_CURRMIRR_RATIO 2446 // 2447 // Internal. Only to be used through TI provided API. 2448 #define FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_W 4 2449 #define FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_M 0x0000F000 2450 #define FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_S 12 2451 2452 // Field: [11:8] HPOSC_BIAS_RES_SET 2453 // 2454 // Internal. Only to be used through TI provided API. 2455 #define FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_W 4 2456 #define FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_M 0x00000F00 2457 #define FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_S 8 2458 2459 // Field: [7] HPOSC_FILTER_EN 2460 // 2461 // Internal. Only to be used through TI provided API. 2462 #define FCFG1_OSC_CONF_HPOSC_FILTER_EN 0x00000080 2463 #define FCFG1_OSC_CONF_HPOSC_FILTER_EN_BITN 7 2464 #define FCFG1_OSC_CONF_HPOSC_FILTER_EN_M 0x00000080 2465 #define FCFG1_OSC_CONF_HPOSC_FILTER_EN_S 7 2466 2467 // Field: [6:5] HPOSC_BIAS_RECHARGE_DELAY 2468 // 2469 // Internal. Only to be used through TI provided API. 2470 #define FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_W 2 2471 #define FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_M 0x00000060 2472 #define FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_S 5 2473 2474 // Field: [2:1] HPOSC_SERIES_CAP 2475 // 2476 // Internal. Only to be used through TI provided API. 2477 #define FCFG1_OSC_CONF_HPOSC_SERIES_CAP_W 2 2478 #define FCFG1_OSC_CONF_HPOSC_SERIES_CAP_M 0x00000006 2479 #define FCFG1_OSC_CONF_HPOSC_SERIES_CAP_S 1 2480 2481 // Field: [0] HPOSC_DIV3_BYPASS 2482 // 2483 // Internal. Only to be used through TI provided API. 2484 #define FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS 0x00000001 2485 #define FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_BITN 0 2486 #define FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_M 0x00000001 2487 #define FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_S 0 2488 2489 //***************************************************************************** 2490 // 2491 // Register: FCFG1_O_FREQ_OFFSET 2492 // 2493 //***************************************************************************** 2494 // Field: [31:16] HPOSC_COMP_P0 2495 // 2496 // Internal. Only to be used through TI provided API. 2497 #define FCFG1_FREQ_OFFSET_HPOSC_COMP_P0_W 16 2498 #define FCFG1_FREQ_OFFSET_HPOSC_COMP_P0_M 0xFFFF0000 2499 #define FCFG1_FREQ_OFFSET_HPOSC_COMP_P0_S 16 2500 2501 // Field: [15:8] HPOSC_COMP_P1 2502 // 2503 // Internal. Only to be used through TI provided API. 2504 #define FCFG1_FREQ_OFFSET_HPOSC_COMP_P1_W 8 2505 #define FCFG1_FREQ_OFFSET_HPOSC_COMP_P1_M 0x0000FF00 2506 #define FCFG1_FREQ_OFFSET_HPOSC_COMP_P1_S 8 2507 2508 // Field: [7:0] HPOSC_COMP_P2 2509 // 2510 // Internal. Only to be used through TI provided API. 2511 #define FCFG1_FREQ_OFFSET_HPOSC_COMP_P2_W 8 2512 #define FCFG1_FREQ_OFFSET_HPOSC_COMP_P2_M 0x000000FF 2513 #define FCFG1_FREQ_OFFSET_HPOSC_COMP_P2_S 0 2514 2515 //***************************************************************************** 2516 // 2517 // Register: FCFG1_O_CAP_TRIM 2518 // 2519 //***************************************************************************** 2520 // Field: [31:16] FLUX_CAP_0P28_TRIM 2521 // 2522 // Internal. Only to be used through TI provided API. 2523 #define FCFG1_CAP_TRIM_FLUX_CAP_0P28_TRIM_W 16 2524 #define FCFG1_CAP_TRIM_FLUX_CAP_0P28_TRIM_M 0xFFFF0000 2525 #define FCFG1_CAP_TRIM_FLUX_CAP_0P28_TRIM_S 16 2526 2527 // Field: [15:0] FLUX_CAP_0P4_TRIM 2528 // 2529 // Internal. Only to be used through TI provided API. 2530 #define FCFG1_CAP_TRIM_FLUX_CAP_0P4_TRIM_W 16 2531 #define FCFG1_CAP_TRIM_FLUX_CAP_0P4_TRIM_M 0x0000FFFF 2532 #define FCFG1_CAP_TRIM_FLUX_CAP_0P4_TRIM_S 0 2533 2534 //***************************************************************************** 2535 // 2536 // Register: FCFG1_O_MISC_OTP_DATA_1 2537 // 2538 //***************************************************************************** 2539 // Field: [28:27] PEAK_DET_ITRIM 2540 // 2541 // Internal. Only to be used through TI provided API. 2542 #define FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_W 2 2543 #define FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_M 0x18000000 2544 #define FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_S 27 2545 2546 // Field: [26:24] HP_BUF_ITRIM 2547 // 2548 // Internal. Only to be used through TI provided API. 2549 #define FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_W 3 2550 #define FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_M 0x07000000 2551 #define FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_S 24 2552 2553 // Field: [23:22] LP_BUF_ITRIM 2554 // 2555 // Internal. Only to be used through TI provided API. 2556 #define FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_W 2 2557 #define FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_M 0x00C00000 2558 #define FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_S 22 2559 2560 // Field: [21:20] DBLR_LOOP_FILTER_RESET_VOLTAGE 2561 // 2562 // Internal. Only to be used through TI provided API. 2563 #define FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_W 2 2564 #define FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_M 0x00300000 2565 #define FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_S 20 2566 2567 // Field: [19:10] HPM_IBIAS_WAIT_CNT 2568 // 2569 // Internal. Only to be used through TI provided API. 2570 #define FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_W 10 2571 #define FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_M 0x000FFC00 2572 #define FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_S 10 2573 2574 // Field: [9:4] LPM_IBIAS_WAIT_CNT 2575 // 2576 // Internal. Only to be used through TI provided API. 2577 #define FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_W 6 2578 #define FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_M 0x000003F0 2579 #define FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_S 4 2580 2581 // Field: [3:0] IDAC_STEP 2582 // 2583 // Internal. Only to be used through TI provided API. 2584 #define FCFG1_MISC_OTP_DATA_1_IDAC_STEP_W 4 2585 #define FCFG1_MISC_OTP_DATA_1_IDAC_STEP_M 0x0000000F 2586 #define FCFG1_MISC_OTP_DATA_1_IDAC_STEP_S 0 2587 2588 //***************************************************************************** 2589 // 2590 // Register: FCFG1_O_PWD_CURR_20C 2591 // 2592 //***************************************************************************** 2593 // Field: [31:24] DELTA_CACHE_REF 2594 // 2595 // Additional maximum current, in units of 1uA, with cache retention 2596 #define FCFG1_PWD_CURR_20C_DELTA_CACHE_REF_W 8 2597 #define FCFG1_PWD_CURR_20C_DELTA_CACHE_REF_M 0xFF000000 2598 #define FCFG1_PWD_CURR_20C_DELTA_CACHE_REF_S 24 2599 2600 // Field: [23:16] DELTA_RFMEM_RET 2601 // 2602 // Additional maximum current, in 1uA units, with RF memory retention 2603 #define FCFG1_PWD_CURR_20C_DELTA_RFMEM_RET_W 8 2604 #define FCFG1_PWD_CURR_20C_DELTA_RFMEM_RET_M 0x00FF0000 2605 #define FCFG1_PWD_CURR_20C_DELTA_RFMEM_RET_S 16 2606 2607 // Field: [15:8] DELTA_XOSC_LPM 2608 // 2609 // Additional maximum current, in units of 1uA, with XOSC_HF on in low-power 2610 // mode 2611 #define FCFG1_PWD_CURR_20C_DELTA_XOSC_LPM_W 8 2612 #define FCFG1_PWD_CURR_20C_DELTA_XOSC_LPM_M 0x0000FF00 2613 #define FCFG1_PWD_CURR_20C_DELTA_XOSC_LPM_S 8 2614 2615 // Field: [7:0] BASELINE 2616 // 2617 // Worst-case baseline maximum powerdown current, in units of 0.5uA 2618 #define FCFG1_PWD_CURR_20C_BASELINE_W 8 2619 #define FCFG1_PWD_CURR_20C_BASELINE_M 0x000000FF 2620 #define FCFG1_PWD_CURR_20C_BASELINE_S 0 2621 2622 //***************************************************************************** 2623 // 2624 // Register: FCFG1_O_PWD_CURR_35C 2625 // 2626 //***************************************************************************** 2627 // Field: [31:24] DELTA_CACHE_REF 2628 // 2629 // Additional maximum current, in units of 1uA, with cache retention 2630 #define FCFG1_PWD_CURR_35C_DELTA_CACHE_REF_W 8 2631 #define FCFG1_PWD_CURR_35C_DELTA_CACHE_REF_M 0xFF000000 2632 #define FCFG1_PWD_CURR_35C_DELTA_CACHE_REF_S 24 2633 2634 // Field: [23:16] DELTA_RFMEM_RET 2635 // 2636 // Additional maximum current, in 1uA units, with RF memory retention 2637 #define FCFG1_PWD_CURR_35C_DELTA_RFMEM_RET_W 8 2638 #define FCFG1_PWD_CURR_35C_DELTA_RFMEM_RET_M 0x00FF0000 2639 #define FCFG1_PWD_CURR_35C_DELTA_RFMEM_RET_S 16 2640 2641 // Field: [15:8] DELTA_XOSC_LPM 2642 // 2643 // Additional maximum current, in units of 1uA, with XOSC_HF on in low-power 2644 // mode 2645 #define FCFG1_PWD_CURR_35C_DELTA_XOSC_LPM_W 8 2646 #define FCFG1_PWD_CURR_35C_DELTA_XOSC_LPM_M 0x0000FF00 2647 #define FCFG1_PWD_CURR_35C_DELTA_XOSC_LPM_S 8 2648 2649 // Field: [7:0] BASELINE 2650 // 2651 // Worst-case baseline maximum powerdown current, in units of 0.5uA 2652 #define FCFG1_PWD_CURR_35C_BASELINE_W 8 2653 #define FCFG1_PWD_CURR_35C_BASELINE_M 0x000000FF 2654 #define FCFG1_PWD_CURR_35C_BASELINE_S 0 2655 2656 //***************************************************************************** 2657 // 2658 // Register: FCFG1_O_PWD_CURR_50C 2659 // 2660 //***************************************************************************** 2661 // Field: [31:24] DELTA_CACHE_REF 2662 // 2663 // Additional maximum current, in units of 1uA, with cache retention 2664 #define FCFG1_PWD_CURR_50C_DELTA_CACHE_REF_W 8 2665 #define FCFG1_PWD_CURR_50C_DELTA_CACHE_REF_M 0xFF000000 2666 #define FCFG1_PWD_CURR_50C_DELTA_CACHE_REF_S 24 2667 2668 // Field: [23:16] DELTA_RFMEM_RET 2669 // 2670 // Additional maximum current, in 1uA units, with RF memory retention 2671 #define FCFG1_PWD_CURR_50C_DELTA_RFMEM_RET_W 8 2672 #define FCFG1_PWD_CURR_50C_DELTA_RFMEM_RET_M 0x00FF0000 2673 #define FCFG1_PWD_CURR_50C_DELTA_RFMEM_RET_S 16 2674 2675 // Field: [15:8] DELTA_XOSC_LPM 2676 // 2677 // Additional maximum current, in units of 1uA, with XOSC_HF on in low-power 2678 // mode 2679 #define FCFG1_PWD_CURR_50C_DELTA_XOSC_LPM_W 8 2680 #define FCFG1_PWD_CURR_50C_DELTA_XOSC_LPM_M 0x0000FF00 2681 #define FCFG1_PWD_CURR_50C_DELTA_XOSC_LPM_S 8 2682 2683 // Field: [7:0] BASELINE 2684 // 2685 // Worst-case baseline maximum powerdown current, in units of 0.5uA 2686 #define FCFG1_PWD_CURR_50C_BASELINE_W 8 2687 #define FCFG1_PWD_CURR_50C_BASELINE_M 0x000000FF 2688 #define FCFG1_PWD_CURR_50C_BASELINE_S 0 2689 2690 //***************************************************************************** 2691 // 2692 // Register: FCFG1_O_PWD_CURR_65C 2693 // 2694 //***************************************************************************** 2695 // Field: [31:24] DELTA_CACHE_REF 2696 // 2697 // Additional maximum current, in units of 1uA, with cache retention 2698 #define FCFG1_PWD_CURR_65C_DELTA_CACHE_REF_W 8 2699 #define FCFG1_PWD_CURR_65C_DELTA_CACHE_REF_M 0xFF000000 2700 #define FCFG1_PWD_CURR_65C_DELTA_CACHE_REF_S 24 2701 2702 // Field: [23:16] DELTA_RFMEM_RET 2703 // 2704 // Additional maximum current, in 1uA units, with RF memory retention 2705 #define FCFG1_PWD_CURR_65C_DELTA_RFMEM_RET_W 8 2706 #define FCFG1_PWD_CURR_65C_DELTA_RFMEM_RET_M 0x00FF0000 2707 #define FCFG1_PWD_CURR_65C_DELTA_RFMEM_RET_S 16 2708 2709 // Field: [15:8] DELTA_XOSC_LPM 2710 // 2711 // Additional maximum current, in units of 1uA, with XOSC_HF on in low-power 2712 // mode 2713 #define FCFG1_PWD_CURR_65C_DELTA_XOSC_LPM_W 8 2714 #define FCFG1_PWD_CURR_65C_DELTA_XOSC_LPM_M 0x0000FF00 2715 #define FCFG1_PWD_CURR_65C_DELTA_XOSC_LPM_S 8 2716 2717 // Field: [7:0] BASELINE 2718 // 2719 // Worst-case baseline maximum powerdown current, in units of 0.5uA 2720 #define FCFG1_PWD_CURR_65C_BASELINE_W 8 2721 #define FCFG1_PWD_CURR_65C_BASELINE_M 0x000000FF 2722 #define FCFG1_PWD_CURR_65C_BASELINE_S 0 2723 2724 //***************************************************************************** 2725 // 2726 // Register: FCFG1_O_PWD_CURR_80C 2727 // 2728 //***************************************************************************** 2729 // Field: [31:24] DELTA_CACHE_REF 2730 // 2731 // Additional maximum current, in units of 1uA, with cache retention 2732 #define FCFG1_PWD_CURR_80C_DELTA_CACHE_REF_W 8 2733 #define FCFG1_PWD_CURR_80C_DELTA_CACHE_REF_M 0xFF000000 2734 #define FCFG1_PWD_CURR_80C_DELTA_CACHE_REF_S 24 2735 2736 // Field: [23:16] DELTA_RFMEM_RET 2737 // 2738 // Additional maximum current, in 1uA units, with RF memory retention 2739 #define FCFG1_PWD_CURR_80C_DELTA_RFMEM_RET_W 8 2740 #define FCFG1_PWD_CURR_80C_DELTA_RFMEM_RET_M 0x00FF0000 2741 #define FCFG1_PWD_CURR_80C_DELTA_RFMEM_RET_S 16 2742 2743 // Field: [15:8] DELTA_XOSC_LPM 2744 // 2745 // Additional maximum current, in units of 1uA, with XOSC_HF on in low-power 2746 // mode 2747 #define FCFG1_PWD_CURR_80C_DELTA_XOSC_LPM_W 8 2748 #define FCFG1_PWD_CURR_80C_DELTA_XOSC_LPM_M 0x0000FF00 2749 #define FCFG1_PWD_CURR_80C_DELTA_XOSC_LPM_S 8 2750 2751 // Field: [7:0] BASELINE 2752 // 2753 // Worst-case baseline maximum powerdown current, in units of 0.5uA 2754 #define FCFG1_PWD_CURR_80C_BASELINE_W 8 2755 #define FCFG1_PWD_CURR_80C_BASELINE_M 0x000000FF 2756 #define FCFG1_PWD_CURR_80C_BASELINE_S 0 2757 2758 //***************************************************************************** 2759 // 2760 // Register: FCFG1_O_PWD_CURR_95C 2761 // 2762 //***************************************************************************** 2763 // Field: [31:24] DELTA_CACHE_REF 2764 // 2765 // Additional maximum current, in units of 1uA, with cache retention 2766 #define FCFG1_PWD_CURR_95C_DELTA_CACHE_REF_W 8 2767 #define FCFG1_PWD_CURR_95C_DELTA_CACHE_REF_M 0xFF000000 2768 #define FCFG1_PWD_CURR_95C_DELTA_CACHE_REF_S 24 2769 2770 // Field: [23:16] DELTA_RFMEM_RET 2771 // 2772 // Additional maximum current, in 1uA units, with RF memory retention 2773 #define FCFG1_PWD_CURR_95C_DELTA_RFMEM_RET_W 8 2774 #define FCFG1_PWD_CURR_95C_DELTA_RFMEM_RET_M 0x00FF0000 2775 #define FCFG1_PWD_CURR_95C_DELTA_RFMEM_RET_S 16 2776 2777 // Field: [15:8] DELTA_XOSC_LPM 2778 // 2779 // Additional maximum current, in units of 1uA, with XOSC_HF on in low-power 2780 // mode 2781 #define FCFG1_PWD_CURR_95C_DELTA_XOSC_LPM_W 8 2782 #define FCFG1_PWD_CURR_95C_DELTA_XOSC_LPM_M 0x0000FF00 2783 #define FCFG1_PWD_CURR_95C_DELTA_XOSC_LPM_S 8 2784 2785 // Field: [7:0] BASELINE 2786 // 2787 // Worst-case baseline maximum powerdown current, in units of 0.5uA 2788 #define FCFG1_PWD_CURR_95C_BASELINE_W 8 2789 #define FCFG1_PWD_CURR_95C_BASELINE_M 0x000000FF 2790 #define FCFG1_PWD_CURR_95C_BASELINE_S 0 2791 2792 //***************************************************************************** 2793 // 2794 // Register: FCFG1_O_PWD_CURR_110C 2795 // 2796 //***************************************************************************** 2797 // Field: [31:24] DELTA_CACHE_REF 2798 // 2799 // Additional maximum current, in units of 1uA, with cache retention 2800 #define FCFG1_PWD_CURR_110C_DELTA_CACHE_REF_W 8 2801 #define FCFG1_PWD_CURR_110C_DELTA_CACHE_REF_M 0xFF000000 2802 #define FCFG1_PWD_CURR_110C_DELTA_CACHE_REF_S 24 2803 2804 // Field: [23:16] DELTA_RFMEM_RET 2805 // 2806 // Additional maximum current, in 1uA units, with RF memory retention 2807 #define FCFG1_PWD_CURR_110C_DELTA_RFMEM_RET_W 8 2808 #define FCFG1_PWD_CURR_110C_DELTA_RFMEM_RET_M 0x00FF0000 2809 #define FCFG1_PWD_CURR_110C_DELTA_RFMEM_RET_S 16 2810 2811 // Field: [15:8] DELTA_XOSC_LPM 2812 // 2813 // Additional maximum current, in units of 1uA, with XOSC_HF on in low-power 2814 // mode 2815 #define FCFG1_PWD_CURR_110C_DELTA_XOSC_LPM_W 8 2816 #define FCFG1_PWD_CURR_110C_DELTA_XOSC_LPM_M 0x0000FF00 2817 #define FCFG1_PWD_CURR_110C_DELTA_XOSC_LPM_S 8 2818 2819 // Field: [7:0] BASELINE 2820 // 2821 // Worst-case baseline maximum powerdown current, in units of 0.5uA 2822 #define FCFG1_PWD_CURR_110C_BASELINE_W 8 2823 #define FCFG1_PWD_CURR_110C_BASELINE_M 0x000000FF 2824 #define FCFG1_PWD_CURR_110C_BASELINE_S 0 2825 2826 //***************************************************************************** 2827 // 2828 // Register: FCFG1_O_PWD_CURR_125C 2829 // 2830 //***************************************************************************** 2831 // Field: [31:24] DELTA_CACHE_REF 2832 // 2833 // Additional maximum current, in units of 1uA, with cache retention 2834 #define FCFG1_PWD_CURR_125C_DELTA_CACHE_REF_W 8 2835 #define FCFG1_PWD_CURR_125C_DELTA_CACHE_REF_M 0xFF000000 2836 #define FCFG1_PWD_CURR_125C_DELTA_CACHE_REF_S 24 2837 2838 // Field: [23:16] DELTA_RFMEM_RET 2839 // 2840 // Additional maximum current, in 1uA units, with RF memory retention 2841 #define FCFG1_PWD_CURR_125C_DELTA_RFMEM_RET_W 8 2842 #define FCFG1_PWD_CURR_125C_DELTA_RFMEM_RET_M 0x00FF0000 2843 #define FCFG1_PWD_CURR_125C_DELTA_RFMEM_RET_S 16 2844 2845 // Field: [15:8] DELTA_XOSC_LPM 2846 // 2847 // Additional maximum current, in units of 1uA, with XOSC_HF on in low-power 2848 // mode 2849 #define FCFG1_PWD_CURR_125C_DELTA_XOSC_LPM_W 8 2850 #define FCFG1_PWD_CURR_125C_DELTA_XOSC_LPM_M 0x0000FF00 2851 #define FCFG1_PWD_CURR_125C_DELTA_XOSC_LPM_S 8 2852 2853 // Field: [7:0] BASELINE 2854 // 2855 // Worst-case baseline maximum powerdown current, in units of 0.5uA 2856 #define FCFG1_PWD_CURR_125C_BASELINE_W 8 2857 #define FCFG1_PWD_CURR_125C_BASELINE_M 0x000000FF 2858 #define FCFG1_PWD_CURR_125C_BASELINE_S 0 2859 2860 2861 #endif // __FCFG1__ 2862