1 /****************************************************************************** 2 * Filename: hw_i2s_h 3 * Revised: 2015-11-12 13:07:02 +0100 (Thu, 12 Nov 2015) 4 * Revision: 45056 5 * 6 * Copyright (c) 2015, Texas Instruments Incorporated 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions are met: 11 * 12 * 1) Redistributions of source code must retain the above copyright notice, 13 * this list of conditions and the following disclaimer. 14 * 15 * 2) Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 19 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may 20 * be used to endorse or promote products derived from this software without 21 * specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 * 35 ******************************************************************************/ 36 37 #ifndef __HW_I2S_H__ 38 #define __HW_I2S_H__ 39 40 //***************************************************************************** 41 // 42 // This section defines the register offsets of 43 // I2S component 44 // 45 //***************************************************************************** 46 // WCLK Source Selection 47 #define I2S_O_AIFWCLKSRC 0x00000000 48 49 // DMA Buffer Size Configuration 50 #define I2S_O_AIFDMACFG 0x00000004 51 52 // Pin Direction 53 #define I2S_O_AIFDIRCFG 0x00000008 54 55 // Serial Interface Format Configuration 56 #define I2S_O_AIFFMTCFG 0x0000000C 57 58 // Word Selection Bit Mask for Pin 0 59 #define I2S_O_AIFWMASK0 0x00000010 60 61 // Word Selection Bit Mask for Pin 1 62 #define I2S_O_AIFWMASK1 0x00000014 63 64 // Word Selection Bit Mask for Pin 2 65 #define I2S_O_AIFWMASK2 0x00000018 66 67 // Audio Interface PWM Debug Value 68 #define I2S_O_AIFPWMVALUE 0x0000001C 69 70 // DMA Input Buffer Next Pointer 71 #define I2S_O_AIFINPTRNEXT 0x00000020 72 73 // DMA Input Buffer Current Pointer 74 #define I2S_O_AIFINPTR 0x00000024 75 76 // DMA Output Buffer Next Pointer 77 #define I2S_O_AIFOUTPTRNEXT 0x00000028 78 79 // DMA Output Buffer Current Pointer 80 #define I2S_O_AIFOUTPTR 0x0000002C 81 82 // SampleStaMP Generator Control Register 83 #define I2S_O_STMPCTL 0x00000034 84 85 // Captured XOSC Counter Value, Capture Channel 0 86 #define I2S_O_STMPXCNTCAPT0 0x00000038 87 88 // XOSC Period Value 89 #define I2S_O_STMPXPER 0x0000003C 90 91 // Captured WCLK Counter Value, Capture Channel 0 92 #define I2S_O_STMPWCNTCAPT0 0x00000040 93 94 // WCLK Counter Period Value 95 #define I2S_O_STMPWPER 0x00000044 96 97 // WCLK Counter Trigger Value for Input Pins 98 #define I2S_O_STMPINTRIG 0x00000048 99 100 // WCLK Counter Trigger Value for Output Pins 101 #define I2S_O_STMPOUTTRIG 0x0000004C 102 103 // WCLK Counter Set Operation 104 #define I2S_O_STMPWSET 0x00000050 105 106 // WCLK Counter Add Operation 107 #define I2S_O_STMPWADD 0x00000054 108 109 // XOSC Minimum Period Value 110 #define I2S_O_STMPXPERMIN 0x00000058 111 112 // Current Value of WCNT 113 #define I2S_O_STMPWCNT 0x0000005C 114 115 // Current Value of XCNT 116 #define I2S_O_STMPXCNT 0x00000060 117 118 // Captured XOSC Counter Value, Capture Channel 1 119 #define I2S_O_STMPXCNTCAPT1 0x00000064 120 121 // Captured WCLK Counter Value, Capture Channel 1 122 #define I2S_O_STMPWCNTCAPT1 0x00000068 123 124 // Masked Interrupt Status Register 125 #define I2S_O_IRQMASK 0x00000070 126 127 // Raw Interrupt Status Register 128 #define I2S_O_IRQFLAGS 0x00000074 129 130 // Interrupt Set Register 131 #define I2S_O_IRQSET 0x00000078 132 133 // Interrupt Clear Register 134 #define I2S_O_IRQCLR 0x0000007C 135 136 //***************************************************************************** 137 // 138 // Register: I2S_O_AIFWCLKSRC 139 // 140 //***************************************************************************** 141 // Field: [2] WCLK_INV 142 // 143 // Inverts WCLK source (pad or internal) when set. 144 // 145 // 0: Not inverted 146 // 1: Inverted 147 #define I2S_AIFWCLKSRC_WCLK_INV 0x00000004 148 #define I2S_AIFWCLKSRC_WCLK_INV_BITN 2 149 #define I2S_AIFWCLKSRC_WCLK_INV_M 0x00000004 150 #define I2S_AIFWCLKSRC_WCLK_INV_S 2 151 152 // Field: [1:0] WCLK_SRC 153 // 154 // Selects WCLK source for AIF (should be the same as the BCLK source). The 155 // BCLK source is defined in the PRCM:I2SBCLKSEL.SRC 156 // ENUMs: 157 // RESERVED Not supported. Will give same WCLK as 'NONE' 158 // ('00') 159 // INT Internal WCLK generator, from module PRCM/ClkCtrl 160 // EXT External WCLK generator, from pad 161 // NONE None ('0') 162 #define I2S_AIFWCLKSRC_WCLK_SRC_W 2 163 #define I2S_AIFWCLKSRC_WCLK_SRC_M 0x00000003 164 #define I2S_AIFWCLKSRC_WCLK_SRC_S 0 165 #define I2S_AIFWCLKSRC_WCLK_SRC_RESERVED 0x00000003 166 #define I2S_AIFWCLKSRC_WCLK_SRC_INT 0x00000002 167 #define I2S_AIFWCLKSRC_WCLK_SRC_EXT 0x00000001 168 #define I2S_AIFWCLKSRC_WCLK_SRC_NONE 0x00000000 169 170 //***************************************************************************** 171 // 172 // Register: I2S_O_AIFDMACFG 173 // 174 //***************************************************************************** 175 // Field: [7:0] END_FRAME_IDX 176 // 177 // Defines the length of the Writing a non-zero value to this registerfield 178 // enables and initializes AIF. Note that before doing so, all other 179 // configuration must have been done, and AIFINPTR/AIFOUTPTR must have been 180 // loaded. 181 #define I2S_AIFDMACFG_END_FRAME_IDX_W 8 182 #define I2S_AIFDMACFG_END_FRAME_IDX_M 0x000000FF 183 #define I2S_AIFDMACFG_END_FRAME_IDX_S 0 184 185 //***************************************************************************** 186 // 187 // Register: I2S_O_AIFDIRCFG 188 // 189 //***************************************************************************** 190 // Field: [9:8] AD2 191 // 192 // Configures the AD2 audio data pin usage 193 // 194 // 0x3: Reserved 195 // ENUMs: 196 // OUT Output mode 197 // IN Input mode 198 // DIS Not in use (disabled) 199 #define I2S_AIFDIRCFG_AD2_W 2 200 #define I2S_AIFDIRCFG_AD2_M 0x00000300 201 #define I2S_AIFDIRCFG_AD2_S 8 202 #define I2S_AIFDIRCFG_AD2_OUT 0x00000200 203 #define I2S_AIFDIRCFG_AD2_IN 0x00000100 204 #define I2S_AIFDIRCFG_AD2_DIS 0x00000000 205 206 // Field: [5:4] AD1 207 // 208 // Configures the AD1 audio data pin usage: 209 // 210 // 0x3: Reserved 211 // ENUMs: 212 // OUT Output mode 213 // IN Input mode 214 // DIS Not in use (disabled) 215 #define I2S_AIFDIRCFG_AD1_W 2 216 #define I2S_AIFDIRCFG_AD1_M 0x00000030 217 #define I2S_AIFDIRCFG_AD1_S 4 218 #define I2S_AIFDIRCFG_AD1_OUT 0x00000020 219 #define I2S_AIFDIRCFG_AD1_IN 0x00000010 220 #define I2S_AIFDIRCFG_AD1_DIS 0x00000000 221 222 // Field: [1:0] AD0 223 // 224 // Configures the AD0 audio data pin usage: 225 // 226 // 0x3: Reserved 227 // ENUMs: 228 // OUT Output mode 229 // IN Input mode 230 // DIS Not in use (disabled) 231 #define I2S_AIFDIRCFG_AD0_W 2 232 #define I2S_AIFDIRCFG_AD0_M 0x00000003 233 #define I2S_AIFDIRCFG_AD0_S 0 234 #define I2S_AIFDIRCFG_AD0_OUT 0x00000002 235 #define I2S_AIFDIRCFG_AD0_IN 0x00000001 236 #define I2S_AIFDIRCFG_AD0_DIS 0x00000000 237 238 //***************************************************************************** 239 // 240 // Register: I2S_O_AIFFMTCFG 241 // 242 //***************************************************************************** 243 // Field: [15:8] DATA_DELAY 244 // 245 // The number of BCLK periods between a WCLK edge and MSB of the first word in 246 // a phase: 247 // 248 // 0x00: LJF format 249 // 0x01: I2S and DSP format 250 // 0x02: RJF format 251 // ... 252 // 0xFF: RJF format 253 // 254 // Note: When 0, MSB of the next word will be output in the idle period between 255 // LSB of the previous word and the start of the next word. Otherwise logical 0 256 // will be output until the data delay has expired. 257 #define I2S_AIFFMTCFG_DATA_DELAY_W 8 258 #define I2S_AIFFMTCFG_DATA_DELAY_M 0x0000FF00 259 #define I2S_AIFFMTCFG_DATA_DELAY_S 8 260 261 // Field: [7] MEM_LEN_24 262 // 263 // The size of each word stored to or loaded from memory: 264 // ENUMs: 265 // 24BIT 24-bit (one 8 bit and one 16 bit locked access per 266 // sample) 267 // 16BIT 16-bit (one 16 bit access per sample) 268 #define I2S_AIFFMTCFG_MEM_LEN_24 0x00000080 269 #define I2S_AIFFMTCFG_MEM_LEN_24_BITN 7 270 #define I2S_AIFFMTCFG_MEM_LEN_24_M 0x00000080 271 #define I2S_AIFFMTCFG_MEM_LEN_24_S 7 272 #define I2S_AIFFMTCFG_MEM_LEN_24_24BIT 0x00000080 273 #define I2S_AIFFMTCFG_MEM_LEN_24_16BIT 0x00000000 274 275 // Field: [6] SMPL_EDGE 276 // 277 // On the serial audio interface, data (and wclk) is sampled and clocked out on 278 // opposite edges of BCLK. 279 // ENUMs: 280 // POS Data is sampled on the positive edge and clocked 281 // out on the negative edge. 282 // NEG Data is sampled on the negative edge and clocked 283 // out on the positive edge. 284 #define I2S_AIFFMTCFG_SMPL_EDGE 0x00000040 285 #define I2S_AIFFMTCFG_SMPL_EDGE_BITN 6 286 #define I2S_AIFFMTCFG_SMPL_EDGE_M 0x00000040 287 #define I2S_AIFFMTCFG_SMPL_EDGE_S 6 288 #define I2S_AIFFMTCFG_SMPL_EDGE_POS 0x00000040 289 #define I2S_AIFFMTCFG_SMPL_EDGE_NEG 0x00000000 290 291 // Field: [5] DUAL_PHASE 292 // 293 // Selects dual- or single-phase format. 294 // 295 // 0: Single-phase 296 // 1: Dual-phase 297 #define I2S_AIFFMTCFG_DUAL_PHASE 0x00000020 298 #define I2S_AIFFMTCFG_DUAL_PHASE_BITN 5 299 #define I2S_AIFFMTCFG_DUAL_PHASE_M 0x00000020 300 #define I2S_AIFFMTCFG_DUAL_PHASE_S 5 301 302 // Field: [4:0] WORD_LEN 303 // 304 // Number of bits per word (8-24): 305 // In single-phase format, this is the exact number of bits per word. 306 // In dual-phase format, this is the maximum number of bits per word. 307 // 308 // Values below 8 and above 24 give undefined behavior. Data written to memory 309 // is always aligned to 16 or 24 bits as defined by MEM_LEN_24. Bit widths that 310 // differ from this alignment will either be truncated or zero padded. 311 #define I2S_AIFFMTCFG_WORD_LEN_W 5 312 #define I2S_AIFFMTCFG_WORD_LEN_M 0x0000001F 313 #define I2S_AIFFMTCFG_WORD_LEN_S 0 314 315 //***************************************************************************** 316 // 317 // Register: I2S_O_AIFWMASK0 318 // 319 //***************************************************************************** 320 // Field: [7:0] MASK 321 // 322 // Bit-mask indicating valid channels in a frame on AD0. 323 // 324 // In single-phase mode, each bit represents one channel, starting with LSB for 325 // the first word in the frame. A frame can contain up to 8 channels. Channels 326 // that are not included in the mask will not be sampled and stored in memory, 327 // and clocked out as '0'. 328 // 329 // In dual-phase mode, only the two LSBs are considered. For a stereo 330 // configuration, set both bits. For a mono configuration, set bit 0 only. In 331 // mono mode, only channel 0 will be sampled and stored to memory, and channel 332 // 0 will be repeated when clocked out. 333 // 334 // In mono mode, only channel 0 will be sampled and stored to memory, and 335 // channel 0 will be repeated in the second phase when clocked out. 336 // 337 // If all bits are zero, no input words will be stored to memory, and the 338 // output data lines will be constant '0'. This can be utilized when PWM debug 339 // output is desired without any actively used output pins. 340 #define I2S_AIFWMASK0_MASK_W 8 341 #define I2S_AIFWMASK0_MASK_M 0x000000FF 342 #define I2S_AIFWMASK0_MASK_S 0 343 344 //***************************************************************************** 345 // 346 // Register: I2S_O_AIFWMASK1 347 // 348 //***************************************************************************** 349 // Field: [7:0] MASK 350 // 351 // Bit-mask indicating valid channels in a frame on AD1. 352 // 353 // In single-phase mode, each bit represents one channel, starting with LSB for 354 // the first word in the frame. A frame can contain up to 8 channels. Channels 355 // that are not included in the mask will not be sampled and stored in memory, 356 // and clocked out as '0'. 357 // 358 // In dual-phase mode, only the two LSBs are considered. For a stereo 359 // configuration, set both bits. For a mono configuration, set bit 0 only. In 360 // mono mode, only channel 0 will be sampled and stored to memory, and channel 361 // 0 will be repeated when clocked out. 362 // 363 // In mono mode, only channel 0 will be sampled and stored to memory, and 364 // channel 0 will be repeated in the second phase when clocked out. 365 // 366 // If all bits are zero, no input words will be stored to memory, and the 367 // output data lines will be constant '0'. This can be utilized when PWM debug 368 // output is desired without any actively used output pins. 369 #define I2S_AIFWMASK1_MASK_W 8 370 #define I2S_AIFWMASK1_MASK_M 0x000000FF 371 #define I2S_AIFWMASK1_MASK_S 0 372 373 //***************************************************************************** 374 // 375 // Register: I2S_O_AIFWMASK2 376 // 377 //***************************************************************************** 378 // Field: [7:0] MASK 379 // 380 // Bit-mask indicating valid channels in a frame on AD2 381 // 382 // In single-phase mode, each bit represents one channel, starting with LSB for 383 // the first word in the frame. A frame can contain up to 8 channels. Channels 384 // that are not included in the mask will not be sampled and stored in memory, 385 // and clocked out as '0'. 386 // 387 // In dual-phase mode, only the two LSBs are considered. For a stereo 388 // configuration, set both bits. For a mono configuration, set bit 0 only. In 389 // mono mode, only channel 0 will be sampled and stored to memory, and channel 390 // 0 will be repeated when clocked out. 391 // 392 // In mono mode, only channel 0 will be sampled and stored to memory, and 393 // channel 0 will be repeated in the second phase when clocked out. 394 // 395 // If all bits are zero, no input words will be stored to memory, and the 396 // output data lines will be constant '0'. This can be utilized when PWM debug 397 // output is desired without any actively used output pins. 398 #define I2S_AIFWMASK2_MASK_W 8 399 #define I2S_AIFWMASK2_MASK_M 0x000000FF 400 #define I2S_AIFWMASK2_MASK_S 0 401 402 //***************************************************************************** 403 // 404 // Register: I2S_O_AIFPWMVALUE 405 // 406 //***************************************************************************** 407 // Field: [15:0] PULSE_WIDTH 408 // 409 // The value written to this register determines the width of the active high 410 // PWM pulse (pwm_debug), which starts together with MSB of the first output 411 // word in a DMA buffer: 412 // 413 // 0x0000: Constant low 414 // 0x0001: Width of the pulse (number of BCLK cycles, here 1). 415 // ... 416 // 0xFFFE: Width of the pulse (number of BCLK cycles, here 65534). 417 // 0xFFFF: Constant high 418 #define I2S_AIFPWMVALUE_PULSE_WIDTH_W 16 419 #define I2S_AIFPWMVALUE_PULSE_WIDTH_M 0x0000FFFF 420 #define I2S_AIFPWMVALUE_PULSE_WIDTH_S 0 421 422 //***************************************************************************** 423 // 424 // Register: I2S_O_AIFINPTRNEXT 425 // 426 //***************************************************************************** 427 // Field: [31:0] PTR 428 // 429 // Pointer to the first byte in the next DMA input buffer. 430 // 431 // The read value equals the last written value until the currently used DMA 432 // input buffer is completed, and then becomes null when the last written value 433 // is transferred to the DMA controller to start on the next buffer. This event 434 // is signalized by aif_dma_in_irq. 435 // 436 // At startup, the value must be written once before and once after configuring 437 // the DMA buffer size in AIFDMACFG. 438 // 439 // The next pointer must be written to this register while the DMA function 440 // uses the previously written pointer. If not written in time, 441 // IRQFLAGS.PTR_ERR will be raised and all input pins will be disabled. 442 // 443 // Note the following limitations: 444 // - Address space wrapping is not supported. That means address(last sample) 445 // must be higher than address(first sample. 446 // - A DMA block cannot be aligned with the end of the address space, that 447 // means a block cannot contain the address 0xFFFF. 448 #define I2S_AIFINPTRNEXT_PTR_W 32 449 #define I2S_AIFINPTRNEXT_PTR_M 0xFFFFFFFF 450 #define I2S_AIFINPTRNEXT_PTR_S 0 451 452 //***************************************************************************** 453 // 454 // Register: I2S_O_AIFINPTR 455 // 456 //***************************************************************************** 457 // Field: [31:0] PTR 458 // 459 // Value of the DMA input buffer pointer currently used by the DMA controller. 460 // Incremented by 1 (byte) or 2 (word) for each AHB access. 461 #define I2S_AIFINPTR_PTR_W 32 462 #define I2S_AIFINPTR_PTR_M 0xFFFFFFFF 463 #define I2S_AIFINPTR_PTR_S 0 464 465 //***************************************************************************** 466 // 467 // Register: I2S_O_AIFOUTPTRNEXT 468 // 469 //***************************************************************************** 470 // Field: [31:0] PTR 471 // 472 // Pointer to the first byte in the next DMA output buffer. 473 // 474 // The read value equals the last written value until the currently used DMA 475 // output buffer is completed, and then becomes null when the last written 476 // value is transferred to the DMA controller to start on the next buffer. This 477 // event is signalized by aif_dma_out_irq. 478 // 479 // At startup, the value must be written once before and once after configuring 480 // the DMA buffer size in AIFDMACFG. At this time, the first two samples will 481 // be fetched from memory. 482 // 483 // The next pointer must be written to this register while the DMA function 484 // uses the previously written pointer. If not written in time, 485 // IRQFLAGS.PTR_ERR will be raised and all output pins will be disabled. 486 // 487 // Note the following limitations: 488 // - Address space wrapping is not supported. That means address(last sample) 489 // must be higher than address(first sample. 490 // - A DMA block cannot be aligned with the end of the address space, that 491 // means a block cannot contain the address 0xFFFF. 492 #define I2S_AIFOUTPTRNEXT_PTR_W 32 493 #define I2S_AIFOUTPTRNEXT_PTR_M 0xFFFFFFFF 494 #define I2S_AIFOUTPTRNEXT_PTR_S 0 495 496 //***************************************************************************** 497 // 498 // Register: I2S_O_AIFOUTPTR 499 // 500 //***************************************************************************** 501 // Field: [31:0] PTR 502 // 503 // Value of the DMA output buffer pointer currently used by the DMA controller 504 // Incremented by 1 (byte) or 2 (word) for each AHB access. 505 #define I2S_AIFOUTPTR_PTR_W 32 506 #define I2S_AIFOUTPTR_PTR_M 0xFFFFFFFF 507 #define I2S_AIFOUTPTR_PTR_S 0 508 509 //***************************************************************************** 510 // 511 // Register: I2S_O_STMPCTL 512 // 513 //***************************************************************************** 514 // Field: [2] OUT_RDY 515 // 516 // Low until the output pins are ready to be started by the samplestamp 517 // generator. When started (that is STMPOUTTRIG equals the WCLK counter) the 518 // bit goes back low. 519 #define I2S_STMPCTL_OUT_RDY 0x00000004 520 #define I2S_STMPCTL_OUT_RDY_BITN 2 521 #define I2S_STMPCTL_OUT_RDY_M 0x00000004 522 #define I2S_STMPCTL_OUT_RDY_S 2 523 524 // Field: [1] IN_RDY 525 // 526 // Low until the input pins are ready to be started by the samplestamp 527 // generator. When started (that is STMPINTRIG equals the WCLK counter) the bit 528 // goes back low. 529 #define I2S_STMPCTL_IN_RDY 0x00000002 530 #define I2S_STMPCTL_IN_RDY_BITN 1 531 #define I2S_STMPCTL_IN_RDY_M 0x00000002 532 #define I2S_STMPCTL_IN_RDY_S 1 533 534 // Field: [0] STMP_EN 535 // 536 // Enables the samplestamp generator. The samplestamp generator must only be 537 // enabled after it has been properly configured. 538 // When cleared, all samplestamp generator counters and capture values are 539 // cleared. 540 #define I2S_STMPCTL_STMP_EN 0x00000001 541 #define I2S_STMPCTL_STMP_EN_BITN 0 542 #define I2S_STMPCTL_STMP_EN_M 0x00000001 543 #define I2S_STMPCTL_STMP_EN_S 0 544 545 //***************************************************************************** 546 // 547 // Register: I2S_O_STMPXCNTCAPT0 548 // 549 //***************************************************************************** 550 // Field: [15:0] CAPT_VALUE 551 // 552 // The value of the samplestamp XOSC counter (STMPXCNT.CURR_VALUE) last time an 553 // event was pulsed (event source selected in [EVENT.I2SSTMPSEL0.EV] for 554 // channel 0). This number corresponds to the number of 24 MHz clock cycles 555 // since the last positive edge of the selected WCLK. 556 // The value is cleared when STMPCTL.STMP_EN = 0. 557 // Note: Due to buffering and synchronization, WCLK is delayed by a small 558 // number of BCLK periods and clk periods. 559 // Note: When calculating the fractional part of the sample stamp, STMPXPER may 560 // be less than this bit field. 561 #define I2S_STMPXCNTCAPT0_CAPT_VALUE_W 16 562 #define I2S_STMPXCNTCAPT0_CAPT_VALUE_M 0x0000FFFF 563 #define I2S_STMPXCNTCAPT0_CAPT_VALUE_S 0 564 565 //***************************************************************************** 566 // 567 // Register: I2S_O_STMPXPER 568 // 569 //***************************************************************************** 570 // Field: [15:0] VALUE 571 // 572 // The number of 24 MHz clock cycles in the previous WCLK period (that is - 573 // the next value of the XOSC counter at the positive WCLK edge, had it not 574 // been reset to 0). 575 // The value is cleared when STMPCTL.STMP_EN = 0. 576 #define I2S_STMPXPER_VALUE_W 16 577 #define I2S_STMPXPER_VALUE_M 0x0000FFFF 578 #define I2S_STMPXPER_VALUE_S 0 579 580 //***************************************************************************** 581 // 582 // Register: I2S_O_STMPWCNTCAPT0 583 // 584 //***************************************************************************** 585 // Field: [15:0] CAPT_VALUE 586 // 587 // The value of the samplestamp WCLK counter (STMPWCNT.CURR_VALUE) last time an 588 // event was pulsed (event source selected in EVENT:I2SSTMPSEL0.EV for channel 589 // 0). This number corresponds to the number of positive WCLK edges since the 590 // samplestamp generator was enabled (not taking modification through 591 // STMPWADD/STMPWSET into account). 592 // The value is cleared when STMPCTL.STMP_EN = 0. 593 #define I2S_STMPWCNTCAPT0_CAPT_VALUE_W 16 594 #define I2S_STMPWCNTCAPT0_CAPT_VALUE_M 0x0000FFFF 595 #define I2S_STMPWCNTCAPT0_CAPT_VALUE_S 0 596 597 //***************************************************************************** 598 // 599 // Register: I2S_O_STMPWPER 600 // 601 //***************************************************************************** 602 // Field: [15:0] VALUE 603 // 604 // Used to define when STMPWCNT is to be reset so number of WCLK edges are 605 // found for the size of the sample buffer. This is thus a modulo value for the 606 // WCLK counter. This number must correspond to the size of the sample buffer 607 // used by the system (that is the index of the last sample plus 1). 608 #define I2S_STMPWPER_VALUE_W 16 609 #define I2S_STMPWPER_VALUE_M 0x0000FFFF 610 #define I2S_STMPWPER_VALUE_S 0 611 612 //***************************************************************************** 613 // 614 // Register: I2S_O_STMPINTRIG 615 // 616 //***************************************************************************** 617 // Field: [15:0] IN_START_WCNT 618 // 619 // Compare value used to start the incoming audio streams. 620 // This bit field shall equal the WCLK counter value during the WCLK period in 621 // which the first input word(s) are sampled and stored to memory (that is the 622 // sample at the start of the very first DMA input buffer). 623 // 624 // The value of this register takes effect when the following conditions are 625 // met: 626 // - One or more pins are configured as inputs in AIFDIRCFG. 627 // - AIFDMACFG has been configured for the correct buffer size, and at least 32 628 // BCLK cycle ticks have happened. 629 // 630 // Note: To avoid false triggers, this bit field should be set higher than 631 // STMPWPER.VALUE. 632 #define I2S_STMPINTRIG_IN_START_WCNT_W 16 633 #define I2S_STMPINTRIG_IN_START_WCNT_M 0x0000FFFF 634 #define I2S_STMPINTRIG_IN_START_WCNT_S 0 635 636 //***************************************************************************** 637 // 638 // Register: I2S_O_STMPOUTTRIG 639 // 640 //***************************************************************************** 641 // Field: [15:0] OUT_START_WCNT 642 // 643 // Compare value used to start the outgoing audio streams. 644 // 645 // This bit field must equal the WCLK counter value during the WCLK period in 646 // which the first output word(s) read from memory are clocked out (that is the 647 // sample at the start of the very first DMA output buffer). 648 // 649 // The value of this register takes effect when the following conditions are 650 // met: 651 // - One or more pins are configured as outputs in AIFDIRCFG. 652 // - AIFDMACFG has been configured for the correct buffer size, and 32 BCLK 653 // cycle ticks have happened. 654 // - 2 samples have been preloaded from memory (examine the AIFOUTPTR register 655 // if necessary). 656 // Note: The memory read access is only performed when required, that is 657 // channels 0/1 must be selected in AIFWMASK0/AIFWMASK1. 658 // 659 // Note: To avoid false triggers, this bit field should be set higher than 660 // STMPWPER.VALUE. 661 #define I2S_STMPOUTTRIG_OUT_START_WCNT_W 16 662 #define I2S_STMPOUTTRIG_OUT_START_WCNT_M 0x0000FFFF 663 #define I2S_STMPOUTTRIG_OUT_START_WCNT_S 0 664 665 //***************************************************************************** 666 // 667 // Register: I2S_O_STMPWSET 668 // 669 //***************************************************************************** 670 // Field: [15:0] VALUE 671 // 672 // WCLK counter modification: Sets the running WCLK counter equal to the 673 // written value. 674 #define I2S_STMPWSET_VALUE_W 16 675 #define I2S_STMPWSET_VALUE_M 0x0000FFFF 676 #define I2S_STMPWSET_VALUE_S 0 677 678 //***************************************************************************** 679 // 680 // Register: I2S_O_STMPWADD 681 // 682 //***************************************************************************** 683 // Field: [15:0] VALUE_INC 684 // 685 // WCLK counter modification: Adds the written value to the running WCLK 686 // counter. If a positive edge of WCLK occurs at the same time as the 687 // operation, this will be taken into account. 688 // To add a negative value, write "STMPWPER.VALUE - value". 689 // 690 #define I2S_STMPWADD_VALUE_INC_W 16 691 #define I2S_STMPWADD_VALUE_INC_M 0x0000FFFF 692 #define I2S_STMPWADD_VALUE_INC_S 0 693 694 //***************************************************************************** 695 // 696 // Register: I2S_O_STMPXPERMIN 697 // 698 //***************************************************************************** 699 // Field: [15:0] VALUE 700 // 701 // Each time STMPXPER is updated, the value is also loaded into this register, 702 // provided that the value is smaller than the current value in this register. 703 // When written, the register is reset to 0xFFFF (65535), regardless of the 704 // value written. 705 // The minimum value can be used to detect extra WCLK pulses (this registers 706 // value will be significantly smaller than STMPXPER.VALUE). 707 #define I2S_STMPXPERMIN_VALUE_W 16 708 #define I2S_STMPXPERMIN_VALUE_M 0x0000FFFF 709 #define I2S_STMPXPERMIN_VALUE_S 0 710 711 //***************************************************************************** 712 // 713 // Register: I2S_O_STMPWCNT 714 // 715 //***************************************************************************** 716 // Field: [15:0] CURR_VALUE 717 // 718 // Current value of the WCLK counter 719 #define I2S_STMPWCNT_CURR_VALUE_W 16 720 #define I2S_STMPWCNT_CURR_VALUE_M 0x0000FFFF 721 #define I2S_STMPWCNT_CURR_VALUE_S 0 722 723 //***************************************************************************** 724 // 725 // Register: I2S_O_STMPXCNT 726 // 727 //***************************************************************************** 728 // Field: [15:0] CURR_VALUE 729 // 730 // Current value of the XOSC counter, latched when reading STMPWCNT. 731 #define I2S_STMPXCNT_CURR_VALUE_W 16 732 #define I2S_STMPXCNT_CURR_VALUE_M 0x0000FFFF 733 #define I2S_STMPXCNT_CURR_VALUE_S 0 734 735 //***************************************************************************** 736 // 737 // Register: I2S_O_STMPXCNTCAPT1 738 // 739 //***************************************************************************** 740 // Field: [15:0] CAPT_VALUE 741 // 742 // Channel 1 is idle and can not be sampled from an external pulse as with 743 // Channel 0 STMPXCNTCAPT0 744 #define I2S_STMPXCNTCAPT1_CAPT_VALUE_W 16 745 #define I2S_STMPXCNTCAPT1_CAPT_VALUE_M 0x0000FFFF 746 #define I2S_STMPXCNTCAPT1_CAPT_VALUE_S 0 747 748 //***************************************************************************** 749 // 750 // Register: I2S_O_STMPWCNTCAPT1 751 // 752 //***************************************************************************** 753 // Field: [15:0] CAPT_VALUE 754 // 755 // Channel 1 is idle and can not be sampled from an external event as with 756 // Channel 0 STMPWCNTCAPT0 757 #define I2S_STMPWCNTCAPT1_CAPT_VALUE_W 16 758 #define I2S_STMPWCNTCAPT1_CAPT_VALUE_M 0x0000FFFF 759 #define I2S_STMPWCNTCAPT1_CAPT_VALUE_S 0 760 761 //***************************************************************************** 762 // 763 // Register: I2S_O_IRQMASK 764 // 765 //***************************************************************************** 766 // Field: [5] AIF_DMA_IN 767 // 768 // Defines the masks state for the interrupt of IRQFLAGS.AIF_DMA_IN 769 // 770 // 0: Disable 771 // 1: Enable 772 #define I2S_IRQMASK_AIF_DMA_IN 0x00000020 773 #define I2S_IRQMASK_AIF_DMA_IN_BITN 5 774 #define I2S_IRQMASK_AIF_DMA_IN_M 0x00000020 775 #define I2S_IRQMASK_AIF_DMA_IN_S 5 776 777 // Field: [4] AIF_DMA_OUT 778 // 779 // Defines the masks state for the interrupt of IRQFLAGS.AIF_DMA_OUT 780 // 781 // 0: Disable 782 // 1: Enable 783 #define I2S_IRQMASK_AIF_DMA_OUT 0x00000010 784 #define I2S_IRQMASK_AIF_DMA_OUT_BITN 4 785 #define I2S_IRQMASK_AIF_DMA_OUT_M 0x00000010 786 #define I2S_IRQMASK_AIF_DMA_OUT_S 4 787 788 // Field: [3] WCLK_TIMEOUT 789 // 790 // Defines the masks state for the interrupt of IRQFLAGS.WCLK_TIMEOUT 791 // 792 // 0: Disable 793 // 1: Enable 794 #define I2S_IRQMASK_WCLK_TIMEOUT 0x00000008 795 #define I2S_IRQMASK_WCLK_TIMEOUT_BITN 3 796 #define I2S_IRQMASK_WCLK_TIMEOUT_M 0x00000008 797 #define I2S_IRQMASK_WCLK_TIMEOUT_S 3 798 799 // Field: [2] BUS_ERR 800 // 801 // Defines the masks state for the interrupt of IRQFLAGS.BUS_ERR 802 // 803 // 0: Disable 804 // 1: Enable 805 #define I2S_IRQMASK_BUS_ERR 0x00000004 806 #define I2S_IRQMASK_BUS_ERR_BITN 2 807 #define I2S_IRQMASK_BUS_ERR_M 0x00000004 808 #define I2S_IRQMASK_BUS_ERR_S 2 809 810 // Field: [1] WCLK_ERR 811 // 812 // Defines the masks state for the interrupt of IRQFLAGS.WCLK_ERR 813 // 814 // 0: Disable 815 // 1: Enable 816 #define I2S_IRQMASK_WCLK_ERR 0x00000002 817 #define I2S_IRQMASK_WCLK_ERR_BITN 1 818 #define I2S_IRQMASK_WCLK_ERR_M 0x00000002 819 #define I2S_IRQMASK_WCLK_ERR_S 1 820 821 // Field: [0] PTR_ERR 822 // 823 // Defines the masks state for the interrupt of IRQFLAGS.PTR_ERR 824 // 825 // 0: Disable 826 // 1: Enable 827 #define I2S_IRQMASK_PTR_ERR 0x00000001 828 #define I2S_IRQMASK_PTR_ERR_BITN 0 829 #define I2S_IRQMASK_PTR_ERR_M 0x00000001 830 #define I2S_IRQMASK_PTR_ERR_S 0 831 832 //***************************************************************************** 833 // 834 // Register: I2S_O_IRQFLAGS 835 // 836 //***************************************************************************** 837 // Field: [5] AIF_DMA_IN 838 // 839 // Set when condition for this bit field event occurs (auto cleared when input 840 // pointer is updated - AIFINPTR), see description of AIFINPTR register 841 #define I2S_IRQFLAGS_AIF_DMA_IN 0x00000020 842 #define I2S_IRQFLAGS_AIF_DMA_IN_BITN 5 843 #define I2S_IRQFLAGS_AIF_DMA_IN_M 0x00000020 844 #define I2S_IRQFLAGS_AIF_DMA_IN_S 5 845 846 // Field: [4] AIF_DMA_OUT 847 // 848 // Set when condition for this bit field event occurs (auto cleared when output 849 // pointer is updated - AIFOUTPTR), see description of AIFOUTPTR register for 850 // details 851 #define I2S_IRQFLAGS_AIF_DMA_OUT 0x00000010 852 #define I2S_IRQFLAGS_AIF_DMA_OUT_BITN 4 853 #define I2S_IRQFLAGS_AIF_DMA_OUT_M 0x00000010 854 #define I2S_IRQFLAGS_AIF_DMA_OUT_S 4 855 856 // Field: [3] WCLK_TIMEOUT 857 // 858 // Set when the sample stamp generator does not detect a positive WCLK edge for 859 // 65535 clk periods. This signalizes that the internal or external BCLK and 860 // WCLK generator source has been disabled. 861 // 862 // The bit is sticky and may only be cleared by software (by writing '1' to 863 // IRQCLR.WCLK_TIMEOUT). 864 #define I2S_IRQFLAGS_WCLK_TIMEOUT 0x00000008 865 #define I2S_IRQFLAGS_WCLK_TIMEOUT_BITN 3 866 #define I2S_IRQFLAGS_WCLK_TIMEOUT_M 0x00000008 867 #define I2S_IRQFLAGS_WCLK_TIMEOUT_S 3 868 869 // Field: [2] BUS_ERR 870 // 871 // Set when a DMA operation is not completed in time (that is audio output 872 // buffer underflow, or audio input buffer overflow). 873 // This error requires a complete restart since word synchronization has been 874 // lost. The bit is sticky and may only be cleared by software (by writing '1' 875 // to IRQCLR.BUS_ERR). 876 // 877 // Note that DMA initiated transactions to illegal addresses will not trigger 878 // an interrupt. The response to such transactions is undefined. 879 #define I2S_IRQFLAGS_BUS_ERR 0x00000004 880 #define I2S_IRQFLAGS_BUS_ERR_BITN 2 881 #define I2S_IRQFLAGS_BUS_ERR_M 0x00000004 882 #define I2S_IRQFLAGS_BUS_ERR_S 2 883 884 // Field: [1] WCLK_ERR 885 // 886 // Set when: 887 // - An unexpected WCLK edge occurs during the data delay period of a phase. 888 // Note unexpected WCLK edges during the word and idle periods of the phase are 889 // not detected. 890 // - In dual-phase mode, when two WCLK edges are less than 4 BCLK cycles 891 // apart. 892 // - In single-phase mode, when a WCLK pulse occurs before the last channel. 893 // This error requires a complete restart since word synchronization has been 894 // lost. The bit is sticky and may only be cleared by software (by writing '1' 895 // to IRQCLR.WCLK_ERR). 896 #define I2S_IRQFLAGS_WCLK_ERR 0x00000002 897 #define I2S_IRQFLAGS_WCLK_ERR_BITN 1 898 #define I2S_IRQFLAGS_WCLK_ERR_M 0x00000002 899 #define I2S_IRQFLAGS_WCLK_ERR_S 1 900 901 // Field: [0] PTR_ERR 902 // 903 // Set when AIFINPTRNEXT or AIFOUTPTRNEXT has not been loaded with the next 904 // block address in time. 905 // This error requires a complete restart since word synchronization has been 906 // lost. The bit is sticky and may only be cleared by software (by writing '1' 907 // to IRQCLR.PTR_ERR). 908 #define I2S_IRQFLAGS_PTR_ERR 0x00000001 909 #define I2S_IRQFLAGS_PTR_ERR_BITN 0 910 #define I2S_IRQFLAGS_PTR_ERR_M 0x00000001 911 #define I2S_IRQFLAGS_PTR_ERR_S 0 912 913 //***************************************************************************** 914 // 915 // Register: I2S_O_IRQSET 916 // 917 //***************************************************************************** 918 // Field: [5] AIF_DMA_IN 919 // 920 // 1: Sets the interrupt of IRQFLAGS.AIF_DMA_IN (unless a auto clear criteria 921 // was given at the same time, in which the set will be ignored) 922 #define I2S_IRQSET_AIF_DMA_IN 0x00000020 923 #define I2S_IRQSET_AIF_DMA_IN_BITN 5 924 #define I2S_IRQSET_AIF_DMA_IN_M 0x00000020 925 #define I2S_IRQSET_AIF_DMA_IN_S 5 926 927 // Field: [4] AIF_DMA_OUT 928 // 929 // 1: Sets the interrupt of IRQFLAGS.AIF_DMA_OUT (unless a auto clear criteria 930 // was given at the same time, in which the set will be ignored) 931 #define I2S_IRQSET_AIF_DMA_OUT 0x00000010 932 #define I2S_IRQSET_AIF_DMA_OUT_BITN 4 933 #define I2S_IRQSET_AIF_DMA_OUT_M 0x00000010 934 #define I2S_IRQSET_AIF_DMA_OUT_S 4 935 936 // Field: [3] WCLK_TIMEOUT 937 // 938 // 1: Sets the interrupt of IRQFLAGS.WCLK_TIMEOUT 939 #define I2S_IRQSET_WCLK_TIMEOUT 0x00000008 940 #define I2S_IRQSET_WCLK_TIMEOUT_BITN 3 941 #define I2S_IRQSET_WCLK_TIMEOUT_M 0x00000008 942 #define I2S_IRQSET_WCLK_TIMEOUT_S 3 943 944 // Field: [2] BUS_ERR 945 // 946 // 1: Sets the interrupt of IRQFLAGS.BUS_ERR 947 #define I2S_IRQSET_BUS_ERR 0x00000004 948 #define I2S_IRQSET_BUS_ERR_BITN 2 949 #define I2S_IRQSET_BUS_ERR_M 0x00000004 950 #define I2S_IRQSET_BUS_ERR_S 2 951 952 // Field: [1] WCLK_ERR 953 // 954 // 1: Sets the interrupt of IRQFLAGS.WCLK_ERR 955 #define I2S_IRQSET_WCLK_ERR 0x00000002 956 #define I2S_IRQSET_WCLK_ERR_BITN 1 957 #define I2S_IRQSET_WCLK_ERR_M 0x00000002 958 #define I2S_IRQSET_WCLK_ERR_S 1 959 960 // Field: [0] PTR_ERR 961 // 962 // 1: Sets the interrupt of IRQFLAGS.PTR_ERR 963 #define I2S_IRQSET_PTR_ERR 0x00000001 964 #define I2S_IRQSET_PTR_ERR_BITN 0 965 #define I2S_IRQSET_PTR_ERR_M 0x00000001 966 #define I2S_IRQSET_PTR_ERR_S 0 967 968 //***************************************************************************** 969 // 970 // Register: I2S_O_IRQCLR 971 // 972 //***************************************************************************** 973 // Field: [5] AIF_DMA_IN 974 // 975 // 1: Clears the interrupt of IRQFLAGS.AIF_DMA_IN (unless a set criteria was 976 // given at the same time in which the clear will be ignored) 977 #define I2S_IRQCLR_AIF_DMA_IN 0x00000020 978 #define I2S_IRQCLR_AIF_DMA_IN_BITN 5 979 #define I2S_IRQCLR_AIF_DMA_IN_M 0x00000020 980 #define I2S_IRQCLR_AIF_DMA_IN_S 5 981 982 // Field: [4] AIF_DMA_OUT 983 // 984 // 1: Clears the interrupt of IRQFLAGS.AIF_DMA_OUT (unless a set criteria was 985 // given at the same time in which the clear will be ignored) 986 #define I2S_IRQCLR_AIF_DMA_OUT 0x00000010 987 #define I2S_IRQCLR_AIF_DMA_OUT_BITN 4 988 #define I2S_IRQCLR_AIF_DMA_OUT_M 0x00000010 989 #define I2S_IRQCLR_AIF_DMA_OUT_S 4 990 991 // Field: [3] WCLK_TIMEOUT 992 // 993 // 1: Clears the interrupt of IRQFLAGS.WCLK_TIMEOUT (unless a set criteria was 994 // given at the same time in which the clear will be ignored) 995 #define I2S_IRQCLR_WCLK_TIMEOUT 0x00000008 996 #define I2S_IRQCLR_WCLK_TIMEOUT_BITN 3 997 #define I2S_IRQCLR_WCLK_TIMEOUT_M 0x00000008 998 #define I2S_IRQCLR_WCLK_TIMEOUT_S 3 999 1000 // Field: [2] BUS_ERR 1001 // 1002 // 1: Clears the interrupt of IRQFLAGS.BUS_ERR (unless a set criteria was given 1003 // at the same time in which the clear will be ignored) 1004 #define I2S_IRQCLR_BUS_ERR 0x00000004 1005 #define I2S_IRQCLR_BUS_ERR_BITN 2 1006 #define I2S_IRQCLR_BUS_ERR_M 0x00000004 1007 #define I2S_IRQCLR_BUS_ERR_S 2 1008 1009 // Field: [1] WCLK_ERR 1010 // 1011 // 1: Clears the interrupt of IRQFLAGS.WCLK_ERR (unless a set criteria was 1012 // given at the same time in which the clear will be ignored) 1013 #define I2S_IRQCLR_WCLK_ERR 0x00000002 1014 #define I2S_IRQCLR_WCLK_ERR_BITN 1 1015 #define I2S_IRQCLR_WCLK_ERR_M 0x00000002 1016 #define I2S_IRQCLR_WCLK_ERR_S 1 1017 1018 // Field: [0] PTR_ERR 1019 // 1020 // 1: Clears the interrupt of IRQFLAGS.PTR_ERR (unless a set criteria was given 1021 // at the same time in which the clear will be ignored) 1022 #define I2S_IRQCLR_PTR_ERR 0x00000001 1023 #define I2S_IRQCLR_PTR_ERR_BITN 0 1024 #define I2S_IRQCLR_PTR_ERR_M 0x00000001 1025 #define I2S_IRQCLR_PTR_ERR_S 0 1026 1027 1028 #endif // __I2S__ 1029