1 /****************************************************************************** 2 * Filename: hw_prcm_h 3 * Revised: 2015-11-12 13:07:02 +0100 (Thu, 12 Nov 2015) 4 * Revision: 45056 5 * 6 * Copyright (c) 2015, Texas Instruments Incorporated 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions are met: 11 * 12 * 1) Redistributions of source code must retain the above copyright notice, 13 * this list of conditions and the following disclaimer. 14 * 15 * 2) Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 19 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may 20 * be used to endorse or promote products derived from this software without 21 * specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 * 35 ******************************************************************************/ 36 37 #ifndef __HW_PRCM_H__ 38 #define __HW_PRCM_H__ 39 40 //***************************************************************************** 41 // 42 // This section defines the register offsets of 43 // PRCM component 44 // 45 //***************************************************************************** 46 // Infrastructure Clock Division Factor For Run Mode 47 #define PRCM_O_INFRCLKDIVR 0x00000000 48 49 // Infrastructure Clock Division Factor For Sleep Mode 50 #define PRCM_O_INFRCLKDIVS 0x00000004 51 52 // Infrastructure Clock Division Factor For DeepSleep Mode 53 #define PRCM_O_INFRCLKDIVDS 0x00000008 54 55 // MCU Voltage Domain Control 56 #define PRCM_O_VDCTL 0x0000000C 57 58 // Clock Load Control 59 #define PRCM_O_CLKLOADCTL 0x00000028 60 61 // RFC Clock Gate 62 #define PRCM_O_RFCCLKG 0x0000002C 63 64 // VIMS Clock Gate 65 #define PRCM_O_VIMSCLKG 0x00000030 66 67 // TRNG, CRYPTO And UDMA Clock Gate For Run Mode 68 #define PRCM_O_SECDMACLKGR 0x0000003C 69 70 // TRNG, CRYPTO And UDMA Clock Gate For Sleep Mode 71 #define PRCM_O_SECDMACLKGS 0x00000040 72 73 // TRNG, CRYPTO And UDMA Clock Gate For Deep Sleep Mode 74 #define PRCM_O_SECDMACLKGDS 0x00000044 75 76 // GPIO Clock Gate For Run Mode 77 #define PRCM_O_GPIOCLKGR 0x00000048 78 79 // GPIO Clock Gate For Sleep Mode 80 #define PRCM_O_GPIOCLKGS 0x0000004C 81 82 // GPIO Clock Gate For Deep Sleep Mode 83 #define PRCM_O_GPIOCLKGDS 0x00000050 84 85 // GPT Clock Gate For Run Mode 86 #define PRCM_O_GPTCLKGR 0x00000054 87 88 // GPT Clock Gate For Sleep Mode 89 #define PRCM_O_GPTCLKGS 0x00000058 90 91 // GPT Clock Gate For Deep Sleep Mode 92 #define PRCM_O_GPTCLKGDS 0x0000005C 93 94 // I2C Clock Gate For Run Mode 95 #define PRCM_O_I2CCLKGR 0x00000060 96 97 // I2C Clock Gate For Sleep Mode 98 #define PRCM_O_I2CCLKGS 0x00000064 99 100 // I2C Clock Gate For Deep Sleep Mode 101 #define PRCM_O_I2CCLKGDS 0x00000068 102 103 // UART Clock Gate For Run Mode 104 #define PRCM_O_UARTCLKGR 0x0000006C 105 106 // UART Clock Gate For Sleep Mode 107 #define PRCM_O_UARTCLKGS 0x00000070 108 109 // UART Clock Gate For Deep Sleep Mode 110 #define PRCM_O_UARTCLKGDS 0x00000074 111 112 // SSI Clock Gate For Run Mode 113 #define PRCM_O_SSICLKGR 0x00000078 114 115 // SSI Clock Gate For Sleep Mode 116 #define PRCM_O_SSICLKGS 0x0000007C 117 118 // SSI Clock Gate For Deep Sleep Mode 119 #define PRCM_O_SSICLKGDS 0x00000080 120 121 // I2S Clock Gate For Run Mode 122 #define PRCM_O_I2SCLKGR 0x00000084 123 124 // I2S Clock Gate For Sleep Mode 125 #define PRCM_O_I2SCLKGS 0x00000088 126 127 // I2S Clock Gate For Deep Sleep Mode 128 #define PRCM_O_I2SCLKGDS 0x0000008C 129 130 // Internal 131 #define PRCM_O_CPUCLKDIV 0x000000B8 132 133 // I2S Clock Control 134 #define PRCM_O_I2SBCLKSEL 0x000000C8 135 136 // GPT Scalar 137 #define PRCM_O_GPTCLKDIV 0x000000CC 138 139 // I2S Clock Control 140 #define PRCM_O_I2SCLKCTL 0x000000D0 141 142 // MCLK Division Ratio 143 #define PRCM_O_I2SMCLKDIV 0x000000D4 144 145 // BCLK Division Ratio 146 #define PRCM_O_I2SBCLKDIV 0x000000D8 147 148 // WCLK Division Ratio 149 #define PRCM_O_I2SWCLKDIV 0x000000DC 150 151 // SW Initiated Resets 152 #define PRCM_O_SWRESET 0x0000010C 153 154 // WARM Reset Control And Status 155 #define PRCM_O_WARMRESET 0x00000110 156 157 // Power Domain Control 158 #define PRCM_O_PDCTL0 0x0000012C 159 160 // RFC Power Domain Control 161 #define PRCM_O_PDCTL0RFC 0x00000130 162 163 // SERIAL Power Domain Control 164 #define PRCM_O_PDCTL0SERIAL 0x00000134 165 166 // PERIPH Power Domain Control 167 #define PRCM_O_PDCTL0PERIPH 0x00000138 168 169 // Power Domain Status 170 #define PRCM_O_PDSTAT0 0x00000140 171 172 // RFC Power Domain Status 173 #define PRCM_O_PDSTAT0RFC 0x00000144 174 175 // SERIAL Power Domain Status 176 #define PRCM_O_PDSTAT0SERIAL 0x00000148 177 178 // PERIPH Power Domain Status 179 #define PRCM_O_PDSTAT0PERIPH 0x0000014C 180 181 // Power Domain Control 182 #define PRCM_O_PDCTL1 0x0000017C 183 184 // CPU Power Domain Control 185 #define PRCM_O_PDCTL1CPU 0x00000184 186 187 // RFC Power Domain Control 188 #define PRCM_O_PDCTL1RFC 0x00000188 189 190 // VIMS Power Domain Control 191 #define PRCM_O_PDCTL1VIMS 0x0000018C 192 193 // Power Domain Status 194 #define PRCM_O_PDSTAT1 0x00000194 195 196 // BUS Power Domain Status 197 #define PRCM_O_PDSTAT1BUS 0x00000198 198 199 // RFC Power Domain Status 200 #define PRCM_O_PDSTAT1RFC 0x0000019C 201 202 // CPU Power Domain Status 203 #define PRCM_O_PDSTAT1CPU 0x000001A0 204 205 // VIMS Power Domain Status 206 #define PRCM_O_PDSTAT1VIMS 0x000001A4 207 208 // Selected RFC Mode 209 #define PRCM_O_RFCMODESEL 0x000001D0 210 211 // Memory Retention Control 212 #define PRCM_O_RAMRETEN 0x00000224 213 214 //***************************************************************************** 215 // 216 // Register: PRCM_O_INFRCLKDIVR 217 // 218 //***************************************************************************** 219 // Field: [1:0] RATIO 220 // 221 // Division rate for clocks driving modules in the MCU_AON domain when system 222 // CPU is in run mode. Division ratio affects both infrastructure clock and 223 // perbusull clock. 224 // ENUMs: 225 // DIV32 Divide by 32 226 // DIV8 Divide by 8 227 // DIV2 Divide by 2 228 // DIV1 Divide by 1 229 #define PRCM_INFRCLKDIVR_RATIO_W 2 230 #define PRCM_INFRCLKDIVR_RATIO_M 0x00000003 231 #define PRCM_INFRCLKDIVR_RATIO_S 0 232 #define PRCM_INFRCLKDIVR_RATIO_DIV32 0x00000003 233 #define PRCM_INFRCLKDIVR_RATIO_DIV8 0x00000002 234 #define PRCM_INFRCLKDIVR_RATIO_DIV2 0x00000001 235 #define PRCM_INFRCLKDIVR_RATIO_DIV1 0x00000000 236 237 //***************************************************************************** 238 // 239 // Register: PRCM_O_INFRCLKDIVS 240 // 241 //***************************************************************************** 242 // Field: [1:0] RATIO 243 // 244 // Division rate for clocks driving modules in the MCU_AON domain when system 245 // CPU is in sleep mode. Division ratio affects both infrastructure clock and 246 // perbusull clock. 247 // ENUMs: 248 // DIV32 Divide by 32 249 // DIV8 Divide by 8 250 // DIV2 Divide by 2 251 // DIV1 Divide by 1 252 #define PRCM_INFRCLKDIVS_RATIO_W 2 253 #define PRCM_INFRCLKDIVS_RATIO_M 0x00000003 254 #define PRCM_INFRCLKDIVS_RATIO_S 0 255 #define PRCM_INFRCLKDIVS_RATIO_DIV32 0x00000003 256 #define PRCM_INFRCLKDIVS_RATIO_DIV8 0x00000002 257 #define PRCM_INFRCLKDIVS_RATIO_DIV2 0x00000001 258 #define PRCM_INFRCLKDIVS_RATIO_DIV1 0x00000000 259 260 //***************************************************************************** 261 // 262 // Register: PRCM_O_INFRCLKDIVDS 263 // 264 //***************************************************************************** 265 // Field: [1:0] RATIO 266 // 267 // Division rate for clocks driving modules in the MCU_AON domain when system 268 // CPU is in seepsleep mode. Division ratio affects both infrastructure clock 269 // and perbusull clock. 270 // ENUMs: 271 // DIV32 Divide by 32 272 // DIV8 Divide by 8 273 // DIV2 Divide by 2 274 // DIV1 Divide by 1 275 #define PRCM_INFRCLKDIVDS_RATIO_W 2 276 #define PRCM_INFRCLKDIVDS_RATIO_M 0x00000003 277 #define PRCM_INFRCLKDIVDS_RATIO_S 0 278 #define PRCM_INFRCLKDIVDS_RATIO_DIV32 0x00000003 279 #define PRCM_INFRCLKDIVDS_RATIO_DIV8 0x00000002 280 #define PRCM_INFRCLKDIVDS_RATIO_DIV2 0x00000001 281 #define PRCM_INFRCLKDIVDS_RATIO_DIV1 0x00000000 282 283 //***************************************************************************** 284 // 285 // Register: PRCM_O_VDCTL 286 // 287 //***************************************************************************** 288 // Field: [2] MCU_VD 289 // 290 // Request WUC to power down the MCU voltage domain 291 // 292 // 0: No request 293 // 1: Assert request when possible. An asserted power down request will result 294 // in a boot of the MCU system when powered up again. 295 // 296 // The bit will have no effect before the following requirements are met: 297 // 1. PDCTL1.CPU_ON = 0 298 // 2. PDCTL1.VIMS_MODE = 0 299 // 3. SECDMACLKGDS.DMA_CLK_EN = 0 (Note: Setting must be loaded with 300 // CLKLOADCTL.LOAD) 301 // 4. SECDMACLKGDS.CRYPTO_CLK_EN = 0 (Note: Setting must be loaded with 302 // CLKLOADCTL.LOAD) 303 // 5. RFC do no request access to BUS 304 // 6. System CPU in deepsleep 305 #define PRCM_VDCTL_MCU_VD 0x00000004 306 #define PRCM_VDCTL_MCU_VD_BITN 2 307 #define PRCM_VDCTL_MCU_VD_M 0x00000004 308 #define PRCM_VDCTL_MCU_VD_S 2 309 310 // Field: [0] ULDO 311 // 312 // Request WUC to switch to uLDO. 313 // 314 // 0: No request 315 // 1: Assert request when possible 316 // 317 // The bit will have no effect before the following requirements are met: 318 // 1. PDCTL1.CPU_ON = 0 319 // 2. PDCTL1.VIMS_MODE = 0 320 // 3. SECDMACLKGDS.DMA_CLK_EN = 0 (Note: Setting must be loaded with 321 // CLKLOADCTL.LOAD) 322 // 4. SECDMACLKGDS.CRYPTO_CLK_EN = 0 (Note: Setting must be loaded with 323 // CLKLOADCTL.LOAD) 324 // 5. RFC do no request access to BUS 325 // 6. System CPU in deepsleep 326 #define PRCM_VDCTL_ULDO 0x00000001 327 #define PRCM_VDCTL_ULDO_BITN 0 328 #define PRCM_VDCTL_ULDO_M 0x00000001 329 #define PRCM_VDCTL_ULDO_S 0 330 331 //***************************************************************************** 332 // 333 // Register: PRCM_O_CLKLOADCTL 334 // 335 //***************************************************************************** 336 // Field: [1] LOAD_DONE 337 // 338 // Status of LOAD. 339 // Will be cleared to 0 when any of the registers requiring a LOAD is written 340 // to, and be set to 1 when a LOAD is done. 341 // Note that writing no change to a register will result in the LOAD_DONE being 342 // cleared. 343 // 344 // 0 : One or more registers have been write accessed after last LOAD 345 // 1 : No registers are write accessed after last LOAD 346 #define PRCM_CLKLOADCTL_LOAD_DONE 0x00000002 347 #define PRCM_CLKLOADCTL_LOAD_DONE_BITN 1 348 #define PRCM_CLKLOADCTL_LOAD_DONE_M 0x00000002 349 #define PRCM_CLKLOADCTL_LOAD_DONE_S 1 350 351 // Field: [0] LOAD 352 // 353 // 0: No action 354 // 1: Load settings to CLKCTRL. Bit is HW cleared. 355 // 356 // Multiple changes to settings may be done before LOAD is written once so all 357 // changes takes place at the same time. LOAD can also be done after single 358 // setting updates. 359 // 360 // Registers that needs to be followed by LOAD before settings being applied 361 // are: 362 // - RFCCLKG 363 // - VIMSCLKG 364 // - SECDMACLKGR 365 // - SECDMACLKGS 366 // - SECDMACLKGDS 367 // - GPIOCLKGR 368 // - GPIOCLKGS 369 // - GPIOCLKGDS 370 // - GPTCLKGR 371 // - GPTCLKGS 372 // - GPTCLKGDS 373 // - GPTCLKDIV 374 // - I2CCLKGR 375 // - I2CCLKGS 376 // - I2CCLKGDS 377 // - SSICLKGR 378 // - SSICLKGS 379 // - SSICLKGDS 380 // - UARTCLKGR 381 // - UARTCLKGS 382 // - UARTCLKGDS 383 // - I2SCLKGR 384 // - I2SCLKGS 385 // - I2SCLKGDS 386 // - I2SBCLKSEL 387 // - I2SCLKCTL 388 // - I2SMCLKDIV 389 // - I2SBCLKDIV 390 // - I2SWCLKDIV 391 #define PRCM_CLKLOADCTL_LOAD 0x00000001 392 #define PRCM_CLKLOADCTL_LOAD_BITN 0 393 #define PRCM_CLKLOADCTL_LOAD_M 0x00000001 394 #define PRCM_CLKLOADCTL_LOAD_S 0 395 396 //***************************************************************************** 397 // 398 // Register: PRCM_O_RFCCLKG 399 // 400 //***************************************************************************** 401 // Field: [0] CLK_EN 402 // 403 // 404 // 0: Disable clock 405 // 1: Enable clock if RFC power domain is on 406 // 407 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 408 #define PRCM_RFCCLKG_CLK_EN 0x00000001 409 #define PRCM_RFCCLKG_CLK_EN_BITN 0 410 #define PRCM_RFCCLKG_CLK_EN_M 0x00000001 411 #define PRCM_RFCCLKG_CLK_EN_S 0 412 413 //***************************************************************************** 414 // 415 // Register: PRCM_O_VIMSCLKG 416 // 417 //***************************************************************************** 418 // Field: [1:0] CLK_EN 419 // 420 // 00: Disable clock 421 // 01: Disable clock when SYSBUS clock is disabled 422 // 11: Enable clock 423 // 424 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 425 #define PRCM_VIMSCLKG_CLK_EN_W 2 426 #define PRCM_VIMSCLKG_CLK_EN_M 0x00000003 427 #define PRCM_VIMSCLKG_CLK_EN_S 0 428 429 //***************************************************************************** 430 // 431 // Register: PRCM_O_SECDMACLKGR 432 // 433 //***************************************************************************** 434 // Field: [8] DMA_CLK_EN 435 // 436 // 437 // 0: Disable clock 438 // 1: Enable clock 439 // 440 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 441 #define PRCM_SECDMACLKGR_DMA_CLK_EN 0x00000100 442 #define PRCM_SECDMACLKGR_DMA_CLK_EN_BITN 8 443 #define PRCM_SECDMACLKGR_DMA_CLK_EN_M 0x00000100 444 #define PRCM_SECDMACLKGR_DMA_CLK_EN_S 8 445 446 // Field: [1] TRNG_CLK_EN 447 // 448 // 449 // 0: Disable clock 450 // 1: Enable clock 451 // 452 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 453 #define PRCM_SECDMACLKGR_TRNG_CLK_EN 0x00000002 454 #define PRCM_SECDMACLKGR_TRNG_CLK_EN_BITN 1 455 #define PRCM_SECDMACLKGR_TRNG_CLK_EN_M 0x00000002 456 #define PRCM_SECDMACLKGR_TRNG_CLK_EN_S 1 457 458 // Field: [0] CRYPTO_CLK_EN 459 // 460 // 461 // 0: Disable clock 462 // 1: Enable clock 463 // 464 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 465 #define PRCM_SECDMACLKGR_CRYPTO_CLK_EN 0x00000001 466 #define PRCM_SECDMACLKGR_CRYPTO_CLK_EN_BITN 0 467 #define PRCM_SECDMACLKGR_CRYPTO_CLK_EN_M 0x00000001 468 #define PRCM_SECDMACLKGR_CRYPTO_CLK_EN_S 0 469 470 //***************************************************************************** 471 // 472 // Register: PRCM_O_SECDMACLKGS 473 // 474 //***************************************************************************** 475 // Field: [8] DMA_CLK_EN 476 // 477 // 478 // 0: Disable clock 479 // 1: Enable clock 480 // 481 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 482 #define PRCM_SECDMACLKGS_DMA_CLK_EN 0x00000100 483 #define PRCM_SECDMACLKGS_DMA_CLK_EN_BITN 8 484 #define PRCM_SECDMACLKGS_DMA_CLK_EN_M 0x00000100 485 #define PRCM_SECDMACLKGS_DMA_CLK_EN_S 8 486 487 // Field: [1] TRNG_CLK_EN 488 // 489 // 490 // 0: Disable clock 491 // 1: Enable clock 492 // 493 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 494 #define PRCM_SECDMACLKGS_TRNG_CLK_EN 0x00000002 495 #define PRCM_SECDMACLKGS_TRNG_CLK_EN_BITN 1 496 #define PRCM_SECDMACLKGS_TRNG_CLK_EN_M 0x00000002 497 #define PRCM_SECDMACLKGS_TRNG_CLK_EN_S 1 498 499 // Field: [0] CRYPTO_CLK_EN 500 // 501 // 502 // 0: Disable clock 503 // 1: Enable clock 504 // 505 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 506 #define PRCM_SECDMACLKGS_CRYPTO_CLK_EN 0x00000001 507 #define PRCM_SECDMACLKGS_CRYPTO_CLK_EN_BITN 0 508 #define PRCM_SECDMACLKGS_CRYPTO_CLK_EN_M 0x00000001 509 #define PRCM_SECDMACLKGS_CRYPTO_CLK_EN_S 0 510 511 //***************************************************************************** 512 // 513 // Register: PRCM_O_SECDMACLKGDS 514 // 515 //***************************************************************************** 516 // Field: [8] DMA_CLK_EN 517 // 518 // 519 // 0: Disable clock 520 // 1: Enable clock 521 // 522 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 523 #define PRCM_SECDMACLKGDS_DMA_CLK_EN 0x00000100 524 #define PRCM_SECDMACLKGDS_DMA_CLK_EN_BITN 8 525 #define PRCM_SECDMACLKGDS_DMA_CLK_EN_M 0x00000100 526 #define PRCM_SECDMACLKGDS_DMA_CLK_EN_S 8 527 528 // Field: [1] TRNG_CLK_EN 529 // 530 // 531 // 0: Disable clock 532 // 1: Enable clock 533 // 534 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 535 #define PRCM_SECDMACLKGDS_TRNG_CLK_EN 0x00000002 536 #define PRCM_SECDMACLKGDS_TRNG_CLK_EN_BITN 1 537 #define PRCM_SECDMACLKGDS_TRNG_CLK_EN_M 0x00000002 538 #define PRCM_SECDMACLKGDS_TRNG_CLK_EN_S 1 539 540 // Field: [0] CRYPTO_CLK_EN 541 // 542 // 543 // 0: Disable clock 544 // 1: Enable clock 545 // 546 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 547 #define PRCM_SECDMACLKGDS_CRYPTO_CLK_EN 0x00000001 548 #define PRCM_SECDMACLKGDS_CRYPTO_CLK_EN_BITN 0 549 #define PRCM_SECDMACLKGDS_CRYPTO_CLK_EN_M 0x00000001 550 #define PRCM_SECDMACLKGDS_CRYPTO_CLK_EN_S 0 551 552 //***************************************************************************** 553 // 554 // Register: PRCM_O_GPIOCLKGR 555 // 556 //***************************************************************************** 557 // Field: [0] CLK_EN 558 // 559 // 560 // 0: Disable clock 561 // 1: Enable clock 562 // 563 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 564 #define PRCM_GPIOCLKGR_CLK_EN 0x00000001 565 #define PRCM_GPIOCLKGR_CLK_EN_BITN 0 566 #define PRCM_GPIOCLKGR_CLK_EN_M 0x00000001 567 #define PRCM_GPIOCLKGR_CLK_EN_S 0 568 569 //***************************************************************************** 570 // 571 // Register: PRCM_O_GPIOCLKGS 572 // 573 //***************************************************************************** 574 // Field: [0] CLK_EN 575 // 576 // 577 // 0: Disable clock 578 // 1: Enable clock 579 // 580 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 581 #define PRCM_GPIOCLKGS_CLK_EN 0x00000001 582 #define PRCM_GPIOCLKGS_CLK_EN_BITN 0 583 #define PRCM_GPIOCLKGS_CLK_EN_M 0x00000001 584 #define PRCM_GPIOCLKGS_CLK_EN_S 0 585 586 //***************************************************************************** 587 // 588 // Register: PRCM_O_GPIOCLKGDS 589 // 590 //***************************************************************************** 591 // Field: [0] CLK_EN 592 // 593 // 594 // 0: Disable clock 595 // 1: Enable clock 596 // 597 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 598 #define PRCM_GPIOCLKGDS_CLK_EN 0x00000001 599 #define PRCM_GPIOCLKGDS_CLK_EN_BITN 0 600 #define PRCM_GPIOCLKGDS_CLK_EN_M 0x00000001 601 #define PRCM_GPIOCLKGDS_CLK_EN_S 0 602 603 //***************************************************************************** 604 // 605 // Register: PRCM_O_GPTCLKGR 606 // 607 //***************************************************************************** 608 // Field: [3:0] CLK_EN 609 // 610 // Each bit below has the following meaning: 611 // 612 // 0: Disable clock 613 // 1: Enable clock 614 // 615 // ENUMs can be combined 616 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 617 // ENUMs: 618 // GPT3 Enable clock for GPT3 619 // GPT2 Enable clock for GPT2 620 // GPT1 Enable clock for GPT1 621 // GPT0 Enable clock for GPT0 622 #define PRCM_GPTCLKGR_CLK_EN_W 4 623 #define PRCM_GPTCLKGR_CLK_EN_M 0x0000000F 624 #define PRCM_GPTCLKGR_CLK_EN_S 0 625 #define PRCM_GPTCLKGR_CLK_EN_GPT3 0x00000008 626 #define PRCM_GPTCLKGR_CLK_EN_GPT2 0x00000004 627 #define PRCM_GPTCLKGR_CLK_EN_GPT1 0x00000002 628 #define PRCM_GPTCLKGR_CLK_EN_GPT0 0x00000001 629 630 //***************************************************************************** 631 // 632 // Register: PRCM_O_GPTCLKGS 633 // 634 //***************************************************************************** 635 // Field: [3:0] CLK_EN 636 // 637 // Each bit below has the following meaning: 638 // 639 // 0: Disable clock 640 // 1: Enable clock 641 // 642 // ENUMs can be combined 643 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 644 // ENUMs: 645 // GPT3 Enable clock for GPT3 646 // GPT2 Enable clock for GPT2 647 // GPT1 Enable clock for GPT1 648 // GPT0 Enable clock for GPT0 649 #define PRCM_GPTCLKGS_CLK_EN_W 4 650 #define PRCM_GPTCLKGS_CLK_EN_M 0x0000000F 651 #define PRCM_GPTCLKGS_CLK_EN_S 0 652 #define PRCM_GPTCLKGS_CLK_EN_GPT3 0x00000008 653 #define PRCM_GPTCLKGS_CLK_EN_GPT2 0x00000004 654 #define PRCM_GPTCLKGS_CLK_EN_GPT1 0x00000002 655 #define PRCM_GPTCLKGS_CLK_EN_GPT0 0x00000001 656 657 //***************************************************************************** 658 // 659 // Register: PRCM_O_GPTCLKGDS 660 // 661 //***************************************************************************** 662 // Field: [3:0] CLK_EN 663 // 664 // Each bit below has the following meaning: 665 // 666 // 0: Disable clock 667 // 1: Enable clock 668 // 669 // ENUMs can be combined 670 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 671 // ENUMs: 672 // GPT3 Enable clock for GPT3 673 // GPT2 Enable clock for GPT2 674 // GPT1 Enable clock for GPT1 675 // GPT0 Enable clock for GPT0 676 #define PRCM_GPTCLKGDS_CLK_EN_W 4 677 #define PRCM_GPTCLKGDS_CLK_EN_M 0x0000000F 678 #define PRCM_GPTCLKGDS_CLK_EN_S 0 679 #define PRCM_GPTCLKGDS_CLK_EN_GPT3 0x00000008 680 #define PRCM_GPTCLKGDS_CLK_EN_GPT2 0x00000004 681 #define PRCM_GPTCLKGDS_CLK_EN_GPT1 0x00000002 682 #define PRCM_GPTCLKGDS_CLK_EN_GPT0 0x00000001 683 684 //***************************************************************************** 685 // 686 // Register: PRCM_O_I2CCLKGR 687 // 688 //***************************************************************************** 689 // Field: [0] CLK_EN 690 // 691 // 692 // 0: Disable clock 693 // 1: Enable clock 694 // 695 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 696 #define PRCM_I2CCLKGR_CLK_EN 0x00000001 697 #define PRCM_I2CCLKGR_CLK_EN_BITN 0 698 #define PRCM_I2CCLKGR_CLK_EN_M 0x00000001 699 #define PRCM_I2CCLKGR_CLK_EN_S 0 700 701 //***************************************************************************** 702 // 703 // Register: PRCM_O_I2CCLKGS 704 // 705 //***************************************************************************** 706 // Field: [0] CLK_EN 707 // 708 // 709 // 0: Disable clock 710 // 1: Enable clock 711 // 712 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 713 #define PRCM_I2CCLKGS_CLK_EN 0x00000001 714 #define PRCM_I2CCLKGS_CLK_EN_BITN 0 715 #define PRCM_I2CCLKGS_CLK_EN_M 0x00000001 716 #define PRCM_I2CCLKGS_CLK_EN_S 0 717 718 //***************************************************************************** 719 // 720 // Register: PRCM_O_I2CCLKGDS 721 // 722 //***************************************************************************** 723 // Field: [0] CLK_EN 724 // 725 // 726 // 0: Disable clock 727 // 1: Enable clock 728 // 729 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 730 #define PRCM_I2CCLKGDS_CLK_EN 0x00000001 731 #define PRCM_I2CCLKGDS_CLK_EN_BITN 0 732 #define PRCM_I2CCLKGDS_CLK_EN_M 0x00000001 733 #define PRCM_I2CCLKGDS_CLK_EN_S 0 734 735 //***************************************************************************** 736 // 737 // Register: PRCM_O_UARTCLKGR 738 // 739 //***************************************************************************** 740 // Field: [0] CLK_EN 741 // 742 // 743 // 0: Disable clock 744 // 1: Enable clock 745 // 746 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 747 #define PRCM_UARTCLKGR_CLK_EN 0x00000001 748 #define PRCM_UARTCLKGR_CLK_EN_BITN 0 749 #define PRCM_UARTCLKGR_CLK_EN_M 0x00000001 750 #define PRCM_UARTCLKGR_CLK_EN_S 0 751 752 //***************************************************************************** 753 // 754 // Register: PRCM_O_UARTCLKGS 755 // 756 //***************************************************************************** 757 // Field: [0] CLK_EN 758 // 759 // 760 // 0: Disable clock 761 // 1: Enable clock 762 // 763 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 764 #define PRCM_UARTCLKGS_CLK_EN 0x00000001 765 #define PRCM_UARTCLKGS_CLK_EN_BITN 0 766 #define PRCM_UARTCLKGS_CLK_EN_M 0x00000001 767 #define PRCM_UARTCLKGS_CLK_EN_S 0 768 769 //***************************************************************************** 770 // 771 // Register: PRCM_O_UARTCLKGDS 772 // 773 //***************************************************************************** 774 // Field: [0] CLK_EN 775 // 776 // 777 // 0: Disable clock 778 // 1: Enable clock 779 // 780 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 781 #define PRCM_UARTCLKGDS_CLK_EN 0x00000001 782 #define PRCM_UARTCLKGDS_CLK_EN_BITN 0 783 #define PRCM_UARTCLKGDS_CLK_EN_M 0x00000001 784 #define PRCM_UARTCLKGDS_CLK_EN_S 0 785 786 //***************************************************************************** 787 // 788 // Register: PRCM_O_SSICLKGR 789 // 790 //***************************************************************************** 791 // Field: [1:0] CLK_EN 792 // 793 // 794 // 0: Disable clock 795 // 1: Enable clock 796 // 797 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 798 // ENUMs: 799 // SSI1 Enable clock for SSI1 800 // SSI0 Enable clock for SSI0 801 #define PRCM_SSICLKGR_CLK_EN_W 2 802 #define PRCM_SSICLKGR_CLK_EN_M 0x00000003 803 #define PRCM_SSICLKGR_CLK_EN_S 0 804 #define PRCM_SSICLKGR_CLK_EN_SSI1 0x00000002 805 #define PRCM_SSICLKGR_CLK_EN_SSI0 0x00000001 806 807 //***************************************************************************** 808 // 809 // Register: PRCM_O_SSICLKGS 810 // 811 //***************************************************************************** 812 // Field: [1:0] CLK_EN 813 // 814 // 815 // 0: Disable clock 816 // 1: Enable clock 817 // 818 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 819 // ENUMs: 820 // SSI1 Enable clock for SSI1 821 // SSI0 Enable clock for SSI0 822 #define PRCM_SSICLKGS_CLK_EN_W 2 823 #define PRCM_SSICLKGS_CLK_EN_M 0x00000003 824 #define PRCM_SSICLKGS_CLK_EN_S 0 825 #define PRCM_SSICLKGS_CLK_EN_SSI1 0x00000002 826 #define PRCM_SSICLKGS_CLK_EN_SSI0 0x00000001 827 828 //***************************************************************************** 829 // 830 // Register: PRCM_O_SSICLKGDS 831 // 832 //***************************************************************************** 833 // Field: [1:0] CLK_EN 834 // 835 // 836 // 0: Disable clock 837 // 1: Enable clock 838 // 839 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 840 // ENUMs: 841 // SSI1 Enable clock for SSI1 842 // SSI0 Enable clock for SSI0 843 #define PRCM_SSICLKGDS_CLK_EN_W 2 844 #define PRCM_SSICLKGDS_CLK_EN_M 0x00000003 845 #define PRCM_SSICLKGDS_CLK_EN_S 0 846 #define PRCM_SSICLKGDS_CLK_EN_SSI1 0x00000002 847 #define PRCM_SSICLKGDS_CLK_EN_SSI0 0x00000001 848 849 //***************************************************************************** 850 // 851 // Register: PRCM_O_I2SCLKGR 852 // 853 //***************************************************************************** 854 // Field: [0] CLK_EN 855 // 856 // 857 // 0: Disable clock 858 // 1: Enable clock 859 // 860 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 861 #define PRCM_I2SCLKGR_CLK_EN 0x00000001 862 #define PRCM_I2SCLKGR_CLK_EN_BITN 0 863 #define PRCM_I2SCLKGR_CLK_EN_M 0x00000001 864 #define PRCM_I2SCLKGR_CLK_EN_S 0 865 866 //***************************************************************************** 867 // 868 // Register: PRCM_O_I2SCLKGS 869 // 870 //***************************************************************************** 871 // Field: [0] CLK_EN 872 // 873 // 874 // 0: Disable clock 875 // 1: Enable clock 876 // 877 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 878 #define PRCM_I2SCLKGS_CLK_EN 0x00000001 879 #define PRCM_I2SCLKGS_CLK_EN_BITN 0 880 #define PRCM_I2SCLKGS_CLK_EN_M 0x00000001 881 #define PRCM_I2SCLKGS_CLK_EN_S 0 882 883 //***************************************************************************** 884 // 885 // Register: PRCM_O_I2SCLKGDS 886 // 887 //***************************************************************************** 888 // Field: [0] CLK_EN 889 // 890 // 891 // 0: Disable clock 892 // 1: Enable clock 893 // 894 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 895 #define PRCM_I2SCLKGDS_CLK_EN 0x00000001 896 #define PRCM_I2SCLKGDS_CLK_EN_BITN 0 897 #define PRCM_I2SCLKGDS_CLK_EN_M 0x00000001 898 #define PRCM_I2SCLKGDS_CLK_EN_S 0 899 900 //***************************************************************************** 901 // 902 // Register: PRCM_O_CPUCLKDIV 903 // 904 //***************************************************************************** 905 // Field: [0] RATIO 906 // 907 // Internal. Only to be used through TI provided API. 908 // ENUMs: 909 // DIV2 Internal. Only to be used through TI provided API. 910 // DIV1 Internal. Only to be used through TI provided API. 911 #define PRCM_CPUCLKDIV_RATIO 0x00000001 912 #define PRCM_CPUCLKDIV_RATIO_BITN 0 913 #define PRCM_CPUCLKDIV_RATIO_M 0x00000001 914 #define PRCM_CPUCLKDIV_RATIO_S 0 915 #define PRCM_CPUCLKDIV_RATIO_DIV2 0x00000001 916 #define PRCM_CPUCLKDIV_RATIO_DIV1 0x00000000 917 918 //***************************************************************************** 919 // 920 // Register: PRCM_O_I2SBCLKSEL 921 // 922 //***************************************************************************** 923 // Field: [0] SRC 924 // 925 // BCLK source selector 926 // 927 // 0: Use external BCLK 928 // 1: Use internally generated clock 929 // 930 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 931 #define PRCM_I2SBCLKSEL_SRC 0x00000001 932 #define PRCM_I2SBCLKSEL_SRC_BITN 0 933 #define PRCM_I2SBCLKSEL_SRC_M 0x00000001 934 #define PRCM_I2SBCLKSEL_SRC_S 0 935 936 //***************************************************************************** 937 // 938 // Register: PRCM_O_GPTCLKDIV 939 // 940 //***************************************************************************** 941 // Field: [3:0] RATIO 942 // 943 // Scalar used for GPTs. The division rate will be constant and ungated for Run 944 // / Sleep / DeepSleep mode. 945 // 946 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 947 // Other values are not supported. 948 // ENUMs: 949 // DIV256 Divide by 256 950 // DIV128 Divide by 128 951 // DIV64 Divide by 64 952 // DIV32 Divide by 32 953 // DIV16 Divide by 16 954 // DIV8 Divide by 8 955 // DIV4 Divide by 4 956 // DIV2 Divide by 2 957 // DIV1 Divide by 1 958 #define PRCM_GPTCLKDIV_RATIO_W 4 959 #define PRCM_GPTCLKDIV_RATIO_M 0x0000000F 960 #define PRCM_GPTCLKDIV_RATIO_S 0 961 #define PRCM_GPTCLKDIV_RATIO_DIV256 0x00000008 962 #define PRCM_GPTCLKDIV_RATIO_DIV128 0x00000007 963 #define PRCM_GPTCLKDIV_RATIO_DIV64 0x00000006 964 #define PRCM_GPTCLKDIV_RATIO_DIV32 0x00000005 965 #define PRCM_GPTCLKDIV_RATIO_DIV16 0x00000004 966 #define PRCM_GPTCLKDIV_RATIO_DIV8 0x00000003 967 #define PRCM_GPTCLKDIV_RATIO_DIV4 0x00000002 968 #define PRCM_GPTCLKDIV_RATIO_DIV2 0x00000001 969 #define PRCM_GPTCLKDIV_RATIO_DIV1 0x00000000 970 971 //***************************************************************************** 972 // 973 // Register: PRCM_O_I2SCLKCTL 974 // 975 //***************************************************************************** 976 // Field: [3] SMPL_ON_POSEDGE 977 // 978 // On the I2S serial interface, data and WCLK is sampled and clocked out on 979 // opposite edges of BCLK. 980 // 981 // 0 - data and WCLK are sampled on the negative edge and clocked out on the 982 // positive edge. 983 // 1 - data and WCLK are sampled on the positive edge and clocked out on the 984 // negative edge. 985 // 986 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 987 #define PRCM_I2SCLKCTL_SMPL_ON_POSEDGE 0x00000008 988 #define PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_BITN 3 989 #define PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_M 0x00000008 990 #define PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_S 3 991 992 // Field: [2:1] WCLK_PHASE 993 // 994 // Decides how the WCLK division ratio is calculated and used to generate 995 // different duty cycles (See I2SWCLKDIV.WDIV). 996 // 997 // 0: Single phase 998 // 1: Dual phase 999 // 2: User Defined 1000 // 3: Reserved/Undefined 1001 // 1002 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 1003 #define PRCM_I2SCLKCTL_WCLK_PHASE_W 2 1004 #define PRCM_I2SCLKCTL_WCLK_PHASE_M 0x00000006 1005 #define PRCM_I2SCLKCTL_WCLK_PHASE_S 1 1006 1007 // Field: [0] EN 1008 // 1009 // 1010 // 0: MCLK, BCLK and **WCLK** will be static low 1011 // 1: Enables the generation of MCLK, BCLK and WCLK 1012 // 1013 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 1014 #define PRCM_I2SCLKCTL_EN 0x00000001 1015 #define PRCM_I2SCLKCTL_EN_BITN 0 1016 #define PRCM_I2SCLKCTL_EN_M 0x00000001 1017 #define PRCM_I2SCLKCTL_EN_S 0 1018 1019 //***************************************************************************** 1020 // 1021 // Register: PRCM_O_I2SMCLKDIV 1022 // 1023 //***************************************************************************** 1024 // Field: [9:0] MDIV 1025 // 1026 // An unsigned factor of the division ratio used to generate MCLK [2-1024]: 1027 // 1028 // MCLK = MCUCLK/MDIV[Hz] 1029 // MCUCLK is 48MHz in normal mode. For powerdown mode the frequency is defined 1030 // by AON_WUC:MCUCLK.PWR_DWN_SRC 1031 // 1032 // A value of 0 is interpreted as 1024. 1033 // A value of 1 is invalid. 1034 // If MDIV is odd the low phase of the clock is one MCUCLK period longer than 1035 // the high phase. 1036 // 1037 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 1038 #define PRCM_I2SMCLKDIV_MDIV_W 10 1039 #define PRCM_I2SMCLKDIV_MDIV_M 0x000003FF 1040 #define PRCM_I2SMCLKDIV_MDIV_S 0 1041 1042 //***************************************************************************** 1043 // 1044 // Register: PRCM_O_I2SBCLKDIV 1045 // 1046 //***************************************************************************** 1047 // Field: [9:0] BDIV 1048 // 1049 // An unsigned factor of the division ratio used to generate I2S BCLK [2-1024]: 1050 // 1051 // BCLK = MCUCLK/BDIV[Hz] 1052 // MCUCLK is 48MHz in normal mode. For powerdown mode the frequency is defined 1053 // by AON_WUC:MCUCLK.PWR_DWN_SRC 1054 // 1055 // A value of 0 is interpreted as 1024. 1056 // A value of 1 is invalid. 1057 // If BDIV is odd and I2SCLKCTL.SMPL_ON_POSEDGE = 0, the low phase of the clock 1058 // is one MCUCLK period longer than the high phase. 1059 // If BDIV is odd and I2SCLKCTL.SMPL_ON_POSEDGE = 1 , the high phase of the 1060 // clock is one MCUCLK period longer than the low phase. 1061 // 1062 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 1063 #define PRCM_I2SBCLKDIV_BDIV_W 10 1064 #define PRCM_I2SBCLKDIV_BDIV_M 0x000003FF 1065 #define PRCM_I2SBCLKDIV_BDIV_S 0 1066 1067 //***************************************************************************** 1068 // 1069 // Register: PRCM_O_I2SWCLKDIV 1070 // 1071 //***************************************************************************** 1072 // Field: [15:0] WDIV 1073 // 1074 // If I2SCLKCTL.WCLK_PHASE = 0, Single phase. 1075 // WCLK is high one BCLK period and low WDIV[9:0] (unsigned, [1-1023]) BCLK 1076 // periods. 1077 // 1078 // WCLK = MCUCLK / BDIV*(WDIV[9:0] + 1) [Hz] 1079 // MCUCLK is 48MHz in normal mode. For powerdown mode the frequency is defined 1080 // by AON_WUC:MCUCLK.PWR_DWN_SRC 1081 // 1082 // If I2SCLKCTL.WCLK_PHASE = 1, Dual phase. 1083 // Each phase on WCLK (50% duty cycle) is WDIV[9:0] (unsigned, [1-1023]) BCLK 1084 // periods. 1085 // 1086 // WCLK = MCUCLK / BDIV*(2*WDIV[9:0]) [Hz] 1087 // 1088 // If I2SCLKCTL.WCLK_PHASE = 2, User defined. 1089 // WCLK is high WDIV[7:0] (unsigned, [1-255]) BCLK periods and low WDIV[15:8] 1090 // (unsigned, [1-255]) BCLK periods. 1091 // 1092 // WCLK = MCUCLK / (BDIV*(WDIV[7:0] + WDIV[15:8]) [Hz] 1093 // 1094 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 1095 #define PRCM_I2SWCLKDIV_WDIV_W 16 1096 #define PRCM_I2SWCLKDIV_WDIV_M 0x0000FFFF 1097 #define PRCM_I2SWCLKDIV_WDIV_S 0 1098 1099 //***************************************************************************** 1100 // 1101 // Register: PRCM_O_SWRESET 1102 // 1103 //***************************************************************************** 1104 // Field: [2] MCU 1105 // 1106 // Internal. Only to be used through TI provided API. 1107 #define PRCM_SWRESET_MCU 0x00000004 1108 #define PRCM_SWRESET_MCU_BITN 2 1109 #define PRCM_SWRESET_MCU_M 0x00000004 1110 #define PRCM_SWRESET_MCU_S 2 1111 1112 //***************************************************************************** 1113 // 1114 // Register: PRCM_O_WARMRESET 1115 // 1116 //***************************************************************************** 1117 // Field: [2] WR_TO_PINRESET 1118 // 1119 // 0: No action 1120 // 1: A warm system reset event triggered by the below listed sources will 1121 // result in an emulated pin reset. 1122 // 1123 // Warm reset sources included: 1124 // ICEPick sysreset 1125 // System CPU reset request, CPU_SCS:AIRCR.SYSRESETREQ 1126 // System CPU Lockup 1127 // WDT timeout 1128 // 1129 // An active ICEPick block system reset will gate all sources except ICEPick 1130 // sysreset 1131 // 1132 // SW can read AON_SYSCTL:RESETCTL.RESET_SRC to find the source of the last 1133 // reset resulting in a full power up sequence. WARMRESET in this register is 1134 // set in the scenario that WR_TO_PINRESET=1 and one of the above listed 1135 // sources is triggered. 1136 #define PRCM_WARMRESET_WR_TO_PINRESET 0x00000004 1137 #define PRCM_WARMRESET_WR_TO_PINRESET_BITN 2 1138 #define PRCM_WARMRESET_WR_TO_PINRESET_M 0x00000004 1139 #define PRCM_WARMRESET_WR_TO_PINRESET_S 2 1140 1141 // Field: [1] LOCKUP_STAT 1142 // 1143 // 1144 // 0: No registred event 1145 // 1: A system CPU LOCKUP event has occured since last SW clear of the 1146 // register. 1147 // 1148 // A read of this register clears both WDT_STAT and LOCKUP_STAT. 1149 #define PRCM_WARMRESET_LOCKUP_STAT 0x00000002 1150 #define PRCM_WARMRESET_LOCKUP_STAT_BITN 1 1151 #define PRCM_WARMRESET_LOCKUP_STAT_M 0x00000002 1152 #define PRCM_WARMRESET_LOCKUP_STAT_S 1 1153 1154 // Field: [0] WDT_STAT 1155 // 1156 // 1157 // 0: No registered event 1158 // 1: A WDT event has occured since last SW clear of the register. 1159 // 1160 // A read of this register clears both WDT_STAT and LOCKUP_STAT. 1161 #define PRCM_WARMRESET_WDT_STAT 0x00000001 1162 #define PRCM_WARMRESET_WDT_STAT_BITN 0 1163 #define PRCM_WARMRESET_WDT_STAT_M 0x00000001 1164 #define PRCM_WARMRESET_WDT_STAT_S 0 1165 1166 //***************************************************************************** 1167 // 1168 // Register: PRCM_O_PDCTL0 1169 // 1170 //***************************************************************************** 1171 // Field: [2] PERIPH_ON 1172 // 1173 // PERIPH Power domain. 1174 // 1175 // 0: PERIPH power domain is powered down 1176 // 1: PERIPH power domain is powered up 1177 #define PRCM_PDCTL0_PERIPH_ON 0x00000004 1178 #define PRCM_PDCTL0_PERIPH_ON_BITN 2 1179 #define PRCM_PDCTL0_PERIPH_ON_M 0x00000004 1180 #define PRCM_PDCTL0_PERIPH_ON_S 2 1181 1182 // Field: [1] SERIAL_ON 1183 // 1184 // SERIAL Power domain. 1185 // 1186 // 0: SERIAL power domain is powered down 1187 // 1: SERIAL power domain is powered up 1188 #define PRCM_PDCTL0_SERIAL_ON 0x00000002 1189 #define PRCM_PDCTL0_SERIAL_ON_BITN 1 1190 #define PRCM_PDCTL0_SERIAL_ON_M 0x00000002 1191 #define PRCM_PDCTL0_SERIAL_ON_S 1 1192 1193 // Field: [0] RFC_ON 1194 // 1195 // 1196 // 0: RFC power domain powered off if also PDCTL1.RFC_ON = 0 1197 // 1: RFC power domain powered on 1198 #define PRCM_PDCTL0_RFC_ON 0x00000001 1199 #define PRCM_PDCTL0_RFC_ON_BITN 0 1200 #define PRCM_PDCTL0_RFC_ON_M 0x00000001 1201 #define PRCM_PDCTL0_RFC_ON_S 0 1202 1203 //***************************************************************************** 1204 // 1205 // Register: PRCM_O_PDCTL0RFC 1206 // 1207 //***************************************************************************** 1208 // Field: [0] ON 1209 // 1210 // Alias for PDCTL0.RFC_ON 1211 #define PRCM_PDCTL0RFC_ON 0x00000001 1212 #define PRCM_PDCTL0RFC_ON_BITN 0 1213 #define PRCM_PDCTL0RFC_ON_M 0x00000001 1214 #define PRCM_PDCTL0RFC_ON_S 0 1215 1216 //***************************************************************************** 1217 // 1218 // Register: PRCM_O_PDCTL0SERIAL 1219 // 1220 //***************************************************************************** 1221 // Field: [0] ON 1222 // 1223 // Alias for PDCTL0.SERIAL_ON 1224 #define PRCM_PDCTL0SERIAL_ON 0x00000001 1225 #define PRCM_PDCTL0SERIAL_ON_BITN 0 1226 #define PRCM_PDCTL0SERIAL_ON_M 0x00000001 1227 #define PRCM_PDCTL0SERIAL_ON_S 0 1228 1229 //***************************************************************************** 1230 // 1231 // Register: PRCM_O_PDCTL0PERIPH 1232 // 1233 //***************************************************************************** 1234 // Field: [0] ON 1235 // 1236 // Alias for PDCTL0.PERIPH_ON 1237 #define PRCM_PDCTL0PERIPH_ON 0x00000001 1238 #define PRCM_PDCTL0PERIPH_ON_BITN 0 1239 #define PRCM_PDCTL0PERIPH_ON_M 0x00000001 1240 #define PRCM_PDCTL0PERIPH_ON_S 0 1241 1242 //***************************************************************************** 1243 // 1244 // Register: PRCM_O_PDSTAT0 1245 // 1246 //***************************************************************************** 1247 // Field: [2] PERIPH_ON 1248 // 1249 // PERIPH Power domain. 1250 // 1251 // 0: Domain may be powered down 1252 // 1: Domain powered up (guaranteed) 1253 #define PRCM_PDSTAT0_PERIPH_ON 0x00000004 1254 #define PRCM_PDSTAT0_PERIPH_ON_BITN 2 1255 #define PRCM_PDSTAT0_PERIPH_ON_M 0x00000004 1256 #define PRCM_PDSTAT0_PERIPH_ON_S 2 1257 1258 // Field: [1] SERIAL_ON 1259 // 1260 // SERIAL Power domain. 1261 // 1262 // 0: Domain may be powered down 1263 // 1: Domain powered up (guaranteed) 1264 #define PRCM_PDSTAT0_SERIAL_ON 0x00000002 1265 #define PRCM_PDSTAT0_SERIAL_ON_BITN 1 1266 #define PRCM_PDSTAT0_SERIAL_ON_M 0x00000002 1267 #define PRCM_PDSTAT0_SERIAL_ON_S 1 1268 1269 // Field: [0] RFC_ON 1270 // 1271 // RFC Power domain 1272 // 1273 // 0: Domain may be powered down 1274 // 1: Domain powered up (guaranteed) 1275 #define PRCM_PDSTAT0_RFC_ON 0x00000001 1276 #define PRCM_PDSTAT0_RFC_ON_BITN 0 1277 #define PRCM_PDSTAT0_RFC_ON_M 0x00000001 1278 #define PRCM_PDSTAT0_RFC_ON_S 0 1279 1280 //***************************************************************************** 1281 // 1282 // Register: PRCM_O_PDSTAT0RFC 1283 // 1284 //***************************************************************************** 1285 // Field: [0] ON 1286 // 1287 // Alias for PDSTAT0.RFC_ON 1288 #define PRCM_PDSTAT0RFC_ON 0x00000001 1289 #define PRCM_PDSTAT0RFC_ON_BITN 0 1290 #define PRCM_PDSTAT0RFC_ON_M 0x00000001 1291 #define PRCM_PDSTAT0RFC_ON_S 0 1292 1293 //***************************************************************************** 1294 // 1295 // Register: PRCM_O_PDSTAT0SERIAL 1296 // 1297 //***************************************************************************** 1298 // Field: [0] ON 1299 // 1300 // Alias for PDSTAT0.SERIAL_ON 1301 #define PRCM_PDSTAT0SERIAL_ON 0x00000001 1302 #define PRCM_PDSTAT0SERIAL_ON_BITN 0 1303 #define PRCM_PDSTAT0SERIAL_ON_M 0x00000001 1304 #define PRCM_PDSTAT0SERIAL_ON_S 0 1305 1306 //***************************************************************************** 1307 // 1308 // Register: PRCM_O_PDSTAT0PERIPH 1309 // 1310 //***************************************************************************** 1311 // Field: [0] ON 1312 // 1313 // Alias for PDSTAT0.PERIPH_ON 1314 #define PRCM_PDSTAT0PERIPH_ON 0x00000001 1315 #define PRCM_PDSTAT0PERIPH_ON_BITN 0 1316 #define PRCM_PDSTAT0PERIPH_ON_M 0x00000001 1317 #define PRCM_PDSTAT0PERIPH_ON_S 0 1318 1319 //***************************************************************************** 1320 // 1321 // Register: PRCM_O_PDCTL1 1322 // 1323 //***************************************************************************** 1324 // Field: [3] VIMS_MODE 1325 // 1326 // 1327 // 0: VIMS power domain is only powered when CPU power domain is powered. 1328 // 1: VIMS power domain is powered whenever the BUS power domain is powered. 1329 #define PRCM_PDCTL1_VIMS_MODE 0x00000008 1330 #define PRCM_PDCTL1_VIMS_MODE_BITN 3 1331 #define PRCM_PDCTL1_VIMS_MODE_M 0x00000008 1332 #define PRCM_PDCTL1_VIMS_MODE_S 3 1333 1334 // Field: [2] RFC_ON 1335 // 1336 // 1337 // 0: RFC power domain powered off if also PDCTL0.RFC_ON = 0 1338 // 1: RFC power domain powered on 1339 // 1340 // Bit shall be used by RFC in autonomus mode but there is no HW restrictions 1341 // fom system CPU to access the bit. 1342 #define PRCM_PDCTL1_RFC_ON 0x00000004 1343 #define PRCM_PDCTL1_RFC_ON_BITN 2 1344 #define PRCM_PDCTL1_RFC_ON_M 0x00000004 1345 #define PRCM_PDCTL1_RFC_ON_S 2 1346 1347 // Field: [1] CPU_ON 1348 // 1349 // 1350 // 0: Causes a power down of the CPU power domain when system CPU indicates it 1351 // is idle. 1352 // 1: Initiates power-on of the CPU power domain. 1353 // 1354 // This bit is automatically set by a WIC power-on event. 1355 #define PRCM_PDCTL1_CPU_ON 0x00000002 1356 #define PRCM_PDCTL1_CPU_ON_BITN 1 1357 #define PRCM_PDCTL1_CPU_ON_M 0x00000002 1358 #define PRCM_PDCTL1_CPU_ON_S 1 1359 1360 //***************************************************************************** 1361 // 1362 // Register: PRCM_O_PDCTL1CPU 1363 // 1364 //***************************************************************************** 1365 // Field: [0] ON 1366 // 1367 // This is an alias for PDCTL1.CPU_ON 1368 #define PRCM_PDCTL1CPU_ON 0x00000001 1369 #define PRCM_PDCTL1CPU_ON_BITN 0 1370 #define PRCM_PDCTL1CPU_ON_M 0x00000001 1371 #define PRCM_PDCTL1CPU_ON_S 0 1372 1373 //***************************************************************************** 1374 // 1375 // Register: PRCM_O_PDCTL1RFC 1376 // 1377 //***************************************************************************** 1378 // Field: [0] ON 1379 // 1380 // This is an alias for PDCTL1.RFC_ON 1381 #define PRCM_PDCTL1RFC_ON 0x00000001 1382 #define PRCM_PDCTL1RFC_ON_BITN 0 1383 #define PRCM_PDCTL1RFC_ON_M 0x00000001 1384 #define PRCM_PDCTL1RFC_ON_S 0 1385 1386 //***************************************************************************** 1387 // 1388 // Register: PRCM_O_PDCTL1VIMS 1389 // 1390 //***************************************************************************** 1391 // Field: [0] ON 1392 // 1393 // This is an alias for PDCTL1.VIMS_MODE 1394 #define PRCM_PDCTL1VIMS_ON 0x00000001 1395 #define PRCM_PDCTL1VIMS_ON_BITN 0 1396 #define PRCM_PDCTL1VIMS_ON_M 0x00000001 1397 #define PRCM_PDCTL1VIMS_ON_S 0 1398 1399 //***************************************************************************** 1400 // 1401 // Register: PRCM_O_PDSTAT1 1402 // 1403 //***************************************************************************** 1404 // Field: [4] BUS_ON 1405 // 1406 // 1407 // 0: BUS domain not accessible 1408 // 1: BUS domain is currently accessible 1409 #define PRCM_PDSTAT1_BUS_ON 0x00000010 1410 #define PRCM_PDSTAT1_BUS_ON_BITN 4 1411 #define PRCM_PDSTAT1_BUS_ON_M 0x00000010 1412 #define PRCM_PDSTAT1_BUS_ON_S 4 1413 1414 // Field: [3] VIMS_MODE 1415 // 1416 // 1417 // 0: VIMS domain not accessible 1418 // 1: VIMS domain is currently accessible 1419 #define PRCM_PDSTAT1_VIMS_MODE 0x00000008 1420 #define PRCM_PDSTAT1_VIMS_MODE_BITN 3 1421 #define PRCM_PDSTAT1_VIMS_MODE_M 0x00000008 1422 #define PRCM_PDSTAT1_VIMS_MODE_S 3 1423 1424 // Field: [2] RFC_ON 1425 // 1426 // 1427 // 0: RFC domain not accessible 1428 // 1: RFC domain is currently accessible 1429 #define PRCM_PDSTAT1_RFC_ON 0x00000004 1430 #define PRCM_PDSTAT1_RFC_ON_BITN 2 1431 #define PRCM_PDSTAT1_RFC_ON_M 0x00000004 1432 #define PRCM_PDSTAT1_RFC_ON_S 2 1433 1434 // Field: [1] CPU_ON 1435 // 1436 // 1437 // 0: CPU and BUS domain not accessible 1438 // 1: CPU and BUS domains are both currently accessible 1439 #define PRCM_PDSTAT1_CPU_ON 0x00000002 1440 #define PRCM_PDSTAT1_CPU_ON_BITN 1 1441 #define PRCM_PDSTAT1_CPU_ON_M 0x00000002 1442 #define PRCM_PDSTAT1_CPU_ON_S 1 1443 1444 //***************************************************************************** 1445 // 1446 // Register: PRCM_O_PDSTAT1BUS 1447 // 1448 //***************************************************************************** 1449 // Field: [0] ON 1450 // 1451 // This is an alias for PDSTAT1.BUS_ON 1452 #define PRCM_PDSTAT1BUS_ON 0x00000001 1453 #define PRCM_PDSTAT1BUS_ON_BITN 0 1454 #define PRCM_PDSTAT1BUS_ON_M 0x00000001 1455 #define PRCM_PDSTAT1BUS_ON_S 0 1456 1457 //***************************************************************************** 1458 // 1459 // Register: PRCM_O_PDSTAT1RFC 1460 // 1461 //***************************************************************************** 1462 // Field: [0] ON 1463 // 1464 // This is an alias for PDSTAT1.RFC_ON 1465 #define PRCM_PDSTAT1RFC_ON 0x00000001 1466 #define PRCM_PDSTAT1RFC_ON_BITN 0 1467 #define PRCM_PDSTAT1RFC_ON_M 0x00000001 1468 #define PRCM_PDSTAT1RFC_ON_S 0 1469 1470 //***************************************************************************** 1471 // 1472 // Register: PRCM_O_PDSTAT1CPU 1473 // 1474 //***************************************************************************** 1475 // Field: [0] ON 1476 // 1477 // This is an alias for PDSTAT1.CPU_ON 1478 #define PRCM_PDSTAT1CPU_ON 0x00000001 1479 #define PRCM_PDSTAT1CPU_ON_BITN 0 1480 #define PRCM_PDSTAT1CPU_ON_M 0x00000001 1481 #define PRCM_PDSTAT1CPU_ON_S 0 1482 1483 //***************************************************************************** 1484 // 1485 // Register: PRCM_O_PDSTAT1VIMS 1486 // 1487 //***************************************************************************** 1488 // Field: [0] ON 1489 // 1490 // This is an alias for PDSTAT1.VIMS_MODE 1491 #define PRCM_PDSTAT1VIMS_ON 0x00000001 1492 #define PRCM_PDSTAT1VIMS_ON_BITN 0 1493 #define PRCM_PDSTAT1VIMS_ON_M 0x00000001 1494 #define PRCM_PDSTAT1VIMS_ON_S 0 1495 1496 //***************************************************************************** 1497 // 1498 // Register: PRCM_O_RFCMODESEL 1499 // 1500 //***************************************************************************** 1501 // Field: [2:0] CURR 1502 // 1503 // Written by MCU - Outputs to RFC. Only modes permitted by RFCMODEHWOPT.AVAIL 1504 // are writeable. 1505 // ENUMs: 1506 // MODE7 Select Mode 7 1507 // MODE6 Select Mode 6 1508 // MODE5 Select Mode 5 1509 // MODE4 Select Mode 4 1510 // MODE3 Select Mode 3 1511 // MODE2 Select Mode 2 1512 // MODE1 Select Mode 1 1513 // MODE0 Select Mode 0 1514 #define PRCM_RFCMODESEL_CURR_W 3 1515 #define PRCM_RFCMODESEL_CURR_M 0x00000007 1516 #define PRCM_RFCMODESEL_CURR_S 0 1517 #define PRCM_RFCMODESEL_CURR_MODE7 0x00000007 1518 #define PRCM_RFCMODESEL_CURR_MODE6 0x00000006 1519 #define PRCM_RFCMODESEL_CURR_MODE5 0x00000005 1520 #define PRCM_RFCMODESEL_CURR_MODE4 0x00000004 1521 #define PRCM_RFCMODESEL_CURR_MODE3 0x00000003 1522 #define PRCM_RFCMODESEL_CURR_MODE2 0x00000002 1523 #define PRCM_RFCMODESEL_CURR_MODE1 0x00000001 1524 #define PRCM_RFCMODESEL_CURR_MODE0 0x00000000 1525 1526 //***************************************************************************** 1527 // 1528 // Register: PRCM_O_RAMRETEN 1529 // 1530 //***************************************************************************** 1531 // Field: [2] RFC 1532 // 1533 // 1534 // 0: Retention for RFC SRAM disabled 1535 // 1: Retention for RFC SRAM enabled 1536 #define PRCM_RAMRETEN_RFC 0x00000004 1537 #define PRCM_RAMRETEN_RFC_BITN 2 1538 #define PRCM_RAMRETEN_RFC_M 0x00000004 1539 #define PRCM_RAMRETEN_RFC_S 2 1540 1541 // Field: [1:0] VIMS 1542 // 1543 // 1544 // 0: Memory retention disabled 1545 // 1: Memory retention enabled 1546 // 1547 // Bit 0: VIMS_TRAM 1548 // Bit 1: VIMS_CRAM 1549 // 1550 // Legal modes depend on settings in VIMS:CTL.MODE 1551 // 1552 // 00: VIMS:CTL.MODE must be OFF before DEEPSLEEP is asserted - must be set to 1553 // CACHE or SPLIT mode after waking up again 1554 // 01: VIMS:CTL.MODE must be GPRAM before DEEPSLEEP is asserted. Must remain in 1555 // GPRAM mode after wake up, alternatively select OFF mode first and then CACHE 1556 // or SPILT mode. 1557 // 10: Illegal mode 1558 // 11: No restrictions 1559 #define PRCM_RAMRETEN_VIMS_W 2 1560 #define PRCM_RAMRETEN_VIMS_M 0x00000003 1561 #define PRCM_RAMRETEN_VIMS_S 0 1562 1563 1564 #endif // __PRCM__ 1565