1 /****************************************************************************** 2 * Filename: hw_trng_h 3 * Revised: 2015-11-12 13:07:02 +0100 (Thu, 12 Nov 2015) 4 * Revision: 45056 5 * 6 * Copyright (c) 2015, Texas Instruments Incorporated 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions are met: 11 * 12 * 1) Redistributions of source code must retain the above copyright notice, 13 * this list of conditions and the following disclaimer. 14 * 15 * 2) Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 19 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may 20 * be used to endorse or promote products derived from this software without 21 * specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 * 35 ******************************************************************************/ 36 37 #ifndef __HW_TRNG_H__ 38 #define __HW_TRNG_H__ 39 40 //***************************************************************************** 41 // 42 // This section defines the register offsets of 43 // TRNG component 44 // 45 //***************************************************************************** 46 // Random Number Lower Word Readout Value 47 #define TRNG_O_OUT0 0x00000000 48 49 // Random Number Upper Word Readout Value 50 #define TRNG_O_OUT1 0x00000004 51 52 // Interrupt Status 53 #define TRNG_O_IRQFLAGSTAT 0x00000008 54 55 // Interrupt Mask 56 #define TRNG_O_IRQFLAGMASK 0x0000000C 57 58 // Interrupt Flag Clear 59 #define TRNG_O_IRQFLAGCLR 0x00000010 60 61 // Control 62 #define TRNG_O_CTL 0x00000014 63 64 // Configuration 0 65 #define TRNG_O_CFG0 0x00000018 66 67 // Alarm Control 68 #define TRNG_O_ALARMCNT 0x0000001C 69 70 // FRO Enable 71 #define TRNG_O_FROEN 0x00000020 72 73 // FRO De-tune Bit 74 #define TRNG_O_FRODETUNE 0x00000024 75 76 // Alarm Event 77 #define TRNG_O_ALARMMASK 0x00000028 78 79 // Alarm Shutdown 80 #define TRNG_O_ALARMSTOP 0x0000002C 81 82 // LFSR Readout Value 83 #define TRNG_O_LFSR0 0x00000030 84 85 // LFSR Readout Value 86 #define TRNG_O_LFSR1 0x00000034 87 88 // LFSR Readout Value 89 #define TRNG_O_LFSR2 0x00000038 90 91 // TRNG Engine Options Information 92 #define TRNG_O_HWOPT 0x00000078 93 94 // HW Version 0 95 #define TRNG_O_HWVER0 0x0000007C 96 97 // Interrupt Status After Masking 98 #define TRNG_O_IRQSTATMASK 0x00001FD8 99 100 // HW Version 1 101 #define TRNG_O_HWVER1 0x00001FE0 102 103 // Interrupt Set 104 #define TRNG_O_IRQSET 0x00001FEC 105 106 // SW Reset Control 107 #define TRNG_O_SWRESET 0x00001FF0 108 109 // Interrupt Status 110 #define TRNG_O_IRQSTAT 0x00001FF8 111 112 //***************************************************************************** 113 // 114 // Register: TRNG_O_OUT0 115 // 116 //***************************************************************************** 117 // Field: [31:0] VALUE_31_0 118 // 119 // LSW of 64- bit random value. New value ready when IRQFLAGSTAT.RDY = 1. 120 #define TRNG_OUT0_VALUE_31_0_W 32 121 #define TRNG_OUT0_VALUE_31_0_M 0xFFFFFFFF 122 #define TRNG_OUT0_VALUE_31_0_S 0 123 124 //***************************************************************************** 125 // 126 // Register: TRNG_O_OUT1 127 // 128 //***************************************************************************** 129 // Field: [31:0] VALUE_63_32 130 // 131 // MSW of 64-bit random value. New value ready when IRQFLAGSTAT.RDY = 1. 132 #define TRNG_OUT1_VALUE_63_32_W 32 133 #define TRNG_OUT1_VALUE_63_32_M 0xFFFFFFFF 134 #define TRNG_OUT1_VALUE_63_32_S 0 135 136 //***************************************************************************** 137 // 138 // Register: TRNG_O_IRQFLAGSTAT 139 // 140 //***************************************************************************** 141 // Field: [31] NEED_CLOCK 142 // 143 // 1: Indicates that the TRNG is busy generating entropy or is in one of its 144 // test modes - clocks may not be turned off and the power supply voltage must 145 // be kept stable. 146 // 0: TRNG is idle and can be shut down 147 #define TRNG_IRQFLAGSTAT_NEED_CLOCK 0x80000000 148 #define TRNG_IRQFLAGSTAT_NEED_CLOCK_BITN 31 149 #define TRNG_IRQFLAGSTAT_NEED_CLOCK_M 0x80000000 150 #define TRNG_IRQFLAGSTAT_NEED_CLOCK_S 31 151 152 // Field: [1] SHUTDOWN_OVF 153 // 154 // 1: The number of FROs shut down (i.e. the number of '1' bits in the 155 // ALARMSTOP register) has exceeded the threshold set by ALARMCNT.SHUTDOWN_THR 156 // 157 // Writing '1' to IRQFLAGCLR.SHUTDOWN_OVF clears this bit to '0' again. 158 #define TRNG_IRQFLAGSTAT_SHUTDOWN_OVF 0x00000002 159 #define TRNG_IRQFLAGSTAT_SHUTDOWN_OVF_BITN 1 160 #define TRNG_IRQFLAGSTAT_SHUTDOWN_OVF_M 0x00000002 161 #define TRNG_IRQFLAGSTAT_SHUTDOWN_OVF_S 1 162 163 // Field: [0] RDY 164 // 165 // 1: Data are available in OUT0 and OUT1. 166 // 167 // Acknowledging this state by writing '1' to IRQFLAGCLR.RDY clears this bit to 168 // '0'. 169 // If a new number is already available in the internal register of the TRNG, 170 // the number is directly clocked into the result register. In this case the 171 // status bit is asserted again, after one clock cycle. 172 #define TRNG_IRQFLAGSTAT_RDY 0x00000001 173 #define TRNG_IRQFLAGSTAT_RDY_BITN 0 174 #define TRNG_IRQFLAGSTAT_RDY_M 0x00000001 175 #define TRNG_IRQFLAGSTAT_RDY_S 0 176 177 //***************************************************************************** 178 // 179 // Register: TRNG_O_IRQFLAGMASK 180 // 181 //***************************************************************************** 182 // Field: [1] SHUTDOWN_OVF 183 // 184 // 1: Allow IRQFLAGSTAT.SHUTDOWN_OVF to activate the interrupt from this 185 // module. 186 #define TRNG_IRQFLAGMASK_SHUTDOWN_OVF 0x00000002 187 #define TRNG_IRQFLAGMASK_SHUTDOWN_OVF_BITN 1 188 #define TRNG_IRQFLAGMASK_SHUTDOWN_OVF_M 0x00000002 189 #define TRNG_IRQFLAGMASK_SHUTDOWN_OVF_S 1 190 191 // Field: [0] RDY 192 // 193 // 1: Allow IRQFLAGSTAT.RDY to activate the interrupt from this module. 194 #define TRNG_IRQFLAGMASK_RDY 0x00000001 195 #define TRNG_IRQFLAGMASK_RDY_BITN 0 196 #define TRNG_IRQFLAGMASK_RDY_M 0x00000001 197 #define TRNG_IRQFLAGMASK_RDY_S 0 198 199 //***************************************************************************** 200 // 201 // Register: TRNG_O_IRQFLAGCLR 202 // 203 //***************************************************************************** 204 // Field: [1] SHUTDOWN_OVF 205 // 206 // 1: Clear IRQFLAGSTAT.SHUTDOWN_OVF. 207 #define TRNG_IRQFLAGCLR_SHUTDOWN_OVF 0x00000002 208 #define TRNG_IRQFLAGCLR_SHUTDOWN_OVF_BITN 1 209 #define TRNG_IRQFLAGCLR_SHUTDOWN_OVF_M 0x00000002 210 #define TRNG_IRQFLAGCLR_SHUTDOWN_OVF_S 1 211 212 // Field: [0] RDY 213 // 214 // 1: Clear IRQFLAGSTAT.RDY. 215 #define TRNG_IRQFLAGCLR_RDY 0x00000001 216 #define TRNG_IRQFLAGCLR_RDY_BITN 0 217 #define TRNG_IRQFLAGCLR_RDY_M 0x00000001 218 #define TRNG_IRQFLAGCLR_RDY_S 0 219 220 //***************************************************************************** 221 // 222 // Register: TRNG_O_CTL 223 // 224 //***************************************************************************** 225 // Field: [31:16] STARTUP_CYCLES 226 // 227 // This field determines the number of samples (between 2^8 and 2^24) taken to 228 // gather entropy from the FROs during startup. If the written value of this 229 // field is zero, the number of samples is 2^24, otherwise the number of 230 // samples equals the written value times 2^8. 231 // 232 // 0x0000: 2^24 samples 233 // 0x0001: 1*2^8 samples 234 // 0x0002: 2*2^8 samples 235 // 0x0003: 3*2^8 samples 236 // ... 237 // 0x8000: 32768*2^8 samples 238 // 0xC000: 49152*2^8 samples 239 // ... 240 // 0xFFFF: 65535*2^8 samples 241 // 242 // This field can only be modified while TRNG_EN is 0. If 1 an update will be 243 // ignored. 244 #define TRNG_CTL_STARTUP_CYCLES_W 16 245 #define TRNG_CTL_STARTUP_CYCLES_M 0xFFFF0000 246 #define TRNG_CTL_STARTUP_CYCLES_S 16 247 248 // Field: [10] TRNG_EN 249 // 250 // 0: Forces all TRNG logic back into the idle state immediately. 251 // 1: Starts TRNG, gathering entropy from the FROs for the number of samples 252 // determined by STARTUP_CYCLES. 253 #define TRNG_CTL_TRNG_EN 0x00000400 254 #define TRNG_CTL_TRNG_EN_BITN 10 255 #define TRNG_CTL_TRNG_EN_M 0x00000400 256 #define TRNG_CTL_TRNG_EN_S 10 257 258 // Field: [2] NO_LFSR_FB 259 // 260 // 1: Remove XNOR feedback from the main LFSR, converting it into a normal 261 // shift register for the XOR-ed outputs of the FROs (shifting data in on the 262 // LSB side). A '1' also forces the LFSR to sample continuously. 263 // 264 // This bit can only be set to '1' when TEST_MODE is also set to '1' and should 265 // not be used for other than test purposes 266 #define TRNG_CTL_NO_LFSR_FB 0x00000004 267 #define TRNG_CTL_NO_LFSR_FB_BITN 2 268 #define TRNG_CTL_NO_LFSR_FB_M 0x00000004 269 #define TRNG_CTL_NO_LFSR_FB_S 2 270 271 // Field: [1] TEST_MODE 272 // 273 // 1: Enables access to the TESTCNT and LFSR0/LFSR1/LFSR2 registers (the latter 274 // are automatically cleared before enabling access) and keeps 275 // IRQFLAGSTAT.NEED_CLOCK at '1'. 276 // 277 // This bit shall not be used unless you need to change the LFSR seed prior to 278 // creating a new random value. All other testing is done external to register 279 // control. 280 #define TRNG_CTL_TEST_MODE 0x00000002 281 #define TRNG_CTL_TEST_MODE_BITN 1 282 #define TRNG_CTL_TEST_MODE_M 0x00000002 283 #define TRNG_CTL_TEST_MODE_S 1 284 285 //***************************************************************************** 286 // 287 // Register: TRNG_O_CFG0 288 // 289 //***************************************************************************** 290 // Field: [31:16] MAX_REFILL_CYCLES 291 // 292 // This field determines the maximum number of samples (between 2^8 and 2^24) 293 // taken to re-generate entropy from the FROs after reading out a 64 bits 294 // random number. If the written value of this field is zero, the number of 295 // samples is 2^24, otherwise the number of samples equals the written value 296 // times 2^8. 297 // 298 // 0x0000: 2^24 samples 299 // 0x0001: 1*2^8 samples 300 // 0x0002: 2*2^8 samples 301 // 0x0003: 3*2^8 samples 302 // ... 303 // 0x8000: 32768*2^8 samples 304 // 0xC000: 49152*2^8 samples 305 // ... 306 // 0xFFFF: 65535*2^8 samples 307 // 308 // This field can only be modified while CTL.TRNG_EN is 0. 309 #define TRNG_CFG0_MAX_REFILL_CYCLES_W 16 310 #define TRNG_CFG0_MAX_REFILL_CYCLES_M 0xFFFF0000 311 #define TRNG_CFG0_MAX_REFILL_CYCLES_S 16 312 313 // Field: [11:8] SMPL_DIV 314 // 315 // This field directly controls the number of clock cycles between samples 316 // taken from the FROs. Default value 0 indicates that samples are taken every 317 // clock cycle, 318 // maximum value 0xF takes one sample every 16 clock cycles. 319 // This field must be set to a value such that the slowest FRO (even under 320 // worst-case 321 // conditions) has a cycle time less than twice the sample period. 322 // 323 // This field can only be modified while CTL.TRNG_EN is '0'. 324 #define TRNG_CFG0_SMPL_DIV_W 4 325 #define TRNG_CFG0_SMPL_DIV_M 0x00000F00 326 #define TRNG_CFG0_SMPL_DIV_S 8 327 328 // Field: [7:0] MIN_REFILL_CYCLES 329 // 330 // This field determines the minimum number of samples (between 2^6 and 2^14) 331 // taken to re-generate entropy from the FROs after reading out a 64 bits 332 // random number. If the value of this field is zero, the number of samples is 333 // fixed to the value determined by the MAX_REFILL_CYCLES field, otherwise the 334 // minimum number of samples equals the written value times 64 (which can be up 335 // to 2^14). To ensure same entropy in all generated random numbers the value 0 336 // should be used. Then MAX_REFILL_CYCLES controls the minimum refill interval. 337 // The number of samples defined here cannot be higher than the number defined 338 // by the 'max_refill_cycles' field (i.e. that field takes precedence). No 339 // random value will be created if min refill > max refill. 340 // 341 // This field can only be modified while CTL.TRNG_EN = 0. 342 // 343 // 0x00: Minimum samples = MAX_REFILL_CYCLES (all numbers have same entropy) 344 // 0x01: 1*2^6 samples 345 // 0x02: 2*2^6 samples 346 // ... 347 // 0xFF: 255*2^6 samples 348 #define TRNG_CFG0_MIN_REFILL_CYCLES_W 8 349 #define TRNG_CFG0_MIN_REFILL_CYCLES_M 0x000000FF 350 #define TRNG_CFG0_MIN_REFILL_CYCLES_S 0 351 352 //***************************************************************************** 353 // 354 // Register: TRNG_O_ALARMCNT 355 // 356 //***************************************************************************** 357 // Field: [29:24] SHUTDOWN_CNT 358 // 359 // Read-only, indicates the number of '1' bits in ALARMSTOP register. 360 // The maximum value equals the number of FROs. 361 #define TRNG_ALARMCNT_SHUTDOWN_CNT_W 6 362 #define TRNG_ALARMCNT_SHUTDOWN_CNT_M 0x3F000000 363 #define TRNG_ALARMCNT_SHUTDOWN_CNT_S 24 364 365 // Field: [20:16] SHUTDOWN_THR 366 // 367 // Threshold setting for generating IRQFLAGSTAT.SHUTDOWN_OVF interrupt. The 368 // interrupt is triggered when SHUTDOWN_CNT value exceeds this bit field. 369 #define TRNG_ALARMCNT_SHUTDOWN_THR_W 5 370 #define TRNG_ALARMCNT_SHUTDOWN_THR_M 0x001F0000 371 #define TRNG_ALARMCNT_SHUTDOWN_THR_S 16 372 373 // Field: [7:0] ALARM_THR 374 // 375 // Alarm detection threshold for the repeating pattern detectors on each FRO. 376 // An FRO 'alarm event' is declared when a repeating pattern (of up to four 377 // samples length) is detected continuously for the number of samples defined 378 // by this field's value. Reset value 0xFF should keep the number of 'alarm 379 // events' to a manageable level. 380 #define TRNG_ALARMCNT_ALARM_THR_W 8 381 #define TRNG_ALARMCNT_ALARM_THR_M 0x000000FF 382 #define TRNG_ALARMCNT_ALARM_THR_S 0 383 384 //***************************************************************************** 385 // 386 // Register: TRNG_O_FROEN 387 // 388 //***************************************************************************** 389 // Field: [23:0] FRO_MASK 390 // 391 // Enable bits for the individual FROs. A '1' in bit [n] enables FRO 'n'. 392 // Default state is all '1's to enable all FROs after power-up. Note that they 393 // are not actually started up before the CTL.TRNG_EN bit is set to '1'. 394 // 395 // Bits are automatically forced to '0' here (and cannot be written to '1') 396 // while the corresponding bit in ALARMSTOP.FRO_FLAGS has value '1'. 397 #define TRNG_FROEN_FRO_MASK_W 24 398 #define TRNG_FROEN_FRO_MASK_M 0x00FFFFFF 399 #define TRNG_FROEN_FRO_MASK_S 0 400 401 //***************************************************************************** 402 // 403 // Register: TRNG_O_FRODETUNE 404 // 405 //***************************************************************************** 406 // Field: [23:0] FRO_MASK 407 // 408 // De-tune bits for the individual FROs. A '1' in bit [n] lets FRO 'n' run 409 // approximately 5% faster. The value of one of these bits may only be changed 410 // while the corresponding FRO is turned off (by temporarily writing a '0' in 411 // the corresponding 412 // bit of the FROEN.FRO_MASK register). 413 #define TRNG_FRODETUNE_FRO_MASK_W 24 414 #define TRNG_FRODETUNE_FRO_MASK_M 0x00FFFFFF 415 #define TRNG_FRODETUNE_FRO_MASK_S 0 416 417 //***************************************************************************** 418 // 419 // Register: TRNG_O_ALARMMASK 420 // 421 //***************************************************************************** 422 // Field: [23:0] FRO_MASK 423 // 424 // Logging bits for the 'alarm events' of individual FROs. A '1' in bit [n] 425 // indicates FRO 'n' experienced an 'alarm event'. 426 #define TRNG_ALARMMASK_FRO_MASK_W 24 427 #define TRNG_ALARMMASK_FRO_MASK_M 0x00FFFFFF 428 #define TRNG_ALARMMASK_FRO_MASK_S 0 429 430 //***************************************************************************** 431 // 432 // Register: TRNG_O_ALARMSTOP 433 // 434 //***************************************************************************** 435 // Field: [23:0] FRO_FLAGS 436 // 437 // Logging bits for the 'alarm events' of individual FROs. A '1' in bit [n] 438 // indicates FRO 'n' experienced more than one 'alarm event' in quick 439 // succession and has been turned off. A '1' in this field forces the 440 // corresponding bit in FROEN.FRO_MASK to '0'. 441 #define TRNG_ALARMSTOP_FRO_FLAGS_W 24 442 #define TRNG_ALARMSTOP_FRO_FLAGS_M 0x00FFFFFF 443 #define TRNG_ALARMSTOP_FRO_FLAGS_S 0 444 445 //***************************************************************************** 446 // 447 // Register: TRNG_O_LFSR0 448 // 449 //***************************************************************************** 450 // Field: [31:0] LFSR_31_0 451 // 452 // Bits [31:0] of the main entropy accumulation LFSR. Register can only be 453 // accessed when CTL.TEST_MODE = 1. 454 // Register contents will be cleared to zero before access is enabled. 455 #define TRNG_LFSR0_LFSR_31_0_W 32 456 #define TRNG_LFSR0_LFSR_31_0_M 0xFFFFFFFF 457 #define TRNG_LFSR0_LFSR_31_0_S 0 458 459 //***************************************************************************** 460 // 461 // Register: TRNG_O_LFSR1 462 // 463 //***************************************************************************** 464 // Field: [31:0] LFSR_63_32 465 // 466 // Bits [63:32] of the main entropy accumulation LFSR. Register can only be 467 // accessed when CTL.TEST_MODE = 1. 468 // Register contents will be cleared to zero before access is enabled. 469 #define TRNG_LFSR1_LFSR_63_32_W 32 470 #define TRNG_LFSR1_LFSR_63_32_M 0xFFFFFFFF 471 #define TRNG_LFSR1_LFSR_63_32_S 0 472 473 //***************************************************************************** 474 // 475 // Register: TRNG_O_LFSR2 476 // 477 //***************************************************************************** 478 // Field: [16:0] LFSR_80_64 479 // 480 // Bits [80:64] of the main entropy accumulation LFSR. Register can only be 481 // accessed when CTL.TEST_MODE = 1. 482 // Register contents will be cleared to zero before access is enabled. 483 #define TRNG_LFSR2_LFSR_80_64_W 17 484 #define TRNG_LFSR2_LFSR_80_64_M 0x0001FFFF 485 #define TRNG_LFSR2_LFSR_80_64_S 0 486 487 //***************************************************************************** 488 // 489 // Register: TRNG_O_HWOPT 490 // 491 //***************************************************************************** 492 // Field: [11:6] NR_OF_FROS 493 // 494 // Number of FROs implemented in this TRNG, value 24 (decimal). 495 #define TRNG_HWOPT_NR_OF_FROS_W 6 496 #define TRNG_HWOPT_NR_OF_FROS_M 0x00000FC0 497 #define TRNG_HWOPT_NR_OF_FROS_S 6 498 499 //***************************************************************************** 500 // 501 // Register: TRNG_O_HWVER0 502 // 503 //***************************************************************************** 504 // Field: [27:24] HW_MAJOR_VER 505 // 506 // 4 bits binary encoding of the major hardware revision number. 507 #define TRNG_HWVER0_HW_MAJOR_VER_W 4 508 #define TRNG_HWVER0_HW_MAJOR_VER_M 0x0F000000 509 #define TRNG_HWVER0_HW_MAJOR_VER_S 24 510 511 // Field: [23:20] HW_MINOR_VER 512 // 513 // 4 bits binary encoding of the minor hardware revision number. 514 #define TRNG_HWVER0_HW_MINOR_VER_W 4 515 #define TRNG_HWVER0_HW_MINOR_VER_M 0x00F00000 516 #define TRNG_HWVER0_HW_MINOR_VER_S 20 517 518 // Field: [19:16] HW_PATCH_LVL 519 // 520 // 4 bits binary encoding of the hardware patch level, initial release will 521 // carry value zero. 522 #define TRNG_HWVER0_HW_PATCH_LVL_W 4 523 #define TRNG_HWVER0_HW_PATCH_LVL_M 0x000F0000 524 #define TRNG_HWVER0_HW_PATCH_LVL_S 16 525 526 // Field: [15:8] EIP_NUM_COMPL 527 // 528 // Bit-by-bit logic complement of bits [7:0]. This TRNG gives 0xB4. 529 #define TRNG_HWVER0_EIP_NUM_COMPL_W 8 530 #define TRNG_HWVER0_EIP_NUM_COMPL_M 0x0000FF00 531 #define TRNG_HWVER0_EIP_NUM_COMPL_S 8 532 533 // Field: [7:0] EIP_NUM 534 // 535 // 8 bits binary encoding of the module number. This TRNG gives 0x4B. 536 #define TRNG_HWVER0_EIP_NUM_W 8 537 #define TRNG_HWVER0_EIP_NUM_M 0x000000FF 538 #define TRNG_HWVER0_EIP_NUM_S 0 539 540 //***************************************************************************** 541 // 542 // Register: TRNG_O_IRQSTATMASK 543 // 544 //***************************************************************************** 545 // Field: [1] SHUTDOWN_OVF 546 // 547 // Shutdown Overflow (result of IRQFLAGSTAT.SHUTDOWN_OVF AND'ed with 548 // IRQFLAGMASK.SHUTDOWN_OVF) 549 #define TRNG_IRQSTATMASK_SHUTDOWN_OVF 0x00000002 550 #define TRNG_IRQSTATMASK_SHUTDOWN_OVF_BITN 1 551 #define TRNG_IRQSTATMASK_SHUTDOWN_OVF_M 0x00000002 552 #define TRNG_IRQSTATMASK_SHUTDOWN_OVF_S 1 553 554 // Field: [0] RDY 555 // 556 // New random value available (result of IRQFLAGSTAT.RDY AND'ed with 557 // IRQFLAGMASK.RDY) 558 #define TRNG_IRQSTATMASK_RDY 0x00000001 559 #define TRNG_IRQSTATMASK_RDY_BITN 0 560 #define TRNG_IRQSTATMASK_RDY_M 0x00000001 561 #define TRNG_IRQSTATMASK_RDY_S 0 562 563 //***************************************************************************** 564 // 565 // Register: TRNG_O_HWVER1 566 // 567 //***************************************************************************** 568 // Field: [7:0] REV 569 // 570 // The revision number of this module is Rev 2.0. 571 #define TRNG_HWVER1_REV_W 8 572 #define TRNG_HWVER1_REV_M 0x000000FF 573 #define TRNG_HWVER1_REV_S 0 574 575 //***************************************************************************** 576 // 577 // Register: TRNG_O_IRQSET 578 // 579 //***************************************************************************** 580 //***************************************************************************** 581 // 582 // Register: TRNG_O_SWRESET 583 // 584 //***************************************************************************** 585 // Field: [0] RESET 586 // 587 // Write '1' to soft reset , reset will be low for 4-5 clock cycles. Poll to 0 588 // for reset to be completed. 589 #define TRNG_SWRESET_RESET 0x00000001 590 #define TRNG_SWRESET_RESET_BITN 0 591 #define TRNG_SWRESET_RESET_M 0x00000001 592 #define TRNG_SWRESET_RESET_S 0 593 594 //***************************************************************************** 595 // 596 // Register: TRNG_O_IRQSTAT 597 // 598 //***************************************************************************** 599 // Field: [0] STAT 600 // 601 // TRNG Interrupt status. OR'ed version of IRQFLAGSTAT.SHUTDOWN_OVF and 602 // IRQFLAGSTAT.RDY 603 #define TRNG_IRQSTAT_STAT 0x00000001 604 #define TRNG_IRQSTAT_STAT_BITN 0 605 #define TRNG_IRQSTAT_STAT_M 0x00000001 606 #define TRNG_IRQSTAT_STAT_S 0 607 608 609 #endif // __TRNG__ 610