1 /******************************************************************************
2 * Filename: startup_gcc.c
3 * Revised: $Date: 2015-11-20 13:29:27 +0100 (fr, 20 nov 2015) $
4 * Revision: $Revision: 16380 $
5 *
6 * Description: Startup code for CC13xx PG2 device family for use with GCC.
7 *
8 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
9 *
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 *
18 * Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution.
21 *
22 * Neither the name of Texas Instruments Incorporated nor the names of
23 * its contributors may be used to endorse or promote products derived
24 * from this software without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 *
38 ******************************************************************************/
39
40 //*****************************************************************************
41 //
42 // Check if compiler is GNU Compiler
43 //
44 //*****************************************************************************
45 #if !(defined(__GNUC__))
46 #error "startup_gcc.c: Unsupported compiler!"
47 #endif
48
49 #include <inc/hw_types.h>
50
51
52 //*****************************************************************************
53 //
54 // Macro for weak symbol aliasing
55 //
56 //*****************************************************************************
57 #define WEAK_ALIAS(x) __attribute__ ((weak, alias(#x)))
58
59 //*****************************************************************************
60 //
61 // Forward declaration of the reset ISR and the default fault handlers.
62 //
63 //*****************************************************************************
64 void ResetISR( void );
65 static void NmiSRHandler( void );
66 static void FaultISRHandler( void );
67 static void IntDefaultHandler( void );
68 extern int main( void );
69
70
71 // Default interrupt handlers
72 void NmiSR(void) WEAK_ALIAS(NmiSRHandler);
73 void FaultISR(void) WEAK_ALIAS(FaultISRHandler);
74 void MPUFaultIntHandler(void) WEAK_ALIAS(IntDefaultHandler);
75 void BusFaultIntHandler(void) WEAK_ALIAS(IntDefaultHandler);
76 void UsageFaultIntHandler(void) WEAK_ALIAS(IntDefaultHandler);
77 void SVCallIntHandler(void) WEAK_ALIAS(IntDefaultHandler);
78 void DebugMonIntHandler(void) WEAK_ALIAS(IntDefaultHandler);
79 void PendSVIntHandler(void) WEAK_ALIAS(IntDefaultHandler);
80 void SysTickIntHandler(void) WEAK_ALIAS(IntDefaultHandler);
81 void GPIOIntHandler(void) WEAK_ALIAS(IntDefaultHandler);
82 void I2CIntHandler(void) WEAK_ALIAS(IntDefaultHandler);
83 void RFCCPE1IntHandler(void) WEAK_ALIAS(IntDefaultHandler);
84 void AONIntHandler(void) WEAK_ALIAS(IntDefaultHandler);
85 void AONRTCIntHandler(void) WEAK_ALIAS(IntDefaultHandler);
86 void UART0IntHandler(void) WEAK_ALIAS(IntDefaultHandler);
87 void AUXSWEvent0IntHandler(void) WEAK_ALIAS(IntDefaultHandler);
88 void SSI0IntHandler(void) WEAK_ALIAS(IntDefaultHandler);
89 void SSI1IntHandler(void) WEAK_ALIAS(IntDefaultHandler);
90 void RFCCPE0IntHandler(void) WEAK_ALIAS(IntDefaultHandler);
91 void RFCHardwareIntHandler(void) WEAK_ALIAS(IntDefaultHandler);
92 void RFCCmdAckIntHandler(void) WEAK_ALIAS(IntDefaultHandler);
93 void I2SIntHandler(void) WEAK_ALIAS(IntDefaultHandler);
94 void AUXSWEvent1IntHandler(void) WEAK_ALIAS(IntDefaultHandler);
95 void WatchdogIntHandler(void) WEAK_ALIAS(IntDefaultHandler);
96 void Timer0AIntHandler(void) WEAK_ALIAS(IntDefaultHandler);
97 void Timer0BIntHandler(void) WEAK_ALIAS(IntDefaultHandler);
98 void Timer1AIntHandler(void) WEAK_ALIAS(IntDefaultHandler);
99 void Timer1BIntHandler(void) WEAK_ALIAS(IntDefaultHandler);
100 void Timer2AIntHandler(void) WEAK_ALIAS(IntDefaultHandler);
101 void Timer2BIntHandler(void) WEAK_ALIAS(IntDefaultHandler);
102 void Timer3AIntHandler(void) WEAK_ALIAS(IntDefaultHandler);
103 void Timer3BIntHandler(void) WEAK_ALIAS(IntDefaultHandler);
104 void CryptoIntHandler(void) WEAK_ALIAS(IntDefaultHandler);
105 void uDMAIntHandler(void) WEAK_ALIAS(IntDefaultHandler);
106 void uDMAErrIntHandler(void) WEAK_ALIAS(IntDefaultHandler);
107 void FlashIntHandler(void) WEAK_ALIAS(IntDefaultHandler);
108 void SWEvent0IntHandler(void) WEAK_ALIAS(IntDefaultHandler);
109 void AUXCombEventIntHandler(void) WEAK_ALIAS(IntDefaultHandler);
110 void AONProgIntHandler(void) WEAK_ALIAS(IntDefaultHandler);
111 void DynProgIntHandler(void) WEAK_ALIAS(IntDefaultHandler);
112 void AUXCompAIntHandler(void) WEAK_ALIAS(IntDefaultHandler);
113 void AUXADCIntHandler(void) WEAK_ALIAS(IntDefaultHandler);
114 void TRNGIntHandler(void) WEAK_ALIAS(IntDefaultHandler);
115
116 //*****************************************************************************
117 //
118 //! The entry point for the device trim fxn.
119 //
120 //*****************************************************************************
121 extern void trimDevice(void);
122
123 //*****************************************************************************
124 //
125 // The following are constructs created by the linker, indicating where the
126 // the "data" and "bss" segments reside in memory.
127 //
128 //*****************************************************************************
129 extern uint32_t _etext;
130 extern uint32_t _data;
131 extern uint32_t _edata;
132 extern uint32_t _bss;
133 extern uint32_t _ebss;
134 extern uint32_t _estack;
135
136 //*****************************************************************************
137 //
138 //! The vector table. Note that the proper constructs must be placed on this to
139 //! ensure that it ends up at physical address 0x0000.0000 or at the start of
140 //! the program if located at a start address other than 0.
141 //
142 //*****************************************************************************
143 __attribute__ ((section(".vectors"), used))
144 void (* const g_pfnVectors[])(void) =
145 {
146 (void (*)(void))&_estack, // The initial stack pointer
147 ResetISR, // The reset handler
148 NmiSR, // The NMI handler
149 FaultISR, // The hard fault handler
150 MPUFaultIntHandler, // The MPU fault handler
151 BusFaultIntHandler, // The bus fault handler
152 UsageFaultIntHandler, // The usage fault handler
153 0, // Reserved
154 0, // Reserved
155 0, // Reserved
156 0, // Reserved
157 SVCallIntHandler, // SVCall handler
158 DebugMonIntHandler, // Debug monitor handler
159 0, // Reserved
160 PendSVIntHandler, // The PendSV handler
161 SysTickIntHandler, // The SysTick handler
162 GPIOIntHandler, // AON edge detect
163 I2CIntHandler, // I2C
164 RFCCPE1IntHandler, // RF Core Command & Packet Engine 1
165 AONIntHandler, // AON SpiSplave Rx, Tx and CS
166 AONRTCIntHandler, // AON RTC
167 UART0IntHandler, // UART0 Rx and Tx
168 AUXSWEvent0IntHandler, // AUX software event 0
169 SSI0IntHandler, // SSI0 Rx and Tx
170 SSI1IntHandler, // SSI1 Rx and Tx
171 RFCCPE0IntHandler, // RF Core Command & Packet Engine 0
172 RFCHardwareIntHandler, // RF Core Hardware
173 RFCCmdAckIntHandler, // RF Core Command Acknowledge
174 I2SIntHandler, // I2S
175 AUXSWEvent1IntHandler, // AUX software event 1
176 WatchdogIntHandler, // Watchdog timer
177 Timer0AIntHandler, // Timer 0 subtimer A
178 Timer0BIntHandler, // Timer 0 subtimer B
179 Timer1AIntHandler, // Timer 1 subtimer A
180 Timer1BIntHandler, // Timer 1 subtimer B
181 Timer2AIntHandler, // Timer 2 subtimer A
182 Timer2BIntHandler, // Timer 2 subtimer B
183 Timer3AIntHandler, // Timer 3 subtimer A
184 Timer3BIntHandler, // Timer 3 subtimer B
185 CryptoIntHandler, // Crypto Core Result available
186 uDMAIntHandler, // uDMA Software
187 uDMAErrIntHandler, // uDMA Error
188 FlashIntHandler, // Flash controller
189 SWEvent0IntHandler, // Software Event 0
190 AUXCombEventIntHandler, // AUX combined event
191 AONProgIntHandler, // AON programmable 0
192 DynProgIntHandler, // Dynamic Programmable interrupt
193 // source (Default: PRCM)
194 AUXCompAIntHandler, // AUX Comparator A
195 AUXADCIntHandler, // AUX ADC new sample or ADC DMA
196 // done, ADC underflow, ADC overflow
197 TRNGIntHandler // TRNG event
198 };
199
200
201 //*****************************************************************************
202 //
203 //! This is the code that gets called when the processor first starts execution
204 //! following a reset event. Only the absolutely necessary set is performed,
205 //! after which the application supplied entry() routine is called. Any fancy
206 //! actions (such as making decisions based on the reset cause register, and
207 //! resetting the bits in that register) are left solely in the hands of the
208 //! application.
209 //
210 //*****************************************************************************
211 void
ResetISR(void)212 ResetISR(void)
213 {
214 uint32_t *pui32Src, *pui32Dest;
215
216 //
217 // Final trim of device
218 //
219 trimDevice();
220
221 //
222 // Copy the data segment initializers from flash to SRAM.
223 //
224 pui32Src = &_etext;
225 for(pui32Dest = &_data; pui32Dest < &_edata; )
226 {
227 *pui32Dest++ = *pui32Src++;
228 }
229
230 //
231 // Zero fill the bss segment.
232 //
233 __asm(" ldr r0, =_bss\n"
234 " ldr r1, =_ebss\n"
235 " mov r2, #0\n"
236 " .thumb_func\n"
237 "zero_loop:\n"
238 " cmp r0, r1\n"
239 " it lt\n"
240 " strlt r2, [r0], #4\n"
241 " blt zero_loop");
242
243 //
244 // Call the application's entry point.
245 //
246 main();
247
248 //
249 // If we ever return signal Error
250 //
251 FaultISR();
252 }
253
254 //*****************************************************************************
255 //
256 //! This is the code that gets called when the processor receives a NMI. This
257 //! simply enters an infinite loop, preserving the system state for examination
258 //! by a debugger.
259 //
260 //*****************************************************************************
261 static void
NmiSRHandler(void)262 NmiSRHandler(void)
263 {
264 //
265 // Enter an infinite loop.
266 //
267 while(1)
268 {
269 }
270 }
271
272 //*****************************************************************************
273 //
274 //! This is the code that gets called when the processor receives a fault
275 //! interrupt. This simply enters an infinite loop, preserving the system state
276 //! for examination by a debugger.
277 //
278 //*****************************************************************************
279 static void
FaultISRHandler(void)280 FaultISRHandler(void)
281 {
282 //
283 // Enter an infinite loop.
284 //
285 while(1)
286 {
287 }
288 }
289
290 //*****************************************************************************
291 //
292 //! This is the code that gets called when the processor receives an unexpected
293 //! interrupt. This simply enters an infinite loop, preserving the system state
294 //! for examination by a debugger.
295 //
296 //*****************************************************************************
297 static void
IntDefaultHandler(void)298 IntDefaultHandler(void)
299 {
300 //
301 // Go into an infinite loop.
302 //
303 while(1)
304 {
305 }
306 }
307