1 /* 2 * @brief Basic CMSIS include file for LPC15xx 3 * 4 * @note 5 * Copyright(C) NXP Semiconductors, 2014 6 * All rights reserved. 7 * 8 * @par 9 * Software that is described herein is for illustrative purposes only 10 * which provides customers with programming information regarding the 11 * LPC products. This software is supplied "AS IS" without any warranties of 12 * any kind, and NXP Semiconductors and its licensor disclaim any and 13 * all warranties, express or implied, including all implied warranties of 14 * merchantability, fitness for a particular purpose and non-infringement of 15 * intellectual property rights. NXP Semiconductors assumes no responsibility 16 * or liability for the use of the software, conveys no license or rights under any 17 * patent, copyright, mask work right, or any other intellectual property rights in 18 * or to any products. NXP Semiconductors reserves the right to make changes 19 * in the software without notification. NXP Semiconductors also makes no 20 * representation or warranty that such application will be suitable for the 21 * specified use without further testing or modification. 22 * 23 * @par 24 * Permission to use, copy, modify, and distribute this software and its 25 * documentation is hereby granted, under NXP Semiconductors' and its 26 * licensor's relevant copyrights in the software, without fee, provided that it 27 * is used in conjunction with NXP Semiconductors microcontrollers. This 28 * copyright, permission, and disclaimer notice must appear in all copies of 29 * this code. 30 */ 31 32 #ifndef __CMSIS_15XX_H_ 33 #define __CMSIS_15XX_H_ 34 35 #include "lpc_types.h" 36 #include "sys_config.h" 37 38 #ifdef __cplusplus 39 extern "C" { 40 #endif 41 42 /** @defgroup CMSIS_LPC15XX CHIP: LPC15xx CMSIS include file 43 * @ingroup CHIP_15XX_CMSIS_Drivers 44 * @{ 45 */ 46 47 #if defined(__ARMCC_VERSION) 48 // Kill warning "#pragma push with no matching #pragma pop" 49 #pragma diag_suppress 2525 50 #pragma push 51 #pragma anon_unions 52 #elif defined(__CWCC__) 53 #pragma push 54 #pragma cpp_extensions on 55 #elif defined(__GNUC__) 56 /* anonymous unions are enabled by default */ 57 #elif defined(__IAR_SYSTEMS_ICC__) 58 // #pragma push // FIXME not usable for IAR 59 #pragma language=extended 60 #else 61 #error Not supported compiler type 62 #endif 63 64 /* 65 * ========================================================================== 66 * ---------- Interrupt Number Definition ----------------------------------- 67 * ========================================================================== 68 */ 69 70 #if !defined(CHIP_LPC15XX) 71 #error Incorrect or missing device variant (CHIP_LPC15XX) 72 #endif 73 74 /** @defgroup CMSIS_15XX_IRQ CHIP: LPC15xx peripheral interrupt numbers 75 * @{ 76 */ 77 78 typedef enum IRQn { 79 Reset_IRQn = -15, /*!< Reset Vector, invoked on Power up and warm reset */ 80 NonMaskableInt_IRQn = -14, /*!< Non maskable Interrupt, cannot be stopped or preempted */ 81 HardFault_IRQn = -13, /*!< Hard Fault, all classes of Fault */ 82 MemoryManagement_IRQn = -12, /*!< Memory Management, MPU mismatch, including Access Violation and No Match */ 83 BusFault_IRQn = -11, /*!< Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ 84 UsageFault_IRQn = -10, /*!< Usage Fault, i.e. Undef Instruction, Illegal State Transition */ 85 SVCall_IRQn = -5, /*!< System Service Call via SVC instruction */ 86 DebugMonitor_IRQn = -4, /*!< Debug Monitor */ 87 PendSV_IRQn = -2, /*!< Pendable request for system service */ 88 SysTick_IRQn = -1, /*!< System Tick Timer */ 89 90 WDT_IRQn = 0, /*!< Watchdog timer Interrupt */ 91 WWDT_IRQn = WDT_IRQn, /*!< Watchdog timer Interrupt alias for WDT_IRQn */ 92 BOD_IRQn = 1, /*!< Brown Out Detect(BOD) Interrupt */ 93 FMC_IRQn = 2, /*!< FLASH Interrupt */ 94 FLASHEEPROM_IRQn = 3, /*!< EEPROM controller interrupt */ 95 DMA_IRQn = 4, /*!< DMA Interrupt */ 96 GINT0_IRQn = 5, /*!< GPIO group 0 Interrupt */ 97 GINT1_IRQn = 6, /*!< GPIO group 1 Interrupt */ 98 PIN_INT0_IRQn = 7, /*!< Pin Interrupt 0 */ 99 PIN_INT1_IRQn = 8, /*!< Pin Interrupt 1 */ 100 PIN_INT2_IRQn = 9, /*!< Pin Interrupt 2 */ 101 PIN_INT3_IRQn = 10, /*!< Pin Interrupt 3 */ 102 PIN_INT4_IRQn = 11, /*!< Pin Interrupt 4 */ 103 PIN_INT5_IRQn = 12, /*!< Pin Interrupt 5 */ 104 PIN_INT6_IRQn = 13, /*!< Pin Interrupt 6 */ 105 PIN_INT7_IRQn = 14, /*!< Pin Interrupt 7 */ 106 RITIMER_IRQn = 15, /*!< RITIMER interrupt */ 107 SCT0_IRQn = 16, /*!< SCT0 interrupt */ 108 SCT_IRQn = SCT0_IRQn, /*!< Optional alias for SCT0_IRQn */ 109 SCT1_IRQn = 17, /*!< SCT1 interrupt */ 110 SCT2_IRQn = 18, /*!< SCT2 interrupt */ 111 SCT3_IRQn = 19, /*!< SCT3 interrupt */ 112 MRT_IRQn = 20, /*!< MRT interrupt */ 113 UART0_IRQn = 21, /*!< UART0 Interrupt */ 114 UART1_IRQn = 22, /*!< UART1 Interrupt */ 115 UART2_IRQn = 23, /*!< UART2 Interrupt */ 116 I2C0_IRQn = 24, /*!< I2C0 Interrupt */ 117 I2C_IRQn = I2C0_IRQn, /*!< Optional alias for I2C0_IRQn */ 118 SPI0_IRQn = 25, /*!< SPI0 Interrupt */ 119 SPI1_IRQn = 26, /*!< SPI1 Interrupt */ 120 CAN_IRQn = 27, /*!< CAN Interrupt */ 121 USB0_IRQn = 28, /*!< USB IRQ interrupt */ 122 USB_IRQn = USB0_IRQn, /*!< Optional alias for USB0_IRQn */ 123 USB0_FIQ_IRQn = 29, /*!< USB FIQ interrupt */ 124 USB_FIQ_IRQn = USB0_FIQ_IRQn, /*!< Optional alias for USB0_FIQ_IRQn */ 125 USB_WAKEUP_IRQn = 30, /*!< USB wake-up interrupt Interrupt */ 126 ADC0_SEQA_IRQn = 31, /*!< ADC0_A sequencer Interrupt */ 127 ADC0_A_IRQn = ADC0_SEQA_IRQn, /*!< Optional alias for ADC0_SEQA_IRQn */ 128 ADC_A_IRQn = ADC0_SEQA_IRQn, /*!< Optional alias for ADC0_SEQA_IRQn */ 129 ADC0_SEQB_IRQn = 32, /*!< ADC0_B sequencer Interrupt */ 130 ADC0_B_IRQn = ADC0_SEQB_IRQn, /*!< Optional alias for ADC0_SEQB_IRQn */ 131 ADC_B_IRQn = ADC0_SEQB_IRQn, /*!< Optional alias for ADC0_SEQB_IRQn */ 132 ADC0_THCMP = 33, /*!< ADC0 threshold compare interrupt */ 133 ADC0_OVR = 34, /*!< ADC0 overrun interrupt */ 134 ADC1_SEQA_IRQn = 35, /*!< ADC1_A sequencer Interrupt */ 135 ADC1_A_IRQn = ADC1_SEQA_IRQn, /*!< Optional alias for ADC1_SEQA_IRQn */ 136 ADC1_SEQB_IRQn = 36, /*!< ADC1_B sequencer Interrupt */ 137 ADC1_B_IRQn = ADC1_SEQB_IRQn, /*!< Optional alias for ADC1_SEQB_IRQn */ 138 ADC1_THCMP = 37, /*!< ADC1 threshold compare interrupt */ 139 ADC1_OVR = 38, /*!< ADC1 overrun interrupt */ 140 DAC_IRQ = 39, /*!< DAC interrupt */ 141 CMP0_IRQ = 40, /*!< Analog comparator 0 interrupt */ 142 CMP_IRQn = CMP0_IRQ, /*!< Optional alias for CMP0_IRQ */ 143 CMP1_IRQ = 41, /*!< Analog comparator 1 interrupt */ 144 CMP2_IRQ = 42, /*!< Analog comparator 2 interrupt */ 145 CMP3_IRQ = 43, /*!< Analog comparator 3 interrupt */ 146 QEI_IRQn = 44, /*!< QEI interrupt */ 147 RTC_ALARM_IRQn = 45, /*!< RTC alarm interrupt */ 148 RTC_WAKE_IRQn = 46, /*!< RTC wake-up interrupt */ 149 } IRQn_Type; 150 151 /** 152 * @} 153 */ 154 155 /* 156 * ========================================================================== 157 * ----------- Processor and Core Peripheral Section ------------------------ 158 * ========================================================================== 159 */ 160 161 /** @defgroup CMSIS_15XX_COMMON CHIP: LPC15xx Cortex CMSIS definitions 162 * @{ 163 */ 164 165 #define __CM3_REV 0x0201 /*!< Cortex-M3 Core Revision */ 166 #define __MPU_PRESENT 0 /*!< MPU present or not */ 167 #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ 168 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 169 #define __FPU_PRESENT 0 /*!< FPU present or not */ 170 171 /** 172 * @} 173 */ 174 175 #include "core_cm3.h" /*!< Cortex-M3 processor and core peripherals */ 176 177 /** 178 * @} 179 */ 180 181 #ifdef __cplusplus 182 } 183 #endif 184 185 #endif /* __CMSIS_15XX_H_ */ 186