1 /*
2 * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice, this
9 * list of conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * 3. Neither the name of the copyright holder nor the names of its
16 * contributors may be used to endorse or promote products derived from this
17 * software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #ifndef NRF_PPI_H__
33 #define NRF_PPI_H__
34
35 #include <nrfx.h>
36
37 #ifdef __cplusplus
38 extern "C" {
39 #endif
40
41 /**
42 * @defgroup nrf_ppi_hal PPI HAL
43 * @{
44 * @ingroup nrf_ppi
45 * @brief Hardware access layer (HAL) for managing the Programmable Peripheral Interconnect (PPI)
46 * channels.
47 */
48
49 /** @brief PPI channels. */
50 typedef enum
51 {
52 NRF_PPI_CHANNEL0 = PPI_CHEN_CH0_Pos, /**< Channel 0. */
53 NRF_PPI_CHANNEL1 = PPI_CHEN_CH1_Pos, /**< Channel 1. */
54 NRF_PPI_CHANNEL2 = PPI_CHEN_CH2_Pos, /**< Channel 2. */
55 NRF_PPI_CHANNEL3 = PPI_CHEN_CH3_Pos, /**< Channel 3. */
56 NRF_PPI_CHANNEL4 = PPI_CHEN_CH4_Pos, /**< Channel 4. */
57 NRF_PPI_CHANNEL5 = PPI_CHEN_CH5_Pos, /**< Channel 5. */
58 NRF_PPI_CHANNEL6 = PPI_CHEN_CH6_Pos, /**< Channel 6. */
59 NRF_PPI_CHANNEL7 = PPI_CHEN_CH7_Pos, /**< Channel 7. */
60 NRF_PPI_CHANNEL8 = PPI_CHEN_CH8_Pos, /**< Channel 8. */
61 NRF_PPI_CHANNEL9 = PPI_CHEN_CH9_Pos, /**< Channel 9. */
62 #if (PPI_CH_NUM > 10) || defined(__NRFX_DOXYGEN__)
63 NRF_PPI_CHANNEL10 = PPI_CHEN_CH10_Pos, /**< Channel 10. */
64 NRF_PPI_CHANNEL11 = PPI_CHEN_CH11_Pos, /**< Channel 11. */
65 NRF_PPI_CHANNEL12 = PPI_CHEN_CH12_Pos, /**< Channel 12. */
66 NRF_PPI_CHANNEL13 = PPI_CHEN_CH13_Pos, /**< Channel 13. */
67 NRF_PPI_CHANNEL14 = PPI_CHEN_CH14_Pos, /**< Channel 14. */
68 NRF_PPI_CHANNEL15 = PPI_CHEN_CH15_Pos, /**< Channel 15. */
69 #endif
70 #if (PPI_CH_NUM > 16) || defined(__NRFX_DOXYGEN__)
71 NRF_PPI_CHANNEL16 = PPI_CHEN_CH16_Pos, /**< Channel 16. */
72 NRF_PPI_CHANNEL17 = PPI_CHEN_CH17_Pos, /**< Channel 17. */
73 NRF_PPI_CHANNEL18 = PPI_CHEN_CH18_Pos, /**< Channel 18. */
74 NRF_PPI_CHANNEL19 = PPI_CHEN_CH19_Pos, /**< Channel 19. */
75 #endif
76 NRF_PPI_CHANNEL20 = PPI_CHEN_CH20_Pos, /**< Channel 20. */
77 NRF_PPI_CHANNEL21 = PPI_CHEN_CH21_Pos, /**< Channel 21. */
78 NRF_PPI_CHANNEL22 = PPI_CHEN_CH22_Pos, /**< Channel 22. */
79 NRF_PPI_CHANNEL23 = PPI_CHEN_CH23_Pos, /**< Channel 23. */
80 NRF_PPI_CHANNEL24 = PPI_CHEN_CH24_Pos, /**< Channel 24. */
81 NRF_PPI_CHANNEL25 = PPI_CHEN_CH25_Pos, /**< Channel 25. */
82 NRF_PPI_CHANNEL26 = PPI_CHEN_CH26_Pos, /**< Channel 26. */
83 NRF_PPI_CHANNEL27 = PPI_CHEN_CH27_Pos, /**< Channel 27. */
84 NRF_PPI_CHANNEL28 = PPI_CHEN_CH28_Pos, /**< Channel 28. */
85 NRF_PPI_CHANNEL29 = PPI_CHEN_CH29_Pos, /**< Channel 29. */
86 NRF_PPI_CHANNEL30 = PPI_CHEN_CH30_Pos, /**< Channel 30. */
87 NRF_PPI_CHANNEL31 = PPI_CHEN_CH31_Pos /**< Channel 31. */
88 } nrf_ppi_channel_t;
89
90 /** @brief PPI channel groups. */
91 typedef enum
92 {
93 NRF_PPI_CHANNEL_GROUP0 = 0, /**< Channel group 0. */
94 NRF_PPI_CHANNEL_GROUP1 = 1, /**< Channel group 1. */
95 NRF_PPI_CHANNEL_GROUP2 = 2, /**< Channel group 2. */
96 NRF_PPI_CHANNEL_GROUP3 = 3, /**< Channel group 3. */
97 #if (PPI_GROUP_NUM > 4) || defined(__NRFX_DOXYGEN__)
98 NRF_PPI_CHANNEL_GROUP4 = 4, /**< Channel group 4. */
99 NRF_PPI_CHANNEL_GROUP5 = 5 /**< Channel group 5. */
100 #endif
101 } nrf_ppi_channel_group_t;
102
103 /** @brief Definition of whether a PPI channel belongs to a group. */
104 typedef enum
105 {
106 NRF_PPI_CHANNEL_EXCLUDE = PPI_CHG_CH0_Excluded, /**< Channel excluded from a group. */
107 NRF_PPI_CHANNEL_INCLUDE = PPI_CHG_CH0_Included /**< Channel included in a group. */
108 } nrf_ppi_channel_include_t;
109
110 /** @brief Definition of whether a PPI channel is enabled. */
111 typedef enum
112 {
113 NRF_PPI_CHANNEL_DISABLED = PPI_CHEN_CH0_Disabled, /**< Channel disabled. */
114 NRF_PPI_CHANNEL_ENABLED = PPI_CHEN_CH0_Enabled /**< Channel enabled. */
115 } nrf_ppi_channel_enable_t;
116
117 /** @brief PPI tasks. */
118 typedef enum
119 {
120 NRF_PPI_TASK_CHG0_EN = offsetof(NRF_PPI_Type, TASKS_CHG[0].EN), /**< Task for enabling channel group 0. */
121 NRF_PPI_TASK_CHG0_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[0].DIS), /**< Task for disabling channel group 0. */
122 NRF_PPI_TASK_CHG1_EN = offsetof(NRF_PPI_Type, TASKS_CHG[1].EN), /**< Task for enabling channel group 1. */
123 NRF_PPI_TASK_CHG1_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[1].DIS), /**< Task for disabling channel group 1. */
124 NRF_PPI_TASK_CHG2_EN = offsetof(NRF_PPI_Type, TASKS_CHG[2].EN), /**< Task for enabling channel group 2. */
125 NRF_PPI_TASK_CHG2_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[2].DIS), /**< Task for disabling channel group 2. */
126 NRF_PPI_TASK_CHG3_EN = offsetof(NRF_PPI_Type, TASKS_CHG[3].EN), /**< Task for enabling channel group 3. */
127 NRF_PPI_TASK_CHG3_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[3].DIS), /**< Task for disabling channel group 3. */
128 #if (PPI_GROUP_NUM > 4) || defined(__NRFX_DOXYGEN__)
129 NRF_PPI_TASK_CHG4_EN = offsetof(NRF_PPI_Type, TASKS_CHG[4].EN), /**< Task for enabling channel group 4. */
130 NRF_PPI_TASK_CHG4_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[4].DIS), /**< Task for disabling channel group 4. */
131 NRF_PPI_TASK_CHG5_EN = offsetof(NRF_PPI_Type, TASKS_CHG[5].EN), /**< Task for enabling channel group 5. */
132 NRF_PPI_TASK_CHG5_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[5].DIS) /**< Task for disabling channel group 5. */
133 #endif
134 } nrf_ppi_task_t;
135
136
137 /**
138 * @brief Function for enabling a given PPI channel.
139 *
140 * @details This function enables only one channel.
141 *
142 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
143 * @param[in] channel Channel to be enabled.
144 */
145 NRF_STATIC_INLINE void nrf_ppi_channel_enable(NRF_PPI_Type * p_reg, nrf_ppi_channel_t channel);
146
147 /**
148 * @brief Function for disabling a given PPI channel.
149 *
150 * @details This function disables only one channel.
151 *
152 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
153 * @param[in] channel Channel to be disabled.
154 */
155 NRF_STATIC_INLINE void nrf_ppi_channel_disable(NRF_PPI_Type * p_reg, nrf_ppi_channel_t channel);
156
157 /**
158 * @brief Function for checking if a given PPI channel is enabled.
159 *
160 * @details This function checks only one channel.
161 *
162 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
163 * @param[in] channel Channel to be checked.
164 *
165 * @retval NRF_PPI_CHANNEL_ENABLED The channel is enabled.
166 * @retval NRF_PPI_CHANNEL_DISABLED The channel is not enabled.
167 *
168 */
169 NRF_STATIC_INLINE nrf_ppi_channel_enable_t nrf_ppi_channel_enable_get(NRF_PPI_Type const * p_reg,
170 nrf_ppi_channel_t channel);
171
172 /**
173 * @brief Function for disabling all PPI channels.
174 *
175 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
176 */
177 NRF_STATIC_INLINE void nrf_ppi_channels_disable_all(NRF_PPI_Type * p_reg);
178
179 /**
180 * @brief Function for enabling multiple PPI channels.
181 *
182 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
183 * @param[in] mask Channel mask.
184 */
185 NRF_STATIC_INLINE void nrf_ppi_channels_enable(NRF_PPI_Type * p_reg, uint32_t mask);
186
187 /**
188 * @brief Function for disabling multiple PPI channels.
189 *
190 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
191 * @param[in] mask Channel mask.
192 */
193 NRF_STATIC_INLINE void nrf_ppi_channels_disable(NRF_PPI_Type * p_reg, uint32_t mask);
194
195 /**
196 * @brief Function for setting up event and task endpoints for a given PPI channel.
197 *
198 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
199 * @param[in] eep Event register address.
200 * @param[in] tep Task register address.
201 * @param[in] channel Channel to which the given endpoints are assigned.
202 */
203 NRF_STATIC_INLINE void nrf_ppi_channel_endpoint_setup(NRF_PPI_Type * p_reg,
204 nrf_ppi_channel_t channel,
205 uint32_t eep,
206 uint32_t tep);
207
208 /**
209 * @brief Function for setting up the event endpoint for a given PPI channel.
210 *
211 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
212 * @param[in] eep Event register address.
213 * @param[in] channel Channel to which the given endpoint is assigned.
214 */
215 NRF_STATIC_INLINE void nrf_ppi_event_endpoint_setup(NRF_PPI_Type * p_reg,
216 nrf_ppi_channel_t channel,
217 uint32_t eep);
218
219 /**
220 * @brief Function for setting up the task endpoint for a given PPI channel.
221 *
222 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
223 * @param[in] tep Task register address.
224 * @param[in] channel Channel to which the given endpoint is assigned.
225 */
226 NRF_STATIC_INLINE void nrf_ppi_task_endpoint_setup(NRF_PPI_Type * p_reg,
227 nrf_ppi_channel_t channel,
228 uint32_t tep);
229
230
231 #if defined(PPI_FEATURE_FORKS_PRESENT) || defined(__NRFX_DOXYGEN__)
232 /**
233 * @brief Function for setting up task endpoint for a given PPI fork.
234 *
235 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
236 * @param[in] fork_tep Task register address.
237 * @param[in] channel Channel to which the given fork endpoint is assigned.
238 */
239 NRF_STATIC_INLINE void nrf_ppi_fork_endpoint_setup(NRF_PPI_Type * p_reg,
240 nrf_ppi_channel_t channel,
241 uint32_t fork_tep);
242
243 /**
244 * @brief Function for setting up event and task endpoints for a given PPI channel and fork.
245 *
246 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
247 * @param[in] eep Event register address.
248 * @param[in] tep Task register address.
249 * @param[in] fork_tep Fork task register address (register value).
250 * @param[in] channel Channel to which the given endpoints are assigned.
251 */
252 NRF_STATIC_INLINE void nrf_ppi_channel_and_fork_endpoint_setup(NRF_PPI_Type * p_reg,
253 nrf_ppi_channel_t channel,
254 uint32_t eep,
255 uint32_t tep,
256 uint32_t fork_tep);
257 #endif
258
259 /**
260 * @brief Function for including a PPI channel in a channel group.
261 *
262 * @details This function adds only one channel to the group.
263 *
264 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
265 * @param[in] channel Channel to be included in the group.
266 * @param[in] channel_group Channel group.
267 */
268 NRF_STATIC_INLINE void nrf_ppi_channel_include_in_group(NRF_PPI_Type * p_reg,
269 nrf_ppi_channel_t channel,
270 nrf_ppi_channel_group_t channel_group);
271
272 /**
273 * @brief Function for including multiple PPI channels in a channel group.
274 *
275 * @details This function adds all specified channels to the group.
276 *
277 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
278 * @param[in] channel_mask Channels to be included in the group.
279 * @param[in] channel_group Channel group.
280 */
281 NRF_STATIC_INLINE void nrf_ppi_channels_include_in_group(NRF_PPI_Type * p_reg,
282 uint32_t channel_mask,
283 nrf_ppi_channel_group_t channel_group);
284
285 /**
286 * @brief Function for removing a PPI channel from a channel group.
287 *
288 * @details This function removes only one channel from the group.
289 *
290 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
291 * @param[in] channel Channel to be removed from the group.
292 * @param[in] channel_group Channel group.
293 */
294 NRF_STATIC_INLINE void nrf_ppi_channel_remove_from_group(NRF_PPI_Type * p_reg,
295 nrf_ppi_channel_t channel,
296 nrf_ppi_channel_group_t channel_group);
297
298 /**
299 * @brief Function for removing multiple PPI channels from a channel group.
300 *
301 * @details This function removes all specified channels from the group.
302 *
303 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
304 * @param[in] channel_mask Channels to be removed from the group.
305 * @param[in] channel_group Channel group.
306 */
307 NRF_STATIC_INLINE void nrf_ppi_channels_remove_from_group(NRF_PPI_Type * p_reg,
308 uint32_t channel_mask,
309 nrf_ppi_channel_group_t channel_group);
310
311 /**
312 * @brief Function for removing all PPI channels from a channel group.
313 *
314 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
315 * @param[in] group Channel group.
316 */
317 NRF_STATIC_INLINE void nrf_ppi_group_clear(NRF_PPI_Type * p_reg, nrf_ppi_channel_group_t group);
318
319 /**
320 * @brief Function for enabling a channel group.
321 *
322 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
323 * @param[in] group Channel group.
324 */
325 NRF_STATIC_INLINE void nrf_ppi_group_enable(NRF_PPI_Type * p_reg, nrf_ppi_channel_group_t group);
326
327 /**
328 * @brief Function for disabling a channel group.
329 *
330 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
331 * @param[in] group Channel group.
332 */
333 NRF_STATIC_INLINE void nrf_ppi_group_disable(NRF_PPI_Type * p_reg, nrf_ppi_channel_group_t group);
334
335 /**
336 * @brief Function for setting a PPI task.
337 *
338 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
339 * @param[in] ppi_task PPI task to be set.
340 */
341 NRF_STATIC_INLINE void nrf_ppi_task_trigger(NRF_PPI_Type * p_reg, nrf_ppi_task_t ppi_task);
342
343 /**
344 * @brief Function for getting the address of the specified PPI task register.
345 *
346 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
347 * @param[in] ppi_task PPI task.
348 *
349 * @return Address of the requested PPI task register.
350 */
351 NRF_STATIC_INLINE uint32_t nrf_ppi_task_address_get(NRF_PPI_Type const * p_reg,
352 nrf_ppi_task_t ppi_task);
353
354 /**
355 * @brief Function for getting the PPI enable task address of the specified group.
356 *
357 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
358 * @param[in] group PPI group.
359 *
360 * @return PPI enable task address of the specified group.
361 */
362 NRF_STATIC_INLINE uint32_t nrf_ppi_task_group_enable_address_get(NRF_PPI_Type const * p_reg,
363 nrf_ppi_channel_group_t group);
364
365 /**
366 * @brief Function for getting the PPI disable task address of the specified group.
367 *
368 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
369 * @param[in] group PPI group.
370 *
371 * @return PPI disable task address of the specified group.
372 */
373 NRF_STATIC_INLINE uint32_t nrf_ppi_task_group_disable_address_get(NRF_PPI_Type const * p_reg,
374 nrf_ppi_channel_group_t group);
375
376 /**
377 * @brief Function for getting the ENABLE task associated with the specified channel group.
378 *
379 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
380 * @param[in] index Channel group index.
381 *
382 * @return Requested ENABLE task.
383 */
384 NRF_STATIC_INLINE nrf_ppi_task_t nrf_ppi_group_enable_task_get(NRF_PPI_Type const * p_reg,
385 uint8_t index);
386
387 /**
388 * @brief Function for getting the DISABLE task associated with the specified channel group.
389 *
390 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
391 * @param[in] index Channel group index.
392 *
393 * @return Requested DISABLE task.
394 */
395 NRF_STATIC_INLINE nrf_ppi_task_t nrf_ppi_group_disable_task_get(NRF_PPI_Type const * p_reg,
396 uint8_t index);
397
398
399 #ifndef NRF_DECLARE_ONLY
400
nrf_ppi_channel_enable(NRF_PPI_Type * p_reg,nrf_ppi_channel_t channel)401 NRF_STATIC_INLINE void nrf_ppi_channel_enable(NRF_PPI_Type * p_reg, nrf_ppi_channel_t channel)
402 {
403 p_reg->CHENSET = PPI_CHENSET_CH0_Set << ((uint32_t) channel);
404 }
405
nrf_ppi_channel_disable(NRF_PPI_Type * p_reg,nrf_ppi_channel_t channel)406 NRF_STATIC_INLINE void nrf_ppi_channel_disable(NRF_PPI_Type * p_reg, nrf_ppi_channel_t channel)
407 {
408 p_reg->CHENCLR = PPI_CHENCLR_CH0_Clear << ((uint32_t) channel);
409 }
410
nrf_ppi_channel_enable_get(NRF_PPI_Type const * p_reg,nrf_ppi_channel_t channel)411 NRF_STATIC_INLINE nrf_ppi_channel_enable_t nrf_ppi_channel_enable_get(NRF_PPI_Type const * p_reg,
412 nrf_ppi_channel_t channel)
413 {
414 if (p_reg->CHEN & (PPI_CHEN_CH0_Msk << ((uint32_t) channel)))
415 {
416 return NRF_PPI_CHANNEL_ENABLED;
417 }
418 else
419 {
420 return NRF_PPI_CHANNEL_DISABLED;
421 }
422 }
423
nrf_ppi_channels_disable_all(NRF_PPI_Type * p_reg)424 NRF_STATIC_INLINE void nrf_ppi_channels_disable_all(NRF_PPI_Type * p_reg)
425 {
426 p_reg->CHENCLR = ((uint32_t)0xFFFFFFFFuL);
427 }
428
nrf_ppi_channels_enable(NRF_PPI_Type * p_reg,uint32_t mask)429 NRF_STATIC_INLINE void nrf_ppi_channels_enable(NRF_PPI_Type * p_reg, uint32_t mask)
430 {
431 p_reg->CHENSET = mask;
432 }
433
nrf_ppi_channels_disable(NRF_PPI_Type * p_reg,uint32_t mask)434 NRF_STATIC_INLINE void nrf_ppi_channels_disable(NRF_PPI_Type * p_reg, uint32_t mask)
435 {
436 p_reg->CHENCLR = mask;
437 }
438
nrf_ppi_channel_endpoint_setup(NRF_PPI_Type * p_reg,nrf_ppi_channel_t channel,uint32_t eep,uint32_t tep)439 NRF_STATIC_INLINE void nrf_ppi_channel_endpoint_setup(NRF_PPI_Type * p_reg,
440 nrf_ppi_channel_t channel,
441 uint32_t eep,
442 uint32_t tep)
443 {
444 p_reg->CH[(uint32_t) channel].EEP = eep;
445 p_reg->CH[(uint32_t) channel].TEP = tep;
446 }
447
nrf_ppi_event_endpoint_setup(NRF_PPI_Type * p_reg,nrf_ppi_channel_t channel,uint32_t eep)448 NRF_STATIC_INLINE void nrf_ppi_event_endpoint_setup(NRF_PPI_Type * p_reg,
449 nrf_ppi_channel_t channel,
450 uint32_t eep)
451 {
452 p_reg->CH[(uint32_t) channel].EEP = eep;
453 }
454
nrf_ppi_task_endpoint_setup(NRF_PPI_Type * p_reg,nrf_ppi_channel_t channel,uint32_t tep)455 NRF_STATIC_INLINE void nrf_ppi_task_endpoint_setup(NRF_PPI_Type * p_reg,
456 nrf_ppi_channel_t channel,
457 uint32_t tep)
458 {
459 p_reg->CH[(uint32_t) channel].TEP = tep;
460 }
461
462 #if defined(PPI_FEATURE_FORKS_PRESENT)
463
nrf_ppi_fork_endpoint_setup(NRF_PPI_Type * p_reg,nrf_ppi_channel_t channel,uint32_t fork_tep)464 NRF_STATIC_INLINE void nrf_ppi_fork_endpoint_setup(NRF_PPI_Type * p_reg,
465 nrf_ppi_channel_t channel,
466 uint32_t fork_tep)
467 {
468 p_reg->FORK[(uint32_t) channel].TEP = fork_tep;
469 }
470
nrf_ppi_channel_and_fork_endpoint_setup(NRF_PPI_Type * p_reg,nrf_ppi_channel_t channel,uint32_t eep,uint32_t tep,uint32_t fork_tep)471 NRF_STATIC_INLINE void nrf_ppi_channel_and_fork_endpoint_setup(NRF_PPI_Type * p_reg,
472 nrf_ppi_channel_t channel,
473 uint32_t eep,
474 uint32_t tep,
475 uint32_t fork_tep)
476 {
477 nrf_ppi_channel_endpoint_setup(p_reg, channel, eep, tep);
478 nrf_ppi_fork_endpoint_setup(p_reg, channel, fork_tep);
479 }
480 #endif
481
nrf_ppi_channel_include_in_group(NRF_PPI_Type * p_reg,nrf_ppi_channel_t channel,nrf_ppi_channel_group_t channel_group)482 NRF_STATIC_INLINE void nrf_ppi_channel_include_in_group(NRF_PPI_Type * p_reg,
483 nrf_ppi_channel_t channel,
484 nrf_ppi_channel_group_t channel_group)
485 {
486 p_reg->CHG[(uint32_t) channel_group] |= (PPI_CHG_CH0_Included << ((uint32_t) channel));
487 }
488
nrf_ppi_channels_include_in_group(NRF_PPI_Type * p_reg,uint32_t channel_mask,nrf_ppi_channel_group_t channel_group)489 NRF_STATIC_INLINE void nrf_ppi_channels_include_in_group(NRF_PPI_Type * p_reg,
490 uint32_t channel_mask,
491 nrf_ppi_channel_group_t channel_group)
492 {
493 p_reg->CHG[(uint32_t) channel_group] |= channel_mask;
494 }
495
nrf_ppi_channel_remove_from_group(NRF_PPI_Type * p_reg,nrf_ppi_channel_t channel,nrf_ppi_channel_group_t channel_group)496 NRF_STATIC_INLINE void nrf_ppi_channel_remove_from_group(NRF_PPI_Type * p_reg,
497 nrf_ppi_channel_t channel,
498 nrf_ppi_channel_group_t channel_group)
499 {
500 p_reg->CHG[(uint32_t) channel_group] &= ~(PPI_CHG_CH0_Included << ((uint32_t) channel));
501 }
502
nrf_ppi_channels_remove_from_group(NRF_PPI_Type * p_reg,uint32_t channel_mask,nrf_ppi_channel_group_t channel_group)503 NRF_STATIC_INLINE void nrf_ppi_channels_remove_from_group(NRF_PPI_Type * p_reg,
504 uint32_t channel_mask,
505 nrf_ppi_channel_group_t channel_group)
506 {
507 p_reg->CHG[(uint32_t) channel_group] &= ~(channel_mask);
508 }
509
nrf_ppi_group_clear(NRF_PPI_Type * p_reg,nrf_ppi_channel_group_t group)510 NRF_STATIC_INLINE void nrf_ppi_group_clear(NRF_PPI_Type * p_reg, nrf_ppi_channel_group_t group)
511 {
512 p_reg->CHG[(uint32_t) group] = 0;
513 }
514
nrf_ppi_group_enable(NRF_PPI_Type * p_reg,nrf_ppi_channel_group_t group)515 NRF_STATIC_INLINE void nrf_ppi_group_enable(NRF_PPI_Type * p_reg, nrf_ppi_channel_group_t group)
516 {
517 p_reg->TASKS_CHG[(uint32_t) group].EN = 1UL;
518 }
519
nrf_ppi_group_disable(NRF_PPI_Type * p_reg,nrf_ppi_channel_group_t group)520 NRF_STATIC_INLINE void nrf_ppi_group_disable(NRF_PPI_Type * p_reg, nrf_ppi_channel_group_t group)
521 {
522 p_reg->TASKS_CHG[(uint32_t) group].DIS = 1UL;
523 }
524
nrf_ppi_task_trigger(NRF_PPI_Type * p_reg,nrf_ppi_task_t ppi_task)525 NRF_STATIC_INLINE void nrf_ppi_task_trigger(NRF_PPI_Type * p_reg, nrf_ppi_task_t ppi_task)
526 {
527 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) ppi_task)) = 1UL;
528 }
529
nrf_ppi_task_address_get(NRF_PPI_Type const * p_reg,nrf_ppi_task_t ppi_task)530 NRF_STATIC_INLINE uint32_t nrf_ppi_task_address_get(NRF_PPI_Type const * p_reg,
531 nrf_ppi_task_t ppi_task)
532 {
533 return (uint32_t) ((uint8_t *) p_reg + (uint32_t) ppi_task);
534 }
535
nrf_ppi_task_group_enable_address_get(NRF_PPI_Type const * p_reg,nrf_ppi_channel_group_t group)536 NRF_STATIC_INLINE uint32_t nrf_ppi_task_group_enable_address_get(NRF_PPI_Type const * p_reg,
537 nrf_ppi_channel_group_t group)
538 {
539 return (uint32_t) &p_reg->TASKS_CHG[(uint32_t) group].EN;
540 }
541
nrf_ppi_task_group_disable_address_get(NRF_PPI_Type const * p_reg,nrf_ppi_channel_group_t group)542 NRF_STATIC_INLINE uint32_t nrf_ppi_task_group_disable_address_get(NRF_PPI_Type const * p_reg,
543 nrf_ppi_channel_group_t group)
544 {
545 return (uint32_t) &p_reg->TASKS_CHG[(uint32_t) group].DIS;
546 }
547
nrf_ppi_group_enable_task_get(NRF_PPI_Type const * p_reg,uint8_t index)548 NRF_STATIC_INLINE nrf_ppi_task_t nrf_ppi_group_enable_task_get(NRF_PPI_Type const * p_reg,
549 uint8_t index)
550 {
551 (void)p_reg;
552 NRFX_ASSERT(index < PPI_GROUP_NUM);
553 return (nrf_ppi_task_t)NRFX_OFFSETOF(NRF_PPI_Type, TASKS_CHG[index].EN);
554 }
555
nrf_ppi_group_disable_task_get(NRF_PPI_Type const * p_reg,uint8_t index)556 NRF_STATIC_INLINE nrf_ppi_task_t nrf_ppi_group_disable_task_get(NRF_PPI_Type const * p_reg,
557 uint8_t index)
558 {
559 (void)p_reg;
560 NRFX_ASSERT(index < PPI_GROUP_NUM);
561 return (nrf_ppi_task_t)NRFX_OFFSETOF(NRF_PPI_Type, TASKS_CHG[index].DIS);
562 }
563
564 #endif // NRF_DECLARE_ONLY
565
566 /** @} */
567
568 #ifdef __cplusplus
569 }
570 #endif
571
572 #endif // NRF_PPI_H__
573