1 /* 2 3 Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. 4 5 Redistribution and use in source and binary forms, with or without 6 modification, are permitted provided that the following conditions are met: 7 8 1. Redistributions of source code must retain the above copyright notice, this 9 list of conditions and the following disclaimer. 10 11 2. Redistributions in binary form must reproduce the above copyright 12 notice, this list of conditions and the following disclaimer in the 13 documentation and/or other materials provided with the distribution. 14 15 3. Neither the name of Nordic Semiconductor ASA nor the names of its 16 contributors may be used to endorse or promote products derived from this 17 software without specific prior written permission. 18 19 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE 22 ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE 23 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 POSSIBILITY OF SUCH DAMAGE. 30 31 */ 32 33 #ifndef NRF51_DEPRECATED_H 34 #define NRF51_DEPRECATED_H 35 36 /*lint ++flb "Enter library region */ 37 38 /* This file is given to prevent your SW from not compiling with the updates made to nrf51.h and 39 * nrf51_bitfields.h. The macros defined in this file were available previously. Do not use these 40 * macros on purpose. Use the ones defined in nrf51.h and nrf51_bitfields.h instead. 41 */ 42 43 /* NVMC */ 44 /* The register ERASEPROTECTEDPAGE is called ERASEPCR0 in the documentation. */ 45 #define ERASEPROTECTEDPAGE ERASEPCR0 46 47 48 /* LPCOMP */ 49 /* The interrupt ISR was renamed. Adding old name to the macros. */ 50 #define LPCOMP_COMP_IRQHandler LPCOMP_IRQHandler 51 #define LPCOMP_COMP_IRQn LPCOMP_IRQn 52 /* Corrected typo in RESULT register. */ 53 #define LPCOMP_RESULT_RESULT_Bellow LPCOMP_RESULT_RESULT_Below 54 55 56 /* MPU */ 57 /* The field MPU.PERR0.LPCOMP_COMP was renamed. Added into deprecated in case somebody was using the macros defined for it. */ 58 #define MPU_PERR0_LPCOMP_COMP_Pos MPU_PERR0_LPCOMP_Pos 59 #define MPU_PERR0_LPCOMP_COMP_Msk MPU_PERR0_LPCOMP_Msk 60 #define MPU_PERR0_LPCOMP_COMP_InRegion1 MPU_PERR0_LPCOMP_InRegion1 61 #define MPU_PERR0_LPCOMP_COMP_InRegion0 MPU_PERR0_LPCOMP_InRegion0 62 63 64 /* POWER */ 65 /* The field POWER.RAMON.OFFRAM3 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */ 66 #define POWER_RAMON_OFFRAM3_Pos (19UL) 67 #define POWER_RAMON_OFFRAM3_Msk (0x1UL << POWER_RAMON_OFFRAM3_Pos) 68 #define POWER_RAMON_OFFRAM3_RAM3Off (0UL) 69 #define POWER_RAMON_OFFRAM3_RAM3On (1UL) 70 /* The field POWER.RAMON.OFFRAM2 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */ 71 #define POWER_RAMON_OFFRAM2_Pos (18UL) 72 #define POWER_RAMON_OFFRAM2_Msk (0x1UL << POWER_RAMON_OFFRAM2_Pos) 73 #define POWER_RAMON_OFFRAM2_RAM2Off (0UL) 74 #define POWER_RAMON_OFFRAM2_RAM2On (1UL) 75 /* The field POWER.RAMON.ONRAM3 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */ 76 #define POWER_RAMON_ONRAM3_Pos (3UL) 77 #define POWER_RAMON_ONRAM3_Msk (0x1UL << POWER_RAMON_ONRAM3_Pos) 78 #define POWER_RAMON_ONRAM3_RAM3Off (0UL) 79 #define POWER_RAMON_ONRAM3_RAM3On (1UL) 80 /* The field POWER.RAMON.ONRAM2 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */ 81 #define POWER_RAMON_ONRAM2_Pos (2UL) 82 #define POWER_RAMON_ONRAM2_Msk (0x1UL << POWER_RAMON_ONRAM2_Pos) 83 #define POWER_RAMON_ONRAM2_RAM2Off (0UL) 84 #define POWER_RAMON_ONRAM2_RAM2On (1UL) 85 86 87 /* RADIO */ 88 /* The enumerated value RADIO.TXPOWER.TXPOWER.Neg40dBm was renamed. Added into deprecated with the new macro name. */ 89 #define RADIO_TXPOWER_TXPOWER_Neg40dBm RADIO_TXPOWER_TXPOWER_Neg30dBm 90 /* The name of the field SKIPADDR was corrected. Old macros added for compatibility. */ 91 #define RADIO_CRCCNF_SKIP_ADDR_Pos RADIO_CRCCNF_SKIPADDR_Pos 92 #define RADIO_CRCCNF_SKIP_ADDR_Msk RADIO_CRCCNF_SKIPADDR_Msk 93 #define RADIO_CRCCNF_SKIP_ADDR_Include RADIO_CRCCNF_SKIPADDR_Include 94 #define RADIO_CRCCNF_SKIP_ADDR_Skip RADIO_CRCCNF_SKIPADDR_Skip 95 /* The name of the field PLLLOCK was corrected. Old macros added for compatibility. */ 96 #define RADIO_TEST_PLL_LOCK_Pos RADIO_TEST_PLLLOCK_Pos 97 #define RADIO_TEST_PLL_LOCK_Msk RADIO_TEST_PLLLOCK_Msk 98 #define RADIO_TEST_PLL_LOCK_Disabled RADIO_TEST_PLLLOCK_Disabled 99 #define RADIO_TEST_PLL_LOCK_Enabled RADIO_TEST_PLLLOCK_Enabled 100 /* The name of the field CONSTCARRIER was corrected. Old macros added for compatibility. */ 101 #define RADIO_TEST_CONST_CARRIER_Pos RADIO_TEST_CONSTCARRIER_Pos 102 #define RADIO_TEST_CONST_CARRIER_Msk RADIO_TEST_CONSTCARRIER_Msk 103 #define RADIO_TEST_CONST_CARRIER_Disabled RADIO_TEST_CONSTCARRIER_Disabled 104 #define RADIO_TEST_CONST_CARRIER_Enabled RADIO_TEST_CONSTCARRIER_Enabled 105 106 107 /* FICR */ 108 /* The registers FICR.SIZERAMBLOCK0, FICR.SIZERAMBLOCK1, FICR.SIZERAMBLOCK2 and FICR.SIZERAMBLOCK3 were renamed into an array. */ 109 #define SIZERAMBLOCK0 SIZERAMBLOCKS 110 #define SIZERAMBLOCK1 SIZERAMBLOCKS 111 #define SIZERAMBLOCK2 SIZERAMBLOCK[2] /*!< Note that this macro will disapear when SIZERAMBLOCK array is eliminated. SIZERAMBLOCK is a deprecated array. */ 112 #define SIZERAMBLOCK3 SIZERAMBLOCK[3] /*!< Note that this macro will disapear when SIZERAMBLOCK array is eliminated. SIZERAMBLOCK is a deprecated array. */ 113 /* The registers FICR.DEVICEID0 and FICR.DEVICEID1 were renamed into an array. */ 114 #define DEVICEID0 DEVICEID[0] 115 #define DEVICEID1 DEVICEID[1] 116 /* The registers FICR.ER0, FICR.ER1, FICR.ER2 and FICR.ER3 were renamed into an array. */ 117 #define ER0 ER[0] 118 #define ER1 ER[1] 119 #define ER2 ER[2] 120 #define ER3 ER[3] 121 /* The registers FICR.IR0, FICR.IR1, FICR.IR2 and FICR.IR3 were renamed into an array. */ 122 #define IR0 IR[0] 123 #define IR1 IR[1] 124 #define IR2 IR[2] 125 #define IR3 IR[3] 126 /* The registers FICR.DEVICEADDR0 and FICR.DEVICEADDR1 were renamed into an array. */ 127 #define DEVICEADDR0 DEVICEADDR[0] 128 #define DEVICEADDR1 DEVICEADDR[1] 129 130 131 /* PPI */ 132 /* The tasks PPI.TASKS_CHGxEN and PPI.TASKS_CHGxDIS were renamed into an array of structs. */ 133 #define TASKS_CHG0EN TASKS_CHG[0].EN 134 #define TASKS_CHG0DIS TASKS_CHG[0].DIS 135 #define TASKS_CHG1EN TASKS_CHG[1].EN 136 #define TASKS_CHG1DIS TASKS_CHG[1].DIS 137 #define TASKS_CHG2EN TASKS_CHG[2].EN 138 #define TASKS_CHG2DIS TASKS_CHG[2].DIS 139 #define TASKS_CHG3EN TASKS_CHG[3].EN 140 #define TASKS_CHG3DIS TASKS_CHG[3].DIS 141 /* The registers PPI.CHx_EEP and PPI.CHx_TEP were renamed into an array of structs. */ 142 #define CH0_EEP CH[0].EEP 143 #define CH0_TEP CH[0].TEP 144 #define CH1_EEP CH[1].EEP 145 #define CH1_TEP CH[1].TEP 146 #define CH2_EEP CH[2].EEP 147 #define CH2_TEP CH[2].TEP 148 #define CH3_EEP CH[3].EEP 149 #define CH3_TEP CH[3].TEP 150 #define CH4_EEP CH[4].EEP 151 #define CH4_TEP CH[4].TEP 152 #define CH5_EEP CH[5].EEP 153 #define CH5_TEP CH[5].TEP 154 #define CH6_EEP CH[6].EEP 155 #define CH6_TEP CH[6].TEP 156 #define CH7_EEP CH[7].EEP 157 #define CH7_TEP CH[7].TEP 158 #define CH8_EEP CH[8].EEP 159 #define CH8_TEP CH[8].TEP 160 #define CH9_EEP CH[9].EEP 161 #define CH9_TEP CH[9].TEP 162 #define CH10_EEP CH[10].EEP 163 #define CH10_TEP CH[10].TEP 164 #define CH11_EEP CH[11].EEP 165 #define CH11_TEP CH[11].TEP 166 #define CH12_EEP CH[12].EEP 167 #define CH12_TEP CH[12].TEP 168 #define CH13_EEP CH[13].EEP 169 #define CH13_TEP CH[13].TEP 170 #define CH14_EEP CH[14].EEP 171 #define CH14_TEP CH[14].TEP 172 #define CH15_EEP CH[15].EEP 173 #define CH15_TEP CH[15].TEP 174 /* The registers PPI.CHG0, PPI.CHG1, PPI.CHG2 and PPI.CHG3 were renamed into an array. */ 175 #define CHG0 CHG[0] 176 #define CHG1 CHG[1] 177 #define CHG2 CHG[2] 178 #define CHG3 CHG[3] 179 /* All bitfield macros for the CHGx registers therefore changed name. */ 180 #define PPI_CHG0_CH15_Pos PPI_CHG_CH15_Pos 181 #define PPI_CHG0_CH15_Msk PPI_CHG_CH15_Msk 182 #define PPI_CHG0_CH15_Excluded PPI_CHG_CH15_Excluded 183 #define PPI_CHG0_CH15_Included PPI_CHG_CH15_Included 184 #define PPI_CHG0_CH14_Pos PPI_CHG_CH14_Pos 185 #define PPI_CHG0_CH14_Msk PPI_CHG_CH14_Msk 186 #define PPI_CHG0_CH14_Excluded PPI_CHG_CH14_Excluded 187 #define PPI_CHG0_CH14_Included PPI_CHG_CH14_Included 188 #define PPI_CHG0_CH13_Pos PPI_CHG_CH13_Pos 189 #define PPI_CHG0_CH13_Msk PPI_CHG_CH13_Msk 190 #define PPI_CHG0_CH13_Excluded PPI_CHG_CH13_Excluded 191 #define PPI_CHG0_CH13_Included PPI_CHG_CH13_Included 192 #define PPI_CHG0_CH12_Pos PPI_CHG_CH12_Pos 193 #define PPI_CHG0_CH12_Msk PPI_CHG_CH12_Msk 194 #define PPI_CHG0_CH12_Excluded PPI_CHG_CH12_Excluded 195 #define PPI_CHG0_CH12_Included PPI_CHG_CH12_Included 196 #define PPI_CHG0_CH11_Pos PPI_CHG_CH11_Pos 197 #define PPI_CHG0_CH11_Msk PPI_CHG_CH11_Msk 198 #define PPI_CHG0_CH11_Excluded PPI_CHG_CH11_Excluded 199 #define PPI_CHG0_CH11_Included PPI_CHG_CH11_Included 200 #define PPI_CHG0_CH10_Pos PPI_CHG_CH10_Pos 201 #define PPI_CHG0_CH10_Msk PPI_CHG_CH10_Msk 202 #define PPI_CHG0_CH10_Excluded PPI_CHG_CH10_Excluded 203 #define PPI_CHG0_CH10_Included PPI_CHG_CH10_Included 204 #define PPI_CHG0_CH9_Pos PPI_CHG_CH9_Pos 205 #define PPI_CHG0_CH9_Msk PPI_CHG_CH9_Msk 206 #define PPI_CHG0_CH9_Excluded PPI_CHG_CH9_Excluded 207 #define PPI_CHG0_CH9_Included PPI_CHG_CH9_Included 208 #define PPI_CHG0_CH8_Pos PPI_CHG_CH8_Pos 209 #define PPI_CHG0_CH8_Msk PPI_CHG_CH8_Msk 210 #define PPI_CHG0_CH8_Excluded PPI_CHG_CH8_Excluded 211 #define PPI_CHG0_CH8_Included PPI_CHG_CH8_Included 212 #define PPI_CHG0_CH7_Pos PPI_CHG_CH7_Pos 213 #define PPI_CHG0_CH7_Msk PPI_CHG_CH7_Msk 214 #define PPI_CHG0_CH7_Excluded PPI_CHG_CH7_Excluded 215 #define PPI_CHG0_CH7_Included PPI_CHG_CH7_Included 216 #define PPI_CHG0_CH6_Pos PPI_CHG_CH6_Pos 217 #define PPI_CHG0_CH6_Msk PPI_CHG_CH6_Msk 218 #define PPI_CHG0_CH6_Excluded PPI_CHG_CH6_Excluded 219 #define PPI_CHG0_CH6_Included PPI_CHG_CH6_Included 220 #define PPI_CHG0_CH5_Pos PPI_CHG_CH5_Pos 221 #define PPI_CHG0_CH5_Msk PPI_CHG_CH5_Msk 222 #define PPI_CHG0_CH5_Excluded PPI_CHG_CH5_Excluded 223 #define PPI_CHG0_CH5_Included PPI_CHG_CH5_Included 224 #define PPI_CHG0_CH4_Pos PPI_CHG_CH4_Pos 225 #define PPI_CHG0_CH4_Msk PPI_CHG_CH4_Msk 226 #define PPI_CHG0_CH4_Excluded PPI_CHG_CH4_Excluded 227 #define PPI_CHG0_CH4_Included PPI_CHG_CH4_Included 228 #define PPI_CHG0_CH3_Pos PPI_CHG_CH3_Pos 229 #define PPI_CHG0_CH3_Msk PPI_CHG_CH3_Msk 230 #define PPI_CHG0_CH3_Excluded PPI_CHG_CH3_Excluded 231 #define PPI_CHG0_CH3_Included PPI_CHG_CH3_Included 232 #define PPI_CHG0_CH2_Pos PPI_CHG_CH2_Pos 233 #define PPI_CHG0_CH2_Msk PPI_CHG_CH2_Msk 234 #define PPI_CHG0_CH2_Excluded PPI_CHG_CH2_Excluded 235 #define PPI_CHG0_CH2_Included PPI_CHG_CH2_Included 236 #define PPI_CHG0_CH1_Pos PPI_CHG_CH1_Pos 237 #define PPI_CHG0_CH1_Msk PPI_CHG_CH1_Msk 238 #define PPI_CHG0_CH1_Excluded PPI_CHG_CH1_Excluded 239 #define PPI_CHG0_CH1_Included PPI_CHG_CH1_Included 240 #define PPI_CHG0_CH0_Pos PPI_CHG_CH0_Pos 241 #define PPI_CHG0_CH0_Msk PPI_CHG_CH0_Msk 242 #define PPI_CHG0_CH0_Excluded PPI_CHG_CH0_Excluded 243 #define PPI_CHG0_CH0_Included PPI_CHG_CH0_Included 244 #define PPI_CHG1_CH15_Pos PPI_CHG_CH15_Pos 245 #define PPI_CHG1_CH15_Msk PPI_CHG_CH15_Msk 246 #define PPI_CHG1_CH15_Excluded PPI_CHG_CH15_Excluded 247 #define PPI_CHG1_CH15_Included PPI_CHG_CH15_Included 248 #define PPI_CHG1_CH14_Pos PPI_CHG_CH14_Pos 249 #define PPI_CHG1_CH14_Msk PPI_CHG_CH14_Msk 250 #define PPI_CHG1_CH14_Excluded PPI_CHG_CH14_Excluded 251 #define PPI_CHG1_CH14_Included PPI_CHG_CH14_Included 252 #define PPI_CHG1_CH13_Pos PPI_CHG_CH13_Pos 253 #define PPI_CHG1_CH13_Msk PPI_CHG_CH13_Msk 254 #define PPI_CHG1_CH13_Excluded PPI_CHG_CH13_Excluded 255 #define PPI_CHG1_CH13_Included PPI_CHG_CH13_Included 256 #define PPI_CHG1_CH12_Pos PPI_CHG_CH12_Pos 257 #define PPI_CHG1_CH12_Msk PPI_CHG_CH12_Msk 258 #define PPI_CHG1_CH12_Excluded PPI_CHG_CH12_Excluded 259 #define PPI_CHG1_CH12_Included PPI_CHG_CH12_Included 260 #define PPI_CHG1_CH11_Pos PPI_CHG_CH11_Pos 261 #define PPI_CHG1_CH11_Msk PPI_CHG_CH11_Msk 262 #define PPI_CHG1_CH11_Excluded PPI_CHG_CH11_Excluded 263 #define PPI_CHG1_CH11_Included PPI_CHG_CH11_Included 264 #define PPI_CHG1_CH10_Pos PPI_CHG_CH10_Pos 265 #define PPI_CHG1_CH10_Msk PPI_CHG_CH10_Msk 266 #define PPI_CHG1_CH10_Excluded PPI_CHG_CH10_Excluded 267 #define PPI_CHG1_CH10_Included PPI_CHG_CH10_Included 268 #define PPI_CHG1_CH9_Pos PPI_CHG_CH9_Pos 269 #define PPI_CHG1_CH9_Msk PPI_CHG_CH9_Msk 270 #define PPI_CHG1_CH9_Excluded PPI_CHG_CH9_Excluded 271 #define PPI_CHG1_CH9_Included PPI_CHG_CH9_Included 272 #define PPI_CHG1_CH8_Pos PPI_CHG_CH8_Pos 273 #define PPI_CHG1_CH8_Msk PPI_CHG_CH8_Msk 274 #define PPI_CHG1_CH8_Excluded PPI_CHG_CH8_Excluded 275 #define PPI_CHG1_CH8_Included PPI_CHG_CH8_Included 276 #define PPI_CHG1_CH7_Pos PPI_CHG_CH7_Pos 277 #define PPI_CHG1_CH7_Msk PPI_CHG_CH7_Msk 278 #define PPI_CHG1_CH7_Excluded PPI_CHG_CH7_Excluded 279 #define PPI_CHG1_CH7_Included PPI_CHG_CH7_Included 280 #define PPI_CHG1_CH6_Pos PPI_CHG_CH6_Pos 281 #define PPI_CHG1_CH6_Msk PPI_CHG_CH6_Msk 282 #define PPI_CHG1_CH6_Excluded PPI_CHG_CH6_Excluded 283 #define PPI_CHG1_CH6_Included PPI_CHG_CH6_Included 284 #define PPI_CHG1_CH5_Pos PPI_CHG_CH5_Pos 285 #define PPI_CHG1_CH5_Msk PPI_CHG_CH5_Msk 286 #define PPI_CHG1_CH5_Excluded PPI_CHG_CH5_Excluded 287 #define PPI_CHG1_CH5_Included PPI_CHG_CH5_Included 288 #define PPI_CHG1_CH4_Pos PPI_CHG_CH4_Pos 289 #define PPI_CHG1_CH4_Msk PPI_CHG_CH4_Msk 290 #define PPI_CHG1_CH4_Excluded PPI_CHG_CH4_Excluded 291 #define PPI_CHG1_CH4_Included PPI_CHG_CH4_Included 292 #define PPI_CHG1_CH3_Pos PPI_CHG_CH3_Pos 293 #define PPI_CHG1_CH3_Msk PPI_CHG_CH3_Msk 294 #define PPI_CHG1_CH3_Excluded PPI_CHG_CH3_Excluded 295 #define PPI_CHG1_CH3_Included PPI_CHG_CH3_Included 296 #define PPI_CHG1_CH2_Pos PPI_CHG_CH2_Pos 297 #define PPI_CHG1_CH2_Msk PPI_CHG_CH2_Msk 298 #define PPI_CHG1_CH2_Excluded PPI_CHG_CH2_Excluded 299 #define PPI_CHG1_CH2_Included PPI_CHG_CH2_Included 300 #define PPI_CHG1_CH1_Pos PPI_CHG_CH1_Pos 301 #define PPI_CHG1_CH1_Msk PPI_CHG_CH1_Msk 302 #define PPI_CHG1_CH1_Excluded PPI_CHG_CH1_Excluded 303 #define PPI_CHG1_CH1_Included PPI_CHG_CH1_Included 304 #define PPI_CHG1_CH0_Pos PPI_CHG_CH0_Pos 305 #define PPI_CHG1_CH0_Msk PPI_CHG_CH0_Msk 306 #define PPI_CHG1_CH0_Excluded PPI_CHG_CH0_Excluded 307 #define PPI_CHG1_CH0_Included PPI_CHG_CH0_Included 308 #define PPI_CHG2_CH15_Pos PPI_CHG_CH15_Pos 309 #define PPI_CHG2_CH15_Msk PPI_CHG_CH15_Msk 310 #define PPI_CHG2_CH15_Excluded PPI_CHG_CH15_Excluded 311 #define PPI_CHG2_CH15_Included PPI_CHG_CH15_Included 312 #define PPI_CHG2_CH14_Pos PPI_CHG_CH14_Pos 313 #define PPI_CHG2_CH14_Msk PPI_CHG_CH14_Msk 314 #define PPI_CHG2_CH14_Excluded PPI_CHG_CH14_Excluded 315 #define PPI_CHG2_CH14_Included PPI_CHG_CH14_Included 316 #define PPI_CHG2_CH13_Pos PPI_CHG_CH13_Pos 317 #define PPI_CHG2_CH13_Msk PPI_CHG_CH13_Msk 318 #define PPI_CHG2_CH13_Excluded PPI_CHG_CH13_Excluded 319 #define PPI_CHG2_CH13_Included PPI_CHG_CH13_Included 320 #define PPI_CHG2_CH12_Pos PPI_CHG_CH12_Pos 321 #define PPI_CHG2_CH12_Msk PPI_CHG_CH12_Msk 322 #define PPI_CHG2_CH12_Excluded PPI_CHG_CH12_Excluded 323 #define PPI_CHG2_CH12_Included PPI_CHG_CH12_Included 324 #define PPI_CHG2_CH11_Pos PPI_CHG_CH11_Pos 325 #define PPI_CHG2_CH11_Msk PPI_CHG_CH11_Msk 326 #define PPI_CHG2_CH11_Excluded PPI_CHG_CH11_Excluded 327 #define PPI_CHG2_CH11_Included PPI_CHG_CH11_Included 328 #define PPI_CHG2_CH10_Pos PPI_CHG_CH10_Pos 329 #define PPI_CHG2_CH10_Msk PPI_CHG_CH10_Msk 330 #define PPI_CHG2_CH10_Excluded PPI_CHG_CH10_Excluded 331 #define PPI_CHG2_CH10_Included PPI_CHG_CH10_Included 332 #define PPI_CHG2_CH9_Pos PPI_CHG_CH9_Pos 333 #define PPI_CHG2_CH9_Msk PPI_CHG_CH9_Msk 334 #define PPI_CHG2_CH9_Excluded PPI_CHG_CH9_Excluded 335 #define PPI_CHG2_CH9_Included PPI_CHG_CH9_Included 336 #define PPI_CHG2_CH8_Pos PPI_CHG_CH8_Pos 337 #define PPI_CHG2_CH8_Msk PPI_CHG_CH8_Msk 338 #define PPI_CHG2_CH8_Excluded PPI_CHG_CH8_Excluded 339 #define PPI_CHG2_CH8_Included PPI_CHG_CH8_Included 340 #define PPI_CHG2_CH7_Pos PPI_CHG_CH7_Pos 341 #define PPI_CHG2_CH7_Msk PPI_CHG_CH7_Msk 342 #define PPI_CHG2_CH7_Excluded PPI_CHG_CH7_Excluded 343 #define PPI_CHG2_CH7_Included PPI_CHG_CH7_Included 344 #define PPI_CHG2_CH6_Pos PPI_CHG_CH6_Pos 345 #define PPI_CHG2_CH6_Msk PPI_CHG_CH6_Msk 346 #define PPI_CHG2_CH6_Excluded PPI_CHG_CH6_Excluded 347 #define PPI_CHG2_CH6_Included PPI_CHG_CH6_Included 348 #define PPI_CHG2_CH5_Pos PPI_CHG_CH5_Pos 349 #define PPI_CHG2_CH5_Msk PPI_CHG_CH5_Msk 350 #define PPI_CHG2_CH5_Excluded PPI_CHG_CH5_Excluded 351 #define PPI_CHG2_CH5_Included PPI_CHG_CH5_Included 352 #define PPI_CHG2_CH4_Pos PPI_CHG_CH4_Pos 353 #define PPI_CHG2_CH4_Msk PPI_CHG_CH4_Msk 354 #define PPI_CHG2_CH4_Excluded PPI_CHG_CH4_Excluded 355 #define PPI_CHG2_CH4_Included PPI_CHG_CH4_Included 356 #define PPI_CHG2_CH3_Pos PPI_CHG_CH3_Pos 357 #define PPI_CHG2_CH3_Msk PPI_CHG_CH3_Msk 358 #define PPI_CHG2_CH3_Excluded PPI_CHG_CH3_Excluded 359 #define PPI_CHG2_CH3_Included PPI_CHG_CH3_Included 360 #define PPI_CHG2_CH2_Pos PPI_CHG_CH2_Pos 361 #define PPI_CHG2_CH2_Msk PPI_CHG_CH2_Msk 362 #define PPI_CHG2_CH2_Excluded PPI_CHG_CH2_Excluded 363 #define PPI_CHG2_CH2_Included PPI_CHG_CH2_Included 364 #define PPI_CHG2_CH1_Pos PPI_CHG_CH1_Pos 365 #define PPI_CHG2_CH1_Msk PPI_CHG_CH1_Msk 366 #define PPI_CHG2_CH1_Excluded PPI_CHG_CH1_Excluded 367 #define PPI_CHG2_CH1_Included PPI_CHG_CH1_Included 368 #define PPI_CHG2_CH0_Pos PPI_CHG_CH0_Pos 369 #define PPI_CHG2_CH0_Msk PPI_CHG_CH0_Msk 370 #define PPI_CHG2_CH0_Excluded PPI_CHG_CH0_Excluded 371 #define PPI_CHG2_CH0_Included PPI_CHG_CH0_Included 372 #define PPI_CHG3_CH15_Pos PPI_CHG_CH15_Pos 373 #define PPI_CHG3_CH15_Msk PPI_CHG_CH15_Msk 374 #define PPI_CHG3_CH15_Excluded PPI_CHG_CH15_Excluded 375 #define PPI_CHG3_CH15_Included PPI_CHG_CH15_Included 376 #define PPI_CHG3_CH14_Pos PPI_CHG_CH14_Pos 377 #define PPI_CHG3_CH14_Msk PPI_CHG_CH14_Msk 378 #define PPI_CHG3_CH14_Excluded PPI_CHG_CH14_Excluded 379 #define PPI_CHG3_CH14_Included PPI_CHG_CH14_Included 380 #define PPI_CHG3_CH13_Pos PPI_CHG_CH13_Pos 381 #define PPI_CHG3_CH13_Msk PPI_CHG_CH13_Msk 382 #define PPI_CHG3_CH13_Excluded PPI_CHG_CH13_Excluded 383 #define PPI_CHG3_CH13_Included PPI_CHG_CH13_Included 384 #define PPI_CHG3_CH12_Pos PPI_CHG_CH12_Pos 385 #define PPI_CHG3_CH12_Msk PPI_CHG_CH12_Msk 386 #define PPI_CHG3_CH12_Excluded PPI_CHG_CH12_Excluded 387 #define PPI_CHG3_CH12_Included PPI_CHG_CH12_Included 388 #define PPI_CHG3_CH11_Pos PPI_CHG_CH11_Pos 389 #define PPI_CHG3_CH11_Msk PPI_CHG_CH11_Msk 390 #define PPI_CHG3_CH11_Excluded PPI_CHG_CH11_Excluded 391 #define PPI_CHG3_CH11_Included PPI_CHG_CH11_Included 392 #define PPI_CHG3_CH10_Pos PPI_CHG_CH10_Pos 393 #define PPI_CHG3_CH10_Msk PPI_CHG_CH10_Msk 394 #define PPI_CHG3_CH10_Excluded PPI_CHG_CH10_Excluded 395 #define PPI_CHG3_CH10_Included PPI_CHG_CH10_Included 396 #define PPI_CHG3_CH9_Pos PPI_CHG_CH9_Pos 397 #define PPI_CHG3_CH9_Msk PPI_CHG_CH9_Msk 398 #define PPI_CHG3_CH9_Excluded PPI_CHG_CH9_Excluded 399 #define PPI_CHG3_CH9_Included PPI_CHG_CH9_Included 400 #define PPI_CHG3_CH8_Pos PPI_CHG_CH8_Pos 401 #define PPI_CHG3_CH8_Msk PPI_CHG_CH8_Msk 402 #define PPI_CHG3_CH8_Excluded PPI_CHG_CH8_Excluded 403 #define PPI_CHG3_CH8_Included PPI_CHG_CH8_Included 404 #define PPI_CHG3_CH7_Pos PPI_CHG_CH7_Pos 405 #define PPI_CHG3_CH7_Msk PPI_CHG_CH7_Msk 406 #define PPI_CHG3_CH7_Excluded PPI_CHG_CH7_Excluded 407 #define PPI_CHG3_CH7_Included PPI_CHG_CH7_Included 408 #define PPI_CHG3_CH6_Pos PPI_CHG_CH6_Pos 409 #define PPI_CHG3_CH6_Msk PPI_CHG_CH6_Msk 410 #define PPI_CHG3_CH6_Excluded PPI_CHG_CH6_Excluded 411 #define PPI_CHG3_CH6_Included PPI_CHG_CH6_Included 412 #define PPI_CHG3_CH5_Pos PPI_CHG_CH5_Pos 413 #define PPI_CHG3_CH5_Msk PPI_CHG_CH5_Msk 414 #define PPI_CHG3_CH5_Excluded PPI_CHG_CH5_Excluded 415 #define PPI_CHG3_CH5_Included PPI_CHG_CH5_Included 416 #define PPI_CHG3_CH4_Pos PPI_CHG_CH4_Pos 417 #define PPI_CHG3_CH4_Msk PPI_CHG_CH4_Msk 418 #define PPI_CHG3_CH4_Excluded PPI_CHG_CH4_Excluded 419 #define PPI_CHG3_CH4_Included PPI_CHG_CH4_Included 420 #define PPI_CHG3_CH3_Pos PPI_CHG_CH3_Pos 421 #define PPI_CHG3_CH3_Msk PPI_CHG_CH3_Msk 422 #define PPI_CHG3_CH3_Excluded PPI_CHG_CH3_Excluded 423 #define PPI_CHG3_CH3_Included PPI_CHG_CH3_Included 424 #define PPI_CHG3_CH2_Pos PPI_CHG_CH2_Pos 425 #define PPI_CHG3_CH2_Msk PPI_CHG_CH2_Msk 426 #define PPI_CHG3_CH2_Excluded PPI_CHG_CH2_Excluded 427 #define PPI_CHG3_CH2_Included PPI_CHG_CH2_Included 428 #define PPI_CHG3_CH1_Pos PPI_CHG_CH1_Pos 429 #define PPI_CHG3_CH1_Msk PPI_CHG_CH1_Msk 430 #define PPI_CHG3_CH1_Excluded PPI_CHG_CH1_Excluded 431 #define PPI_CHG3_CH1_Included PPI_CHG_CH1_Included 432 #define PPI_CHG3_CH0_Pos PPI_CHG_CH0_Pos 433 #define PPI_CHG3_CH0_Msk PPI_CHG_CH0_Msk 434 #define PPI_CHG3_CH0_Excluded PPI_CHG_CH0_Excluded 435 #define PPI_CHG3_CH0_Included PPI_CHG_CH0_Included 436 437 /* SPIS */ 438 /* nRF51 devices do not have an SPIS0, only SPIS1. SPIS0_EASYDMA_MAXCNT_SIZE was therefore renamed. */ 439 #define SPIS0_EASYDMA_MAXCNT_SIZE SPIS1_EASYDMA_MAXCNT_SIZE 440 441 442 443 /*lint --flb "Leave library region" */ 444 445 #endif /* NRF51_DEPRECATED_H */ 446 447