1 /* 2 3 Copyright (c) 2009-2020 ARM Limited. All rights reserved. 4 5 SPDX-License-Identifier: Apache-2.0 6 7 Licensed under the Apache License, Version 2.0 (the License); you may 8 not use this file except in compliance with the License. 9 You may obtain a copy of the License at 10 11 www.apache.org/licenses/LICENSE-2.0 12 13 Unless required by applicable law or agreed to in writing, software 14 distributed under the License is distributed on an AS IS BASIS, WITHOUT 15 WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 16 See the License for the specific language governing permissions and 17 limitations under the License. 18 19 NOTICE: This file has been modified by Nordic Semiconductor ASA. 20 21 */ 22 23 /* NOTE: Template files (including this one) are application specific and therefore expected to 24 be copied into the application project folder prior to its use! */ 25 26 #include <stdint.h> 27 #include <stdbool.h> 28 #include "nrf.h" 29 #include "nrf_erratas.h" 30 #include "system_nrf52840.h" 31 32 /*lint ++flb "Enter library region" */ 33 34 #define __SYSTEM_CLOCK_64M (64000000UL) 35 36 37 #if defined ( __CC_ARM ) 38 uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M; 39 #elif defined ( __ICCARM__ ) 40 __root uint32_t SystemCoreClock = __SYSTEM_CLOCK_64M; 41 #elif defined ( __GNUC__ ) 42 uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M; 43 #endif 44 SystemCoreClockUpdate(void)45void SystemCoreClockUpdate(void) 46 { 47 SystemCoreClock = __SYSTEM_CLOCK_64M; 48 } 49 SystemInit(void)50void SystemInit(void) 51 { 52 /* Enable SWO trace functionality. If ENABLE_SWO is not defined, SWO pin will be used as GPIO (see Product 53 Specification to see which one). */ 54 #if defined (ENABLE_SWO) 55 CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; 56 NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial << CLOCK_TRACECONFIG_TRACEMUX_Pos; 57 NRF_P1->PIN_CNF[0] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); 58 #endif 59 60 /* Enable Trace functionality. If ENABLE_TRACE is not defined, TRACE pins will be used as GPIOs (see Product 61 Specification to see which ones). */ 62 #if defined (ENABLE_TRACE) 63 CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; 64 NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Parallel << CLOCK_TRACECONFIG_TRACEMUX_Pos; 65 NRF_P0->PIN_CNF[7] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); 66 NRF_P1->PIN_CNF[0] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); 67 NRF_P0->PIN_CNF[12] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); 68 NRF_P0->PIN_CNF[11] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); 69 NRF_P1->PIN_CNF[9] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); 70 #endif 71 72 /* Workaround for Errata 36 "CLOCK: Some registers are not reset when expected" found at the Errata document 73 for your device located at https://infocenter.nordicsemi.com/index.jsp */ 74 if (nrf52_errata_36()){ 75 NRF_CLOCK->EVENTS_DONE = 0; 76 NRF_CLOCK->EVENTS_CTTO = 0; 77 NRF_CLOCK->CTIV = 0; 78 } 79 80 /* Workaround for Errata 66 "TEMP: Linearity specification not met with default settings" found at the Errata document 81 for your device located at https://infocenter.nordicsemi.com/index.jsp */ 82 if (nrf52_errata_66()){ 83 NRF_TEMP->A0 = NRF_FICR->TEMP.A0; 84 NRF_TEMP->A1 = NRF_FICR->TEMP.A1; 85 NRF_TEMP->A2 = NRF_FICR->TEMP.A2; 86 NRF_TEMP->A3 = NRF_FICR->TEMP.A3; 87 NRF_TEMP->A4 = NRF_FICR->TEMP.A4; 88 NRF_TEMP->A5 = NRF_FICR->TEMP.A5; 89 NRF_TEMP->B0 = NRF_FICR->TEMP.B0; 90 NRF_TEMP->B1 = NRF_FICR->TEMP.B1; 91 NRF_TEMP->B2 = NRF_FICR->TEMP.B2; 92 NRF_TEMP->B3 = NRF_FICR->TEMP.B3; 93 NRF_TEMP->B4 = NRF_FICR->TEMP.B4; 94 NRF_TEMP->B5 = NRF_FICR->TEMP.B5; 95 NRF_TEMP->T0 = NRF_FICR->TEMP.T0; 96 NRF_TEMP->T1 = NRF_FICR->TEMP.T1; 97 NRF_TEMP->T2 = NRF_FICR->TEMP.T2; 98 NRF_TEMP->T3 = NRF_FICR->TEMP.T3; 99 NRF_TEMP->T4 = NRF_FICR->TEMP.T4; 100 } 101 102 /* Workaround for Errata 98 "NFCT: Not able to communicate with the peer" found at the Errata document 103 for your device located at https://infocenter.nordicsemi.com/index.jsp */ 104 if (nrf52_errata_98()){ 105 *(volatile uint32_t *)0x4000568Cul = 0x00038148ul; 106 } 107 108 /* Workaround for Errata 103 "CCM: Wrong reset value of CCM MAXPACKETSIZE" found at the Errata document 109 for your device located at https://infocenter.nordicsemi.com/index.jsp */ 110 if (nrf52_errata_103()){ 111 NRF_CCM->MAXPACKETSIZE = 0xFBul; 112 } 113 114 /* Workaround for Errata 115 "RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document 115 for your device located at https://infocenter.nordicsemi.com/index.jsp */ 116 if (nrf52_errata_115()){ 117 *(volatile uint32_t *)0x40000EE4ul = (*(volatile uint32_t *)0x40000EE4ul & 0xFFFFFFF0ul) | (*(uint32_t *)0x10000258ul & 0x0000000Ful); 118 } 119 120 /* Workaround for Errata 120 "QSPI: Data read or written is corrupted" found at the Errata document 121 for your device located at https://infocenter.nordicsemi.com/index.jsp */ 122 if (nrf52_errata_120()){ 123 *(volatile uint32_t *)0x40029640ul = 0x200ul; 124 } 125 126 /* Workaround for Errata 136 "System: Bits in RESETREAS are set when they should not be" found at the Errata document 127 for your device located at https://infocenter.nordicsemi.com/index.jsp */ 128 if (nrf52_errata_136()){ 129 if (NRF_POWER->RESETREAS & POWER_RESETREAS_RESETPIN_Msk){ 130 NRF_POWER->RESETREAS = ~POWER_RESETREAS_RESETPIN_Msk; 131 } 132 } 133 134 /* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the 135 * compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit 136 * operations are not used in your code. */ 137 #if (__FPU_USED == 1) 138 SCB->CPACR |= (3UL << 20) | (3UL << 22); 139 __DSB(); 140 __ISB(); 141 #endif 142 143 /* Configure NFCT pins as GPIOs if NFCT is not to be used in your code. If CONFIG_NFCT_PINS_AS_GPIOS is not defined, 144 two GPIOs (see Product Specification to see which ones) will be reserved for NFC and will not be available as 145 normal GPIOs. */ 146 #if defined (CONFIG_NFCT_PINS_AS_GPIOS) 147 if ((NRF_UICR->NFCPINS & UICR_NFCPINS_PROTECT_Msk) == (UICR_NFCPINS_PROTECT_NFC << UICR_NFCPINS_PROTECT_Pos)){ 148 NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos; 149 while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} 150 NRF_UICR->NFCPINS &= ~UICR_NFCPINS_PROTECT_Msk; 151 while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} 152 NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos; 153 while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} 154 NVIC_SystemReset(); 155 } 156 #endif 157 158 /* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities desired. If CONFIG_GPIO_AS_PINRESET is not 159 defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be 160 reserved for PinReset and not available as normal GPIO. */ 161 #if defined (CONFIG_GPIO_AS_PINRESET) 162 if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) || 163 ((NRF_UICR->PSELRESET[1] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))){ 164 NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos; 165 while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} 166 NRF_UICR->PSELRESET[0] = 18; 167 while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} 168 NRF_UICR->PSELRESET[1] = 18; 169 while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} 170 NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos; 171 while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} 172 NVIC_SystemReset(); 173 } 174 #endif 175 176 SystemCoreClockUpdate(); 177 } 178 179 /*lint --flb "Leave library region" */ 180