1 /** 2 * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 // ============================================================================= 7 // Register block : ADC 8 // Version : 2 9 // Bus type : apb 10 // Description : Control and data interface to SAR ADC 11 // ============================================================================= 12 #ifndef HARDWARE_REGS_ADC_DEFINED 13 #define HARDWARE_REGS_ADC_DEFINED 14 // ============================================================================= 15 // Register : ADC_CS 16 // Description : ADC Control and Status 17 #define ADC_CS_OFFSET 0x00000000 18 #define ADC_CS_BITS 0x001f770f 19 #define ADC_CS_RESET 0x00000000 20 // ----------------------------------------------------------------------------- 21 // Field : ADC_CS_RROBIN 22 // Description : Round-robin sampling. 1 bit per channel. Set all bits to 0 to 23 // disable. 24 // Otherwise, the ADC will cycle through each enabled channel in a 25 // round-robin fashion. 26 // The first channel to be sampled will be the one currently 27 // indicated by AINSEL. 28 // AINSEL will be updated after each conversion with the 29 // newly-selected channel. 30 #define ADC_CS_RROBIN_RESET 0x00 31 #define ADC_CS_RROBIN_BITS 0x001f0000 32 #define ADC_CS_RROBIN_MSB 20 33 #define ADC_CS_RROBIN_LSB 16 34 #define ADC_CS_RROBIN_ACCESS "RW" 35 // ----------------------------------------------------------------------------- 36 // Field : ADC_CS_AINSEL 37 // Description : Select analog mux input. Updated automatically in round-robin 38 // mode. 39 #define ADC_CS_AINSEL_RESET 0x0 40 #define ADC_CS_AINSEL_BITS 0x00007000 41 #define ADC_CS_AINSEL_MSB 14 42 #define ADC_CS_AINSEL_LSB 12 43 #define ADC_CS_AINSEL_ACCESS "RW" 44 // ----------------------------------------------------------------------------- 45 // Field : ADC_CS_ERR_STICKY 46 // Description : Some past ADC conversion encountered an error. Write 1 to 47 // clear. 48 #define ADC_CS_ERR_STICKY_RESET 0x0 49 #define ADC_CS_ERR_STICKY_BITS 0x00000400 50 #define ADC_CS_ERR_STICKY_MSB 10 51 #define ADC_CS_ERR_STICKY_LSB 10 52 #define ADC_CS_ERR_STICKY_ACCESS "WC" 53 // ----------------------------------------------------------------------------- 54 // Field : ADC_CS_ERR 55 // Description : The most recent ADC conversion encountered an error; result is 56 // undefined or noisy. 57 #define ADC_CS_ERR_RESET 0x0 58 #define ADC_CS_ERR_BITS 0x00000200 59 #define ADC_CS_ERR_MSB 9 60 #define ADC_CS_ERR_LSB 9 61 #define ADC_CS_ERR_ACCESS "RO" 62 // ----------------------------------------------------------------------------- 63 // Field : ADC_CS_READY 64 // Description : 1 if the ADC is ready to start a new conversion. Implies any 65 // previous conversion has completed. 66 // 0 whilst conversion in progress. 67 #define ADC_CS_READY_RESET 0x0 68 #define ADC_CS_READY_BITS 0x00000100 69 #define ADC_CS_READY_MSB 8 70 #define ADC_CS_READY_LSB 8 71 #define ADC_CS_READY_ACCESS "RO" 72 // ----------------------------------------------------------------------------- 73 // Field : ADC_CS_START_MANY 74 // Description : Continuously perform conversions whilst this bit is 1. A new 75 // conversion will start immediately after the previous finishes. 76 #define ADC_CS_START_MANY_RESET 0x0 77 #define ADC_CS_START_MANY_BITS 0x00000008 78 #define ADC_CS_START_MANY_MSB 3 79 #define ADC_CS_START_MANY_LSB 3 80 #define ADC_CS_START_MANY_ACCESS "RW" 81 // ----------------------------------------------------------------------------- 82 // Field : ADC_CS_START_ONCE 83 // Description : Start a single conversion. Self-clearing. Ignored if start_many 84 // is asserted. 85 #define ADC_CS_START_ONCE_RESET 0x0 86 #define ADC_CS_START_ONCE_BITS 0x00000004 87 #define ADC_CS_START_ONCE_MSB 2 88 #define ADC_CS_START_ONCE_LSB 2 89 #define ADC_CS_START_ONCE_ACCESS "SC" 90 // ----------------------------------------------------------------------------- 91 // Field : ADC_CS_TS_EN 92 // Description : Power on temperature sensor. 1 - enabled. 0 - disabled. 93 #define ADC_CS_TS_EN_RESET 0x0 94 #define ADC_CS_TS_EN_BITS 0x00000002 95 #define ADC_CS_TS_EN_MSB 1 96 #define ADC_CS_TS_EN_LSB 1 97 #define ADC_CS_TS_EN_ACCESS "RW" 98 // ----------------------------------------------------------------------------- 99 // Field : ADC_CS_EN 100 // Description : Power on ADC and enable its clock. 101 // 1 - enabled. 0 - disabled. 102 #define ADC_CS_EN_RESET 0x0 103 #define ADC_CS_EN_BITS 0x00000001 104 #define ADC_CS_EN_MSB 0 105 #define ADC_CS_EN_LSB 0 106 #define ADC_CS_EN_ACCESS "RW" 107 // ============================================================================= 108 // Register : ADC_RESULT 109 // Description : Result of most recent ADC conversion 110 #define ADC_RESULT_OFFSET 0x00000004 111 #define ADC_RESULT_BITS 0x00000fff 112 #define ADC_RESULT_RESET 0x00000000 113 #define ADC_RESULT_MSB 11 114 #define ADC_RESULT_LSB 0 115 #define ADC_RESULT_ACCESS "RO" 116 // ============================================================================= 117 // Register : ADC_FCS 118 // Description : FIFO control and status 119 #define ADC_FCS_OFFSET 0x00000008 120 #define ADC_FCS_BITS 0x0f0f0f0f 121 #define ADC_FCS_RESET 0x00000000 122 // ----------------------------------------------------------------------------- 123 // Field : ADC_FCS_THRESH 124 // Description : DREQ/IRQ asserted when level >= threshold 125 #define ADC_FCS_THRESH_RESET 0x0 126 #define ADC_FCS_THRESH_BITS 0x0f000000 127 #define ADC_FCS_THRESH_MSB 27 128 #define ADC_FCS_THRESH_LSB 24 129 #define ADC_FCS_THRESH_ACCESS "RW" 130 // ----------------------------------------------------------------------------- 131 // Field : ADC_FCS_LEVEL 132 // Description : The number of conversion results currently waiting in the FIFO 133 #define ADC_FCS_LEVEL_RESET 0x0 134 #define ADC_FCS_LEVEL_BITS 0x000f0000 135 #define ADC_FCS_LEVEL_MSB 19 136 #define ADC_FCS_LEVEL_LSB 16 137 #define ADC_FCS_LEVEL_ACCESS "RO" 138 // ----------------------------------------------------------------------------- 139 // Field : ADC_FCS_OVER 140 // Description : 1 if the FIFO has been overflowed. Write 1 to clear. 141 #define ADC_FCS_OVER_RESET 0x0 142 #define ADC_FCS_OVER_BITS 0x00000800 143 #define ADC_FCS_OVER_MSB 11 144 #define ADC_FCS_OVER_LSB 11 145 #define ADC_FCS_OVER_ACCESS "WC" 146 // ----------------------------------------------------------------------------- 147 // Field : ADC_FCS_UNDER 148 // Description : 1 if the FIFO has been underflowed. Write 1 to clear. 149 #define ADC_FCS_UNDER_RESET 0x0 150 #define ADC_FCS_UNDER_BITS 0x00000400 151 #define ADC_FCS_UNDER_MSB 10 152 #define ADC_FCS_UNDER_LSB 10 153 #define ADC_FCS_UNDER_ACCESS "WC" 154 // ----------------------------------------------------------------------------- 155 // Field : ADC_FCS_FULL 156 // Description : None 157 #define ADC_FCS_FULL_RESET 0x0 158 #define ADC_FCS_FULL_BITS 0x00000200 159 #define ADC_FCS_FULL_MSB 9 160 #define ADC_FCS_FULL_LSB 9 161 #define ADC_FCS_FULL_ACCESS "RO" 162 // ----------------------------------------------------------------------------- 163 // Field : ADC_FCS_EMPTY 164 // Description : None 165 #define ADC_FCS_EMPTY_RESET 0x0 166 #define ADC_FCS_EMPTY_BITS 0x00000100 167 #define ADC_FCS_EMPTY_MSB 8 168 #define ADC_FCS_EMPTY_LSB 8 169 #define ADC_FCS_EMPTY_ACCESS "RO" 170 // ----------------------------------------------------------------------------- 171 // Field : ADC_FCS_DREQ_EN 172 // Description : If 1: assert DMA requests when FIFO contains data 173 #define ADC_FCS_DREQ_EN_RESET 0x0 174 #define ADC_FCS_DREQ_EN_BITS 0x00000008 175 #define ADC_FCS_DREQ_EN_MSB 3 176 #define ADC_FCS_DREQ_EN_LSB 3 177 #define ADC_FCS_DREQ_EN_ACCESS "RW" 178 // ----------------------------------------------------------------------------- 179 // Field : ADC_FCS_ERR 180 // Description : If 1: conversion error bit appears in the FIFO alongside the 181 // result 182 #define ADC_FCS_ERR_RESET 0x0 183 #define ADC_FCS_ERR_BITS 0x00000004 184 #define ADC_FCS_ERR_MSB 2 185 #define ADC_FCS_ERR_LSB 2 186 #define ADC_FCS_ERR_ACCESS "RW" 187 // ----------------------------------------------------------------------------- 188 // Field : ADC_FCS_SHIFT 189 // Description : If 1: FIFO results are right-shifted to be one byte in size. 190 // Enables DMA to byte buffers. 191 #define ADC_FCS_SHIFT_RESET 0x0 192 #define ADC_FCS_SHIFT_BITS 0x00000002 193 #define ADC_FCS_SHIFT_MSB 1 194 #define ADC_FCS_SHIFT_LSB 1 195 #define ADC_FCS_SHIFT_ACCESS "RW" 196 // ----------------------------------------------------------------------------- 197 // Field : ADC_FCS_EN 198 // Description : If 1: write result to the FIFO after each conversion. 199 #define ADC_FCS_EN_RESET 0x0 200 #define ADC_FCS_EN_BITS 0x00000001 201 #define ADC_FCS_EN_MSB 0 202 #define ADC_FCS_EN_LSB 0 203 #define ADC_FCS_EN_ACCESS "RW" 204 // ============================================================================= 205 // Register : ADC_FIFO 206 // Description : Conversion result FIFO 207 #define ADC_FIFO_OFFSET 0x0000000c 208 #define ADC_FIFO_BITS 0x00008fff 209 #define ADC_FIFO_RESET 0x00000000 210 // ----------------------------------------------------------------------------- 211 // Field : ADC_FIFO_ERR 212 // Description : 1 if this particular sample experienced a conversion error. 213 // Remains in the same location if the sample is shifted. 214 #define ADC_FIFO_ERR_RESET "-" 215 #define ADC_FIFO_ERR_BITS 0x00008000 216 #define ADC_FIFO_ERR_MSB 15 217 #define ADC_FIFO_ERR_LSB 15 218 #define ADC_FIFO_ERR_ACCESS "RF" 219 // ----------------------------------------------------------------------------- 220 // Field : ADC_FIFO_VAL 221 // Description : None 222 #define ADC_FIFO_VAL_RESET "-" 223 #define ADC_FIFO_VAL_BITS 0x00000fff 224 #define ADC_FIFO_VAL_MSB 11 225 #define ADC_FIFO_VAL_LSB 0 226 #define ADC_FIFO_VAL_ACCESS "RF" 227 // ============================================================================= 228 // Register : ADC_DIV 229 // Description : Clock divider. If non-zero, CS_START_MANY will start 230 // conversions 231 // at regular intervals rather than back-to-back. 232 // The divider is reset when either of these fields are written. 233 // Total period is 1 + INT + FRAC / 256 234 #define ADC_DIV_OFFSET 0x00000010 235 #define ADC_DIV_BITS 0x00ffffff 236 #define ADC_DIV_RESET 0x00000000 237 // ----------------------------------------------------------------------------- 238 // Field : ADC_DIV_INT 239 // Description : Integer part of clock divisor. 240 #define ADC_DIV_INT_RESET 0x0000 241 #define ADC_DIV_INT_BITS 0x00ffff00 242 #define ADC_DIV_INT_MSB 23 243 #define ADC_DIV_INT_LSB 8 244 #define ADC_DIV_INT_ACCESS "RW" 245 // ----------------------------------------------------------------------------- 246 // Field : ADC_DIV_FRAC 247 // Description : Fractional part of clock divisor. First-order delta-sigma. 248 #define ADC_DIV_FRAC_RESET 0x00 249 #define ADC_DIV_FRAC_BITS 0x000000ff 250 #define ADC_DIV_FRAC_MSB 7 251 #define ADC_DIV_FRAC_LSB 0 252 #define ADC_DIV_FRAC_ACCESS "RW" 253 // ============================================================================= 254 // Register : ADC_INTR 255 // Description : Raw Interrupts 256 #define ADC_INTR_OFFSET 0x00000014 257 #define ADC_INTR_BITS 0x00000001 258 #define ADC_INTR_RESET 0x00000000 259 // ----------------------------------------------------------------------------- 260 // Field : ADC_INTR_FIFO 261 // Description : Triggered when the sample FIFO reaches a certain level. 262 // This level can be programmed via the FCS_THRESH field. 263 #define ADC_INTR_FIFO_RESET 0x0 264 #define ADC_INTR_FIFO_BITS 0x00000001 265 #define ADC_INTR_FIFO_MSB 0 266 #define ADC_INTR_FIFO_LSB 0 267 #define ADC_INTR_FIFO_ACCESS "RO" 268 // ============================================================================= 269 // Register : ADC_INTE 270 // Description : Interrupt Enable 271 #define ADC_INTE_OFFSET 0x00000018 272 #define ADC_INTE_BITS 0x00000001 273 #define ADC_INTE_RESET 0x00000000 274 // ----------------------------------------------------------------------------- 275 // Field : ADC_INTE_FIFO 276 // Description : Triggered when the sample FIFO reaches a certain level. 277 // This level can be programmed via the FCS_THRESH field. 278 #define ADC_INTE_FIFO_RESET 0x0 279 #define ADC_INTE_FIFO_BITS 0x00000001 280 #define ADC_INTE_FIFO_MSB 0 281 #define ADC_INTE_FIFO_LSB 0 282 #define ADC_INTE_FIFO_ACCESS "RW" 283 // ============================================================================= 284 // Register : ADC_INTF 285 // Description : Interrupt Force 286 #define ADC_INTF_OFFSET 0x0000001c 287 #define ADC_INTF_BITS 0x00000001 288 #define ADC_INTF_RESET 0x00000000 289 // ----------------------------------------------------------------------------- 290 // Field : ADC_INTF_FIFO 291 // Description : Triggered when the sample FIFO reaches a certain level. 292 // This level can be programmed via the FCS_THRESH field. 293 #define ADC_INTF_FIFO_RESET 0x0 294 #define ADC_INTF_FIFO_BITS 0x00000001 295 #define ADC_INTF_FIFO_MSB 0 296 #define ADC_INTF_FIFO_LSB 0 297 #define ADC_INTF_FIFO_ACCESS "RW" 298 // ============================================================================= 299 // Register : ADC_INTS 300 // Description : Interrupt status after masking & forcing 301 #define ADC_INTS_OFFSET 0x00000020 302 #define ADC_INTS_BITS 0x00000001 303 #define ADC_INTS_RESET 0x00000000 304 // ----------------------------------------------------------------------------- 305 // Field : ADC_INTS_FIFO 306 // Description : Triggered when the sample FIFO reaches a certain level. 307 // This level can be programmed via the FCS_THRESH field. 308 #define ADC_INTS_FIFO_RESET 0x0 309 #define ADC_INTS_FIFO_BITS 0x00000001 310 #define ADC_INTS_FIFO_MSB 0 311 #define ADC_INTS_FIFO_LSB 0 312 #define ADC_INTS_FIFO_ACCESS "RO" 313 // ============================================================================= 314 #endif // HARDWARE_REGS_ADC_DEFINED 315