1 /** 2 * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 // ============================================================================= 7 // Register block : BUSCTRL 8 // Version : 1 9 // Bus type : apb 10 // Description : Register block for busfabric control signals and performance 11 // counters 12 // ============================================================================= 13 #ifndef HARDWARE_REGS_BUSCTRL_DEFINED 14 #define HARDWARE_REGS_BUSCTRL_DEFINED 15 // ============================================================================= 16 // Register : BUSCTRL_BUS_PRIORITY 17 // Description : Set the priority of each master for bus arbitration. 18 #define BUSCTRL_BUS_PRIORITY_OFFSET 0x00000000 19 #define BUSCTRL_BUS_PRIORITY_BITS 0x00001111 20 #define BUSCTRL_BUS_PRIORITY_RESET 0x00000000 21 // ----------------------------------------------------------------------------- 22 // Field : BUSCTRL_BUS_PRIORITY_DMA_W 23 // Description : 0 - low priority, 1 - high priority 24 #define BUSCTRL_BUS_PRIORITY_DMA_W_RESET 0x0 25 #define BUSCTRL_BUS_PRIORITY_DMA_W_BITS 0x00001000 26 #define BUSCTRL_BUS_PRIORITY_DMA_W_MSB 12 27 #define BUSCTRL_BUS_PRIORITY_DMA_W_LSB 12 28 #define BUSCTRL_BUS_PRIORITY_DMA_W_ACCESS "RW" 29 // ----------------------------------------------------------------------------- 30 // Field : BUSCTRL_BUS_PRIORITY_DMA_R 31 // Description : 0 - low priority, 1 - high priority 32 #define BUSCTRL_BUS_PRIORITY_DMA_R_RESET 0x0 33 #define BUSCTRL_BUS_PRIORITY_DMA_R_BITS 0x00000100 34 #define BUSCTRL_BUS_PRIORITY_DMA_R_MSB 8 35 #define BUSCTRL_BUS_PRIORITY_DMA_R_LSB 8 36 #define BUSCTRL_BUS_PRIORITY_DMA_R_ACCESS "RW" 37 // ----------------------------------------------------------------------------- 38 // Field : BUSCTRL_BUS_PRIORITY_PROC1 39 // Description : 0 - low priority, 1 - high priority 40 #define BUSCTRL_BUS_PRIORITY_PROC1_RESET 0x0 41 #define BUSCTRL_BUS_PRIORITY_PROC1_BITS 0x00000010 42 #define BUSCTRL_BUS_PRIORITY_PROC1_MSB 4 43 #define BUSCTRL_BUS_PRIORITY_PROC1_LSB 4 44 #define BUSCTRL_BUS_PRIORITY_PROC1_ACCESS "RW" 45 // ----------------------------------------------------------------------------- 46 // Field : BUSCTRL_BUS_PRIORITY_PROC0 47 // Description : 0 - low priority, 1 - high priority 48 #define BUSCTRL_BUS_PRIORITY_PROC0_RESET 0x0 49 #define BUSCTRL_BUS_PRIORITY_PROC0_BITS 0x00000001 50 #define BUSCTRL_BUS_PRIORITY_PROC0_MSB 0 51 #define BUSCTRL_BUS_PRIORITY_PROC0_LSB 0 52 #define BUSCTRL_BUS_PRIORITY_PROC0_ACCESS "RW" 53 // ============================================================================= 54 // Register : BUSCTRL_BUS_PRIORITY_ACK 55 // Description : Bus priority acknowledge 56 // Goes to 1 once all arbiters have registered the new global 57 // priority levels. 58 // Arbiters update their local priority when servicing a new 59 // nonsequential access. 60 // In normal circumstances this will happen almost immediately. 61 #define BUSCTRL_BUS_PRIORITY_ACK_OFFSET 0x00000004 62 #define BUSCTRL_BUS_PRIORITY_ACK_BITS 0x00000001 63 #define BUSCTRL_BUS_PRIORITY_ACK_RESET 0x00000000 64 #define BUSCTRL_BUS_PRIORITY_ACK_MSB 0 65 #define BUSCTRL_BUS_PRIORITY_ACK_LSB 0 66 #define BUSCTRL_BUS_PRIORITY_ACK_ACCESS "RO" 67 // ============================================================================= 68 // Register : BUSCTRL_PERFCTR0 69 // Description : Bus fabric performance counter 0 70 // Busfabric saturating performance counter 0 71 // Count some event signal from the busfabric arbiters. 72 // Write any value to clear. Select an event to count using 73 // PERFSEL0 74 #define BUSCTRL_PERFCTR0_OFFSET 0x00000008 75 #define BUSCTRL_PERFCTR0_BITS 0x00ffffff 76 #define BUSCTRL_PERFCTR0_RESET 0x00000000 77 #define BUSCTRL_PERFCTR0_MSB 23 78 #define BUSCTRL_PERFCTR0_LSB 0 79 #define BUSCTRL_PERFCTR0_ACCESS "WC" 80 // ============================================================================= 81 // Register : BUSCTRL_PERFSEL0 82 // Description : Bus fabric performance event select for PERFCTR0 83 // Select an event for PERFCTR0. Count either contested accesses, 84 // or all accesses, on a downstream port of the main crossbar. 85 // 0x00 -> apb_contested 86 // 0x01 -> apb 87 // 0x02 -> fastperi_contested 88 // 0x03 -> fastperi 89 // 0x04 -> sram5_contested 90 // 0x05 -> sram5 91 // 0x06 -> sram4_contested 92 // 0x07 -> sram4 93 // 0x08 -> sram3_contested 94 // 0x09 -> sram3 95 // 0x0a -> sram2_contested 96 // 0x0b -> sram2 97 // 0x0c -> sram1_contested 98 // 0x0d -> sram1 99 // 0x0e -> sram0_contested 100 // 0x0f -> sram0 101 // 0x10 -> xip_main_contested 102 // 0x11 -> xip_main 103 // 0x12 -> rom_contested 104 // 0x13 -> rom 105 #define BUSCTRL_PERFSEL0_OFFSET 0x0000000c 106 #define BUSCTRL_PERFSEL0_BITS 0x0000001f 107 #define BUSCTRL_PERFSEL0_RESET 0x0000001f 108 #define BUSCTRL_PERFSEL0_MSB 4 109 #define BUSCTRL_PERFSEL0_LSB 0 110 #define BUSCTRL_PERFSEL0_ACCESS "RW" 111 #define BUSCTRL_PERFSEL0_VALUE_APB_CONTESTED 0x00 112 #define BUSCTRL_PERFSEL0_VALUE_APB 0x01 113 #define BUSCTRL_PERFSEL0_VALUE_FASTPERI_CONTESTED 0x02 114 #define BUSCTRL_PERFSEL0_VALUE_FASTPERI 0x03 115 #define BUSCTRL_PERFSEL0_VALUE_SRAM5_CONTESTED 0x04 116 #define BUSCTRL_PERFSEL0_VALUE_SRAM5 0x05 117 #define BUSCTRL_PERFSEL0_VALUE_SRAM4_CONTESTED 0x06 118 #define BUSCTRL_PERFSEL0_VALUE_SRAM4 0x07 119 #define BUSCTRL_PERFSEL0_VALUE_SRAM3_CONTESTED 0x08 120 #define BUSCTRL_PERFSEL0_VALUE_SRAM3 0x09 121 #define BUSCTRL_PERFSEL0_VALUE_SRAM2_CONTESTED 0x0a 122 #define BUSCTRL_PERFSEL0_VALUE_SRAM2 0x0b 123 #define BUSCTRL_PERFSEL0_VALUE_SRAM1_CONTESTED 0x0c 124 #define BUSCTRL_PERFSEL0_VALUE_SRAM1 0x0d 125 #define BUSCTRL_PERFSEL0_VALUE_SRAM0_CONTESTED 0x0e 126 #define BUSCTRL_PERFSEL0_VALUE_SRAM0 0x0f 127 #define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN_CONTESTED 0x10 128 #define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN 0x11 129 #define BUSCTRL_PERFSEL0_VALUE_ROM_CONTESTED 0x12 130 #define BUSCTRL_PERFSEL0_VALUE_ROM 0x13 131 // ============================================================================= 132 // Register : BUSCTRL_PERFCTR1 133 // Description : Bus fabric performance counter 1 134 // Busfabric saturating performance counter 1 135 // Count some event signal from the busfabric arbiters. 136 // Write any value to clear. Select an event to count using 137 // PERFSEL1 138 #define BUSCTRL_PERFCTR1_OFFSET 0x00000010 139 #define BUSCTRL_PERFCTR1_BITS 0x00ffffff 140 #define BUSCTRL_PERFCTR1_RESET 0x00000000 141 #define BUSCTRL_PERFCTR1_MSB 23 142 #define BUSCTRL_PERFCTR1_LSB 0 143 #define BUSCTRL_PERFCTR1_ACCESS "WC" 144 // ============================================================================= 145 // Register : BUSCTRL_PERFSEL1 146 // Description : Bus fabric performance event select for PERFCTR1 147 // Select an event for PERFCTR1. Count either contested accesses, 148 // or all accesses, on a downstream port of the main crossbar. 149 // 0x00 -> apb_contested 150 // 0x01 -> apb 151 // 0x02 -> fastperi_contested 152 // 0x03 -> fastperi 153 // 0x04 -> sram5_contested 154 // 0x05 -> sram5 155 // 0x06 -> sram4_contested 156 // 0x07 -> sram4 157 // 0x08 -> sram3_contested 158 // 0x09 -> sram3 159 // 0x0a -> sram2_contested 160 // 0x0b -> sram2 161 // 0x0c -> sram1_contested 162 // 0x0d -> sram1 163 // 0x0e -> sram0_contested 164 // 0x0f -> sram0 165 // 0x10 -> xip_main_contested 166 // 0x11 -> xip_main 167 // 0x12 -> rom_contested 168 // 0x13 -> rom 169 #define BUSCTRL_PERFSEL1_OFFSET 0x00000014 170 #define BUSCTRL_PERFSEL1_BITS 0x0000001f 171 #define BUSCTRL_PERFSEL1_RESET 0x0000001f 172 #define BUSCTRL_PERFSEL1_MSB 4 173 #define BUSCTRL_PERFSEL1_LSB 0 174 #define BUSCTRL_PERFSEL1_ACCESS "RW" 175 #define BUSCTRL_PERFSEL1_VALUE_APB_CONTESTED 0x00 176 #define BUSCTRL_PERFSEL1_VALUE_APB 0x01 177 #define BUSCTRL_PERFSEL1_VALUE_FASTPERI_CONTESTED 0x02 178 #define BUSCTRL_PERFSEL1_VALUE_FASTPERI 0x03 179 #define BUSCTRL_PERFSEL1_VALUE_SRAM5_CONTESTED 0x04 180 #define BUSCTRL_PERFSEL1_VALUE_SRAM5 0x05 181 #define BUSCTRL_PERFSEL1_VALUE_SRAM4_CONTESTED 0x06 182 #define BUSCTRL_PERFSEL1_VALUE_SRAM4 0x07 183 #define BUSCTRL_PERFSEL1_VALUE_SRAM3_CONTESTED 0x08 184 #define BUSCTRL_PERFSEL1_VALUE_SRAM3 0x09 185 #define BUSCTRL_PERFSEL1_VALUE_SRAM2_CONTESTED 0x0a 186 #define BUSCTRL_PERFSEL1_VALUE_SRAM2 0x0b 187 #define BUSCTRL_PERFSEL1_VALUE_SRAM1_CONTESTED 0x0c 188 #define BUSCTRL_PERFSEL1_VALUE_SRAM1 0x0d 189 #define BUSCTRL_PERFSEL1_VALUE_SRAM0_CONTESTED 0x0e 190 #define BUSCTRL_PERFSEL1_VALUE_SRAM0 0x0f 191 #define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN_CONTESTED 0x10 192 #define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN 0x11 193 #define BUSCTRL_PERFSEL1_VALUE_ROM_CONTESTED 0x12 194 #define BUSCTRL_PERFSEL1_VALUE_ROM 0x13 195 // ============================================================================= 196 // Register : BUSCTRL_PERFCTR2 197 // Description : Bus fabric performance counter 2 198 // Busfabric saturating performance counter 2 199 // Count some event signal from the busfabric arbiters. 200 // Write any value to clear. Select an event to count using 201 // PERFSEL2 202 #define BUSCTRL_PERFCTR2_OFFSET 0x00000018 203 #define BUSCTRL_PERFCTR2_BITS 0x00ffffff 204 #define BUSCTRL_PERFCTR2_RESET 0x00000000 205 #define BUSCTRL_PERFCTR2_MSB 23 206 #define BUSCTRL_PERFCTR2_LSB 0 207 #define BUSCTRL_PERFCTR2_ACCESS "WC" 208 // ============================================================================= 209 // Register : BUSCTRL_PERFSEL2 210 // Description : Bus fabric performance event select for PERFCTR2 211 // Select an event for PERFCTR2. Count either contested accesses, 212 // or all accesses, on a downstream port of the main crossbar. 213 // 0x00 -> apb_contested 214 // 0x01 -> apb 215 // 0x02 -> fastperi_contested 216 // 0x03 -> fastperi 217 // 0x04 -> sram5_contested 218 // 0x05 -> sram5 219 // 0x06 -> sram4_contested 220 // 0x07 -> sram4 221 // 0x08 -> sram3_contested 222 // 0x09 -> sram3 223 // 0x0a -> sram2_contested 224 // 0x0b -> sram2 225 // 0x0c -> sram1_contested 226 // 0x0d -> sram1 227 // 0x0e -> sram0_contested 228 // 0x0f -> sram0 229 // 0x10 -> xip_main_contested 230 // 0x11 -> xip_main 231 // 0x12 -> rom_contested 232 // 0x13 -> rom 233 #define BUSCTRL_PERFSEL2_OFFSET 0x0000001c 234 #define BUSCTRL_PERFSEL2_BITS 0x0000001f 235 #define BUSCTRL_PERFSEL2_RESET 0x0000001f 236 #define BUSCTRL_PERFSEL2_MSB 4 237 #define BUSCTRL_PERFSEL2_LSB 0 238 #define BUSCTRL_PERFSEL2_ACCESS "RW" 239 #define BUSCTRL_PERFSEL2_VALUE_APB_CONTESTED 0x00 240 #define BUSCTRL_PERFSEL2_VALUE_APB 0x01 241 #define BUSCTRL_PERFSEL2_VALUE_FASTPERI_CONTESTED 0x02 242 #define BUSCTRL_PERFSEL2_VALUE_FASTPERI 0x03 243 #define BUSCTRL_PERFSEL2_VALUE_SRAM5_CONTESTED 0x04 244 #define BUSCTRL_PERFSEL2_VALUE_SRAM5 0x05 245 #define BUSCTRL_PERFSEL2_VALUE_SRAM4_CONTESTED 0x06 246 #define BUSCTRL_PERFSEL2_VALUE_SRAM4 0x07 247 #define BUSCTRL_PERFSEL2_VALUE_SRAM3_CONTESTED 0x08 248 #define BUSCTRL_PERFSEL2_VALUE_SRAM3 0x09 249 #define BUSCTRL_PERFSEL2_VALUE_SRAM2_CONTESTED 0x0a 250 #define BUSCTRL_PERFSEL2_VALUE_SRAM2 0x0b 251 #define BUSCTRL_PERFSEL2_VALUE_SRAM1_CONTESTED 0x0c 252 #define BUSCTRL_PERFSEL2_VALUE_SRAM1 0x0d 253 #define BUSCTRL_PERFSEL2_VALUE_SRAM0_CONTESTED 0x0e 254 #define BUSCTRL_PERFSEL2_VALUE_SRAM0 0x0f 255 #define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN_CONTESTED 0x10 256 #define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN 0x11 257 #define BUSCTRL_PERFSEL2_VALUE_ROM_CONTESTED 0x12 258 #define BUSCTRL_PERFSEL2_VALUE_ROM 0x13 259 // ============================================================================= 260 // Register : BUSCTRL_PERFCTR3 261 // Description : Bus fabric performance counter 3 262 // Busfabric saturating performance counter 3 263 // Count some event signal from the busfabric arbiters. 264 // Write any value to clear. Select an event to count using 265 // PERFSEL3 266 #define BUSCTRL_PERFCTR3_OFFSET 0x00000020 267 #define BUSCTRL_PERFCTR3_BITS 0x00ffffff 268 #define BUSCTRL_PERFCTR3_RESET 0x00000000 269 #define BUSCTRL_PERFCTR3_MSB 23 270 #define BUSCTRL_PERFCTR3_LSB 0 271 #define BUSCTRL_PERFCTR3_ACCESS "WC" 272 // ============================================================================= 273 // Register : BUSCTRL_PERFSEL3 274 // Description : Bus fabric performance event select for PERFCTR3 275 // Select an event for PERFCTR3. Count either contested accesses, 276 // or all accesses, on a downstream port of the main crossbar. 277 // 0x00 -> apb_contested 278 // 0x01 -> apb 279 // 0x02 -> fastperi_contested 280 // 0x03 -> fastperi 281 // 0x04 -> sram5_contested 282 // 0x05 -> sram5 283 // 0x06 -> sram4_contested 284 // 0x07 -> sram4 285 // 0x08 -> sram3_contested 286 // 0x09 -> sram3 287 // 0x0a -> sram2_contested 288 // 0x0b -> sram2 289 // 0x0c -> sram1_contested 290 // 0x0d -> sram1 291 // 0x0e -> sram0_contested 292 // 0x0f -> sram0 293 // 0x10 -> xip_main_contested 294 // 0x11 -> xip_main 295 // 0x12 -> rom_contested 296 // 0x13 -> rom 297 #define BUSCTRL_PERFSEL3_OFFSET 0x00000024 298 #define BUSCTRL_PERFSEL3_BITS 0x0000001f 299 #define BUSCTRL_PERFSEL3_RESET 0x0000001f 300 #define BUSCTRL_PERFSEL3_MSB 4 301 #define BUSCTRL_PERFSEL3_LSB 0 302 #define BUSCTRL_PERFSEL3_ACCESS "RW" 303 #define BUSCTRL_PERFSEL3_VALUE_APB_CONTESTED 0x00 304 #define BUSCTRL_PERFSEL3_VALUE_APB 0x01 305 #define BUSCTRL_PERFSEL3_VALUE_FASTPERI_CONTESTED 0x02 306 #define BUSCTRL_PERFSEL3_VALUE_FASTPERI 0x03 307 #define BUSCTRL_PERFSEL3_VALUE_SRAM5_CONTESTED 0x04 308 #define BUSCTRL_PERFSEL3_VALUE_SRAM5 0x05 309 #define BUSCTRL_PERFSEL3_VALUE_SRAM4_CONTESTED 0x06 310 #define BUSCTRL_PERFSEL3_VALUE_SRAM4 0x07 311 #define BUSCTRL_PERFSEL3_VALUE_SRAM3_CONTESTED 0x08 312 #define BUSCTRL_PERFSEL3_VALUE_SRAM3 0x09 313 #define BUSCTRL_PERFSEL3_VALUE_SRAM2_CONTESTED 0x0a 314 #define BUSCTRL_PERFSEL3_VALUE_SRAM2 0x0b 315 #define BUSCTRL_PERFSEL3_VALUE_SRAM1_CONTESTED 0x0c 316 #define BUSCTRL_PERFSEL3_VALUE_SRAM1 0x0d 317 #define BUSCTRL_PERFSEL3_VALUE_SRAM0_CONTESTED 0x0e 318 #define BUSCTRL_PERFSEL3_VALUE_SRAM0 0x0f 319 #define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN_CONTESTED 0x10 320 #define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN 0x11 321 #define BUSCTRL_PERFSEL3_VALUE_ROM_CONTESTED 0x12 322 #define BUSCTRL_PERFSEL3_VALUE_ROM 0x13 323 // ============================================================================= 324 #endif // HARDWARE_REGS_BUSCTRL_DEFINED 325