1 /** 2 * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 // ============================================================================= 7 // Register block : M0PLUS 8 // Version : 1 9 // Bus type : ahbl 10 // Description : None 11 // ============================================================================= 12 #ifndef HARDWARE_REGS_M0PLUS_DEFINED 13 #define HARDWARE_REGS_M0PLUS_DEFINED 14 // ============================================================================= 15 // Register : M0PLUS_SYST_CSR 16 // Description : Use the SysTick Control and Status Register to enable the 17 // SysTick features. 18 #define M0PLUS_SYST_CSR_OFFSET 0x0000e010 19 #define M0PLUS_SYST_CSR_BITS 0x00010007 20 #define M0PLUS_SYST_CSR_RESET 0x00000000 21 // ----------------------------------------------------------------------------- 22 // Field : M0PLUS_SYST_CSR_COUNTFLAG 23 // Description : Returns 1 if timer counted to 0 since last time this was read. 24 // Clears on read by application or debugger. 25 #define M0PLUS_SYST_CSR_COUNTFLAG_RESET 0x0 26 #define M0PLUS_SYST_CSR_COUNTFLAG_BITS 0x00010000 27 #define M0PLUS_SYST_CSR_COUNTFLAG_MSB 16 28 #define M0PLUS_SYST_CSR_COUNTFLAG_LSB 16 29 #define M0PLUS_SYST_CSR_COUNTFLAG_ACCESS "RO" 30 // ----------------------------------------------------------------------------- 31 // Field : M0PLUS_SYST_CSR_CLKSOURCE 32 // Description : SysTick clock source. Always reads as one if SYST_CALIB reports 33 // NOREF. 34 // Selects the SysTick timer clock source: 35 // 0 = External reference clock. 36 // 1 = Processor clock. 37 #define M0PLUS_SYST_CSR_CLKSOURCE_RESET 0x0 38 #define M0PLUS_SYST_CSR_CLKSOURCE_BITS 0x00000004 39 #define M0PLUS_SYST_CSR_CLKSOURCE_MSB 2 40 #define M0PLUS_SYST_CSR_CLKSOURCE_LSB 2 41 #define M0PLUS_SYST_CSR_CLKSOURCE_ACCESS "RW" 42 // ----------------------------------------------------------------------------- 43 // Field : M0PLUS_SYST_CSR_TICKINT 44 // Description : Enables SysTick exception request: 45 // 0 = Counting down to zero does not assert the SysTick exception 46 // request. 47 // 1 = Counting down to zero to asserts the SysTick exception 48 // request. 49 #define M0PLUS_SYST_CSR_TICKINT_RESET 0x0 50 #define M0PLUS_SYST_CSR_TICKINT_BITS 0x00000002 51 #define M0PLUS_SYST_CSR_TICKINT_MSB 1 52 #define M0PLUS_SYST_CSR_TICKINT_LSB 1 53 #define M0PLUS_SYST_CSR_TICKINT_ACCESS "RW" 54 // ----------------------------------------------------------------------------- 55 // Field : M0PLUS_SYST_CSR_ENABLE 56 // Description : Enable SysTick counter: 57 // 0 = Counter disabled. 58 // 1 = Counter enabled. 59 #define M0PLUS_SYST_CSR_ENABLE_RESET 0x0 60 #define M0PLUS_SYST_CSR_ENABLE_BITS 0x00000001 61 #define M0PLUS_SYST_CSR_ENABLE_MSB 0 62 #define M0PLUS_SYST_CSR_ENABLE_LSB 0 63 #define M0PLUS_SYST_CSR_ENABLE_ACCESS "RW" 64 // ============================================================================= 65 // Register : M0PLUS_SYST_RVR 66 // Description : Use the SysTick Reload Value Register to specify the start 67 // value to load into the current value register when the counter 68 // reaches 0. It can be any value between 0 and 0x00FFFFFF. A 69 // start value of 0 is possible, but has no effect because the 70 // SysTick interrupt and COUNTFLAG are activated when counting 71 // from 1 to 0. The reset value of this register is UNKNOWN. 72 // To generate a multi-shot timer with a period of N processor 73 // clock cycles, use a RELOAD value of N-1. For example, if the 74 // SysTick interrupt is required every 100 clock pulses, set 75 // RELOAD to 99. 76 #define M0PLUS_SYST_RVR_OFFSET 0x0000e014 77 #define M0PLUS_SYST_RVR_BITS 0x00ffffff 78 #define M0PLUS_SYST_RVR_RESET 0x00000000 79 // ----------------------------------------------------------------------------- 80 // Field : M0PLUS_SYST_RVR_RELOAD 81 // Description : Value to load into the SysTick Current Value Register when the 82 // counter reaches 0. 83 #define M0PLUS_SYST_RVR_RELOAD_RESET 0x000000 84 #define M0PLUS_SYST_RVR_RELOAD_BITS 0x00ffffff 85 #define M0PLUS_SYST_RVR_RELOAD_MSB 23 86 #define M0PLUS_SYST_RVR_RELOAD_LSB 0 87 #define M0PLUS_SYST_RVR_RELOAD_ACCESS "RW" 88 // ============================================================================= 89 // Register : M0PLUS_SYST_CVR 90 // Description : Use the SysTick Current Value Register to find the current 91 // value in the register. The reset value of this register is 92 // UNKNOWN. 93 #define M0PLUS_SYST_CVR_OFFSET 0x0000e018 94 #define M0PLUS_SYST_CVR_BITS 0x00ffffff 95 #define M0PLUS_SYST_CVR_RESET 0x00000000 96 // ----------------------------------------------------------------------------- 97 // Field : M0PLUS_SYST_CVR_CURRENT 98 // Description : Reads return the current value of the SysTick counter. This 99 // register is write-clear. Writing to it with any value clears 100 // the register to 0. Clearing this register also clears the 101 // COUNTFLAG bit of the SysTick Control and Status Register. 102 #define M0PLUS_SYST_CVR_CURRENT_RESET 0x000000 103 #define M0PLUS_SYST_CVR_CURRENT_BITS 0x00ffffff 104 #define M0PLUS_SYST_CVR_CURRENT_MSB 23 105 #define M0PLUS_SYST_CVR_CURRENT_LSB 0 106 #define M0PLUS_SYST_CVR_CURRENT_ACCESS "RW" 107 // ============================================================================= 108 // Register : M0PLUS_SYST_CALIB 109 // Description : Use the SysTick Calibration Value Register to enable software 110 // to scale to any required speed using divide and multiply. 111 #define M0PLUS_SYST_CALIB_OFFSET 0x0000e01c 112 #define M0PLUS_SYST_CALIB_BITS 0xc0ffffff 113 #define M0PLUS_SYST_CALIB_RESET 0x00000000 114 // ----------------------------------------------------------------------------- 115 // Field : M0PLUS_SYST_CALIB_NOREF 116 // Description : If reads as 1, the Reference clock is not provided - the 117 // CLKSOURCE bit of the SysTick Control and Status register will 118 // be forced to 1 and cannot be cleared to 0. 119 #define M0PLUS_SYST_CALIB_NOREF_RESET 0x0 120 #define M0PLUS_SYST_CALIB_NOREF_BITS 0x80000000 121 #define M0PLUS_SYST_CALIB_NOREF_MSB 31 122 #define M0PLUS_SYST_CALIB_NOREF_LSB 31 123 #define M0PLUS_SYST_CALIB_NOREF_ACCESS "RO" 124 // ----------------------------------------------------------------------------- 125 // Field : M0PLUS_SYST_CALIB_SKEW 126 // Description : If reads as 1, the calibration value for 10ms is inexact (due 127 // to clock frequency). 128 #define M0PLUS_SYST_CALIB_SKEW_RESET 0x0 129 #define M0PLUS_SYST_CALIB_SKEW_BITS 0x40000000 130 #define M0PLUS_SYST_CALIB_SKEW_MSB 30 131 #define M0PLUS_SYST_CALIB_SKEW_LSB 30 132 #define M0PLUS_SYST_CALIB_SKEW_ACCESS "RO" 133 // ----------------------------------------------------------------------------- 134 // Field : M0PLUS_SYST_CALIB_TENMS 135 // Description : An optional Reload value to be used for 10ms (100Hz) timing, 136 // subject to system clock skew errors. If the value reads as 0, 137 // the calibration value is not known. 138 #define M0PLUS_SYST_CALIB_TENMS_RESET 0x000000 139 #define M0PLUS_SYST_CALIB_TENMS_BITS 0x00ffffff 140 #define M0PLUS_SYST_CALIB_TENMS_MSB 23 141 #define M0PLUS_SYST_CALIB_TENMS_LSB 0 142 #define M0PLUS_SYST_CALIB_TENMS_ACCESS "RO" 143 // ============================================================================= 144 // Register : M0PLUS_NVIC_ISER 145 // Description : Use the Interrupt Set-Enable Register to enable interrupts and 146 // determine which interrupts are currently enabled. 147 // If a pending interrupt is enabled, the NVIC activates the 148 // interrupt based on its priority. If an interrupt is not 149 // enabled, asserting its interrupt signal changes the interrupt 150 // state to pending, but the NVIC never activates the interrupt, 151 // regardless of its priority. 152 #define M0PLUS_NVIC_ISER_OFFSET 0x0000e100 153 #define M0PLUS_NVIC_ISER_BITS 0xffffffff 154 #define M0PLUS_NVIC_ISER_RESET 0x00000000 155 // ----------------------------------------------------------------------------- 156 // Field : M0PLUS_NVIC_ISER_SETENA 157 // Description : Interrupt set-enable bits. 158 // Write: 159 // 0 = No effect. 160 // 1 = Enable interrupt. 161 // Read: 162 // 0 = Interrupt disabled. 163 // 1 = Interrupt enabled. 164 #define M0PLUS_NVIC_ISER_SETENA_RESET 0x00000000 165 #define M0PLUS_NVIC_ISER_SETENA_BITS 0xffffffff 166 #define M0PLUS_NVIC_ISER_SETENA_MSB 31 167 #define M0PLUS_NVIC_ISER_SETENA_LSB 0 168 #define M0PLUS_NVIC_ISER_SETENA_ACCESS "RW" 169 // ============================================================================= 170 // Register : M0PLUS_NVIC_ICER 171 // Description : Use the Interrupt Clear-Enable Registers to disable interrupts 172 // and determine which interrupts are currently enabled. 173 #define M0PLUS_NVIC_ICER_OFFSET 0x0000e180 174 #define M0PLUS_NVIC_ICER_BITS 0xffffffff 175 #define M0PLUS_NVIC_ICER_RESET 0x00000000 176 // ----------------------------------------------------------------------------- 177 // Field : M0PLUS_NVIC_ICER_CLRENA 178 // Description : Interrupt clear-enable bits. 179 // Write: 180 // 0 = No effect. 181 // 1 = Disable interrupt. 182 // Read: 183 // 0 = Interrupt disabled. 184 // 1 = Interrupt enabled. 185 #define M0PLUS_NVIC_ICER_CLRENA_RESET 0x00000000 186 #define M0PLUS_NVIC_ICER_CLRENA_BITS 0xffffffff 187 #define M0PLUS_NVIC_ICER_CLRENA_MSB 31 188 #define M0PLUS_NVIC_ICER_CLRENA_LSB 0 189 #define M0PLUS_NVIC_ICER_CLRENA_ACCESS "RW" 190 // ============================================================================= 191 // Register : M0PLUS_NVIC_ISPR 192 // Description : The NVIC_ISPR forces interrupts into the pending state, and 193 // shows which interrupts are pending. 194 #define M0PLUS_NVIC_ISPR_OFFSET 0x0000e200 195 #define M0PLUS_NVIC_ISPR_BITS 0xffffffff 196 #define M0PLUS_NVIC_ISPR_RESET 0x00000000 197 // ----------------------------------------------------------------------------- 198 // Field : M0PLUS_NVIC_ISPR_SETPEND 199 // Description : Interrupt set-pending bits. 200 // Write: 201 // 0 = No effect. 202 // 1 = Changes interrupt state to pending. 203 // Read: 204 // 0 = Interrupt is not pending. 205 // 1 = Interrupt is pending. 206 // Note: Writing 1 to the NVIC_ISPR bit corresponding to: 207 // An interrupt that is pending has no effect. 208 // A disabled interrupt sets the state of that interrupt to 209 // pending. 210 #define M0PLUS_NVIC_ISPR_SETPEND_RESET 0x00000000 211 #define M0PLUS_NVIC_ISPR_SETPEND_BITS 0xffffffff 212 #define M0PLUS_NVIC_ISPR_SETPEND_MSB 31 213 #define M0PLUS_NVIC_ISPR_SETPEND_LSB 0 214 #define M0PLUS_NVIC_ISPR_SETPEND_ACCESS "RW" 215 // ============================================================================= 216 // Register : M0PLUS_NVIC_ICPR 217 // Description : Use the Interrupt Clear-Pending Register to clear pending 218 // interrupts and determine which interrupts are currently 219 // pending. 220 #define M0PLUS_NVIC_ICPR_OFFSET 0x0000e280 221 #define M0PLUS_NVIC_ICPR_BITS 0xffffffff 222 #define M0PLUS_NVIC_ICPR_RESET 0x00000000 223 // ----------------------------------------------------------------------------- 224 // Field : M0PLUS_NVIC_ICPR_CLRPEND 225 // Description : Interrupt clear-pending bits. 226 // Write: 227 // 0 = No effect. 228 // 1 = Removes pending state and interrupt. 229 // Read: 230 // 0 = Interrupt is not pending. 231 // 1 = Interrupt is pending. 232 #define M0PLUS_NVIC_ICPR_CLRPEND_RESET 0x00000000 233 #define M0PLUS_NVIC_ICPR_CLRPEND_BITS 0xffffffff 234 #define M0PLUS_NVIC_ICPR_CLRPEND_MSB 31 235 #define M0PLUS_NVIC_ICPR_CLRPEND_LSB 0 236 #define M0PLUS_NVIC_ICPR_CLRPEND_ACCESS "RW" 237 // ============================================================================= 238 // Register : M0PLUS_NVIC_IPR0 239 // Description : Use the Interrupt Priority Registers to assign a priority from 240 // 0 to 3 to each of the available interrupts. 0 is the highest 241 // priority, and 3 is the lowest. 242 // Note: Writing 1 to an NVIC_ICPR bit does not affect the active 243 // state of the corresponding interrupt. 244 // These registers are only word-accessible 245 #define M0PLUS_NVIC_IPR0_OFFSET 0x0000e400 246 #define M0PLUS_NVIC_IPR0_BITS 0xc0c0c0c0 247 #define M0PLUS_NVIC_IPR0_RESET 0x00000000 248 // ----------------------------------------------------------------------------- 249 // Field : M0PLUS_NVIC_IPR0_IP_3 250 // Description : Priority of interrupt 3 251 #define M0PLUS_NVIC_IPR0_IP_3_RESET 0x0 252 #define M0PLUS_NVIC_IPR0_IP_3_BITS 0xc0000000 253 #define M0PLUS_NVIC_IPR0_IP_3_MSB 31 254 #define M0PLUS_NVIC_IPR0_IP_3_LSB 30 255 #define M0PLUS_NVIC_IPR0_IP_3_ACCESS "RW" 256 // ----------------------------------------------------------------------------- 257 // Field : M0PLUS_NVIC_IPR0_IP_2 258 // Description : Priority of interrupt 2 259 #define M0PLUS_NVIC_IPR0_IP_2_RESET 0x0 260 #define M0PLUS_NVIC_IPR0_IP_2_BITS 0x00c00000 261 #define M0PLUS_NVIC_IPR0_IP_2_MSB 23 262 #define M0PLUS_NVIC_IPR0_IP_2_LSB 22 263 #define M0PLUS_NVIC_IPR0_IP_2_ACCESS "RW" 264 // ----------------------------------------------------------------------------- 265 // Field : M0PLUS_NVIC_IPR0_IP_1 266 // Description : Priority of interrupt 1 267 #define M0PLUS_NVIC_IPR0_IP_1_RESET 0x0 268 #define M0PLUS_NVIC_IPR0_IP_1_BITS 0x0000c000 269 #define M0PLUS_NVIC_IPR0_IP_1_MSB 15 270 #define M0PLUS_NVIC_IPR0_IP_1_LSB 14 271 #define M0PLUS_NVIC_IPR0_IP_1_ACCESS "RW" 272 // ----------------------------------------------------------------------------- 273 // Field : M0PLUS_NVIC_IPR0_IP_0 274 // Description : Priority of interrupt 0 275 #define M0PLUS_NVIC_IPR0_IP_0_RESET 0x0 276 #define M0PLUS_NVIC_IPR0_IP_0_BITS 0x000000c0 277 #define M0PLUS_NVIC_IPR0_IP_0_MSB 7 278 #define M0PLUS_NVIC_IPR0_IP_0_LSB 6 279 #define M0PLUS_NVIC_IPR0_IP_0_ACCESS "RW" 280 // ============================================================================= 281 // Register : M0PLUS_NVIC_IPR1 282 // Description : Use the Interrupt Priority Registers to assign a priority from 283 // 0 to 3 to each of the available interrupts. 0 is the highest 284 // priority, and 3 is the lowest. 285 #define M0PLUS_NVIC_IPR1_OFFSET 0x0000e404 286 #define M0PLUS_NVIC_IPR1_BITS 0xc0c0c0c0 287 #define M0PLUS_NVIC_IPR1_RESET 0x00000000 288 // ----------------------------------------------------------------------------- 289 // Field : M0PLUS_NVIC_IPR1_IP_7 290 // Description : Priority of interrupt 7 291 #define M0PLUS_NVIC_IPR1_IP_7_RESET 0x0 292 #define M0PLUS_NVIC_IPR1_IP_7_BITS 0xc0000000 293 #define M0PLUS_NVIC_IPR1_IP_7_MSB 31 294 #define M0PLUS_NVIC_IPR1_IP_7_LSB 30 295 #define M0PLUS_NVIC_IPR1_IP_7_ACCESS "RW" 296 // ----------------------------------------------------------------------------- 297 // Field : M0PLUS_NVIC_IPR1_IP_6 298 // Description : Priority of interrupt 6 299 #define M0PLUS_NVIC_IPR1_IP_6_RESET 0x0 300 #define M0PLUS_NVIC_IPR1_IP_6_BITS 0x00c00000 301 #define M0PLUS_NVIC_IPR1_IP_6_MSB 23 302 #define M0PLUS_NVIC_IPR1_IP_6_LSB 22 303 #define M0PLUS_NVIC_IPR1_IP_6_ACCESS "RW" 304 // ----------------------------------------------------------------------------- 305 // Field : M0PLUS_NVIC_IPR1_IP_5 306 // Description : Priority of interrupt 5 307 #define M0PLUS_NVIC_IPR1_IP_5_RESET 0x0 308 #define M0PLUS_NVIC_IPR1_IP_5_BITS 0x0000c000 309 #define M0PLUS_NVIC_IPR1_IP_5_MSB 15 310 #define M0PLUS_NVIC_IPR1_IP_5_LSB 14 311 #define M0PLUS_NVIC_IPR1_IP_5_ACCESS "RW" 312 // ----------------------------------------------------------------------------- 313 // Field : M0PLUS_NVIC_IPR1_IP_4 314 // Description : Priority of interrupt 4 315 #define M0PLUS_NVIC_IPR1_IP_4_RESET 0x0 316 #define M0PLUS_NVIC_IPR1_IP_4_BITS 0x000000c0 317 #define M0PLUS_NVIC_IPR1_IP_4_MSB 7 318 #define M0PLUS_NVIC_IPR1_IP_4_LSB 6 319 #define M0PLUS_NVIC_IPR1_IP_4_ACCESS "RW" 320 // ============================================================================= 321 // Register : M0PLUS_NVIC_IPR2 322 // Description : Use the Interrupt Priority Registers to assign a priority from 323 // 0 to 3 to each of the available interrupts. 0 is the highest 324 // priority, and 3 is the lowest. 325 #define M0PLUS_NVIC_IPR2_OFFSET 0x0000e408 326 #define M0PLUS_NVIC_IPR2_BITS 0xc0c0c0c0 327 #define M0PLUS_NVIC_IPR2_RESET 0x00000000 328 // ----------------------------------------------------------------------------- 329 // Field : M0PLUS_NVIC_IPR2_IP_11 330 // Description : Priority of interrupt 11 331 #define M0PLUS_NVIC_IPR2_IP_11_RESET 0x0 332 #define M0PLUS_NVIC_IPR2_IP_11_BITS 0xc0000000 333 #define M0PLUS_NVIC_IPR2_IP_11_MSB 31 334 #define M0PLUS_NVIC_IPR2_IP_11_LSB 30 335 #define M0PLUS_NVIC_IPR2_IP_11_ACCESS "RW" 336 // ----------------------------------------------------------------------------- 337 // Field : M0PLUS_NVIC_IPR2_IP_10 338 // Description : Priority of interrupt 10 339 #define M0PLUS_NVIC_IPR2_IP_10_RESET 0x0 340 #define M0PLUS_NVIC_IPR2_IP_10_BITS 0x00c00000 341 #define M0PLUS_NVIC_IPR2_IP_10_MSB 23 342 #define M0PLUS_NVIC_IPR2_IP_10_LSB 22 343 #define M0PLUS_NVIC_IPR2_IP_10_ACCESS "RW" 344 // ----------------------------------------------------------------------------- 345 // Field : M0PLUS_NVIC_IPR2_IP_9 346 // Description : Priority of interrupt 9 347 #define M0PLUS_NVIC_IPR2_IP_9_RESET 0x0 348 #define M0PLUS_NVIC_IPR2_IP_9_BITS 0x0000c000 349 #define M0PLUS_NVIC_IPR2_IP_9_MSB 15 350 #define M0PLUS_NVIC_IPR2_IP_9_LSB 14 351 #define M0PLUS_NVIC_IPR2_IP_9_ACCESS "RW" 352 // ----------------------------------------------------------------------------- 353 // Field : M0PLUS_NVIC_IPR2_IP_8 354 // Description : Priority of interrupt 8 355 #define M0PLUS_NVIC_IPR2_IP_8_RESET 0x0 356 #define M0PLUS_NVIC_IPR2_IP_8_BITS 0x000000c0 357 #define M0PLUS_NVIC_IPR2_IP_8_MSB 7 358 #define M0PLUS_NVIC_IPR2_IP_8_LSB 6 359 #define M0PLUS_NVIC_IPR2_IP_8_ACCESS "RW" 360 // ============================================================================= 361 // Register : M0PLUS_NVIC_IPR3 362 // Description : Use the Interrupt Priority Registers to assign a priority from 363 // 0 to 3 to each of the available interrupts. 0 is the highest 364 // priority, and 3 is the lowest. 365 #define M0PLUS_NVIC_IPR3_OFFSET 0x0000e40c 366 #define M0PLUS_NVIC_IPR3_BITS 0xc0c0c0c0 367 #define M0PLUS_NVIC_IPR3_RESET 0x00000000 368 // ----------------------------------------------------------------------------- 369 // Field : M0PLUS_NVIC_IPR3_IP_15 370 // Description : Priority of interrupt 15 371 #define M0PLUS_NVIC_IPR3_IP_15_RESET 0x0 372 #define M0PLUS_NVIC_IPR3_IP_15_BITS 0xc0000000 373 #define M0PLUS_NVIC_IPR3_IP_15_MSB 31 374 #define M0PLUS_NVIC_IPR3_IP_15_LSB 30 375 #define M0PLUS_NVIC_IPR3_IP_15_ACCESS "RW" 376 // ----------------------------------------------------------------------------- 377 // Field : M0PLUS_NVIC_IPR3_IP_14 378 // Description : Priority of interrupt 14 379 #define M0PLUS_NVIC_IPR3_IP_14_RESET 0x0 380 #define M0PLUS_NVIC_IPR3_IP_14_BITS 0x00c00000 381 #define M0PLUS_NVIC_IPR3_IP_14_MSB 23 382 #define M0PLUS_NVIC_IPR3_IP_14_LSB 22 383 #define M0PLUS_NVIC_IPR3_IP_14_ACCESS "RW" 384 // ----------------------------------------------------------------------------- 385 // Field : M0PLUS_NVIC_IPR3_IP_13 386 // Description : Priority of interrupt 13 387 #define M0PLUS_NVIC_IPR3_IP_13_RESET 0x0 388 #define M0PLUS_NVIC_IPR3_IP_13_BITS 0x0000c000 389 #define M0PLUS_NVIC_IPR3_IP_13_MSB 15 390 #define M0PLUS_NVIC_IPR3_IP_13_LSB 14 391 #define M0PLUS_NVIC_IPR3_IP_13_ACCESS "RW" 392 // ----------------------------------------------------------------------------- 393 // Field : M0PLUS_NVIC_IPR3_IP_12 394 // Description : Priority of interrupt 12 395 #define M0PLUS_NVIC_IPR3_IP_12_RESET 0x0 396 #define M0PLUS_NVIC_IPR3_IP_12_BITS 0x000000c0 397 #define M0PLUS_NVIC_IPR3_IP_12_MSB 7 398 #define M0PLUS_NVIC_IPR3_IP_12_LSB 6 399 #define M0PLUS_NVIC_IPR3_IP_12_ACCESS "RW" 400 // ============================================================================= 401 // Register : M0PLUS_NVIC_IPR4 402 // Description : Use the Interrupt Priority Registers to assign a priority from 403 // 0 to 3 to each of the available interrupts. 0 is the highest 404 // priority, and 3 is the lowest. 405 #define M0PLUS_NVIC_IPR4_OFFSET 0x0000e410 406 #define M0PLUS_NVIC_IPR4_BITS 0xc0c0c0c0 407 #define M0PLUS_NVIC_IPR4_RESET 0x00000000 408 // ----------------------------------------------------------------------------- 409 // Field : M0PLUS_NVIC_IPR4_IP_19 410 // Description : Priority of interrupt 19 411 #define M0PLUS_NVIC_IPR4_IP_19_RESET 0x0 412 #define M0PLUS_NVIC_IPR4_IP_19_BITS 0xc0000000 413 #define M0PLUS_NVIC_IPR4_IP_19_MSB 31 414 #define M0PLUS_NVIC_IPR4_IP_19_LSB 30 415 #define M0PLUS_NVIC_IPR4_IP_19_ACCESS "RW" 416 // ----------------------------------------------------------------------------- 417 // Field : M0PLUS_NVIC_IPR4_IP_18 418 // Description : Priority of interrupt 18 419 #define M0PLUS_NVIC_IPR4_IP_18_RESET 0x0 420 #define M0PLUS_NVIC_IPR4_IP_18_BITS 0x00c00000 421 #define M0PLUS_NVIC_IPR4_IP_18_MSB 23 422 #define M0PLUS_NVIC_IPR4_IP_18_LSB 22 423 #define M0PLUS_NVIC_IPR4_IP_18_ACCESS "RW" 424 // ----------------------------------------------------------------------------- 425 // Field : M0PLUS_NVIC_IPR4_IP_17 426 // Description : Priority of interrupt 17 427 #define M0PLUS_NVIC_IPR4_IP_17_RESET 0x0 428 #define M0PLUS_NVIC_IPR4_IP_17_BITS 0x0000c000 429 #define M0PLUS_NVIC_IPR4_IP_17_MSB 15 430 #define M0PLUS_NVIC_IPR4_IP_17_LSB 14 431 #define M0PLUS_NVIC_IPR4_IP_17_ACCESS "RW" 432 // ----------------------------------------------------------------------------- 433 // Field : M0PLUS_NVIC_IPR4_IP_16 434 // Description : Priority of interrupt 16 435 #define M0PLUS_NVIC_IPR4_IP_16_RESET 0x0 436 #define M0PLUS_NVIC_IPR4_IP_16_BITS 0x000000c0 437 #define M0PLUS_NVIC_IPR4_IP_16_MSB 7 438 #define M0PLUS_NVIC_IPR4_IP_16_LSB 6 439 #define M0PLUS_NVIC_IPR4_IP_16_ACCESS "RW" 440 // ============================================================================= 441 // Register : M0PLUS_NVIC_IPR5 442 // Description : Use the Interrupt Priority Registers to assign a priority from 443 // 0 to 3 to each of the available interrupts. 0 is the highest 444 // priority, and 3 is the lowest. 445 #define M0PLUS_NVIC_IPR5_OFFSET 0x0000e414 446 #define M0PLUS_NVIC_IPR5_BITS 0xc0c0c0c0 447 #define M0PLUS_NVIC_IPR5_RESET 0x00000000 448 // ----------------------------------------------------------------------------- 449 // Field : M0PLUS_NVIC_IPR5_IP_23 450 // Description : Priority of interrupt 23 451 #define M0PLUS_NVIC_IPR5_IP_23_RESET 0x0 452 #define M0PLUS_NVIC_IPR5_IP_23_BITS 0xc0000000 453 #define M0PLUS_NVIC_IPR5_IP_23_MSB 31 454 #define M0PLUS_NVIC_IPR5_IP_23_LSB 30 455 #define M0PLUS_NVIC_IPR5_IP_23_ACCESS "RW" 456 // ----------------------------------------------------------------------------- 457 // Field : M0PLUS_NVIC_IPR5_IP_22 458 // Description : Priority of interrupt 22 459 #define M0PLUS_NVIC_IPR5_IP_22_RESET 0x0 460 #define M0PLUS_NVIC_IPR5_IP_22_BITS 0x00c00000 461 #define M0PLUS_NVIC_IPR5_IP_22_MSB 23 462 #define M0PLUS_NVIC_IPR5_IP_22_LSB 22 463 #define M0PLUS_NVIC_IPR5_IP_22_ACCESS "RW" 464 // ----------------------------------------------------------------------------- 465 // Field : M0PLUS_NVIC_IPR5_IP_21 466 // Description : Priority of interrupt 21 467 #define M0PLUS_NVIC_IPR5_IP_21_RESET 0x0 468 #define M0PLUS_NVIC_IPR5_IP_21_BITS 0x0000c000 469 #define M0PLUS_NVIC_IPR5_IP_21_MSB 15 470 #define M0PLUS_NVIC_IPR5_IP_21_LSB 14 471 #define M0PLUS_NVIC_IPR5_IP_21_ACCESS "RW" 472 // ----------------------------------------------------------------------------- 473 // Field : M0PLUS_NVIC_IPR5_IP_20 474 // Description : Priority of interrupt 20 475 #define M0PLUS_NVIC_IPR5_IP_20_RESET 0x0 476 #define M0PLUS_NVIC_IPR5_IP_20_BITS 0x000000c0 477 #define M0PLUS_NVIC_IPR5_IP_20_MSB 7 478 #define M0PLUS_NVIC_IPR5_IP_20_LSB 6 479 #define M0PLUS_NVIC_IPR5_IP_20_ACCESS "RW" 480 // ============================================================================= 481 // Register : M0PLUS_NVIC_IPR6 482 // Description : Use the Interrupt Priority Registers to assign a priority from 483 // 0 to 3 to each of the available interrupts. 0 is the highest 484 // priority, and 3 is the lowest. 485 #define M0PLUS_NVIC_IPR6_OFFSET 0x0000e418 486 #define M0PLUS_NVIC_IPR6_BITS 0xc0c0c0c0 487 #define M0PLUS_NVIC_IPR6_RESET 0x00000000 488 // ----------------------------------------------------------------------------- 489 // Field : M0PLUS_NVIC_IPR6_IP_27 490 // Description : Priority of interrupt 27 491 #define M0PLUS_NVIC_IPR6_IP_27_RESET 0x0 492 #define M0PLUS_NVIC_IPR6_IP_27_BITS 0xc0000000 493 #define M0PLUS_NVIC_IPR6_IP_27_MSB 31 494 #define M0PLUS_NVIC_IPR6_IP_27_LSB 30 495 #define M0PLUS_NVIC_IPR6_IP_27_ACCESS "RW" 496 // ----------------------------------------------------------------------------- 497 // Field : M0PLUS_NVIC_IPR6_IP_26 498 // Description : Priority of interrupt 26 499 #define M0PLUS_NVIC_IPR6_IP_26_RESET 0x0 500 #define M0PLUS_NVIC_IPR6_IP_26_BITS 0x00c00000 501 #define M0PLUS_NVIC_IPR6_IP_26_MSB 23 502 #define M0PLUS_NVIC_IPR6_IP_26_LSB 22 503 #define M0PLUS_NVIC_IPR6_IP_26_ACCESS "RW" 504 // ----------------------------------------------------------------------------- 505 // Field : M0PLUS_NVIC_IPR6_IP_25 506 // Description : Priority of interrupt 25 507 #define M0PLUS_NVIC_IPR6_IP_25_RESET 0x0 508 #define M0PLUS_NVIC_IPR6_IP_25_BITS 0x0000c000 509 #define M0PLUS_NVIC_IPR6_IP_25_MSB 15 510 #define M0PLUS_NVIC_IPR6_IP_25_LSB 14 511 #define M0PLUS_NVIC_IPR6_IP_25_ACCESS "RW" 512 // ----------------------------------------------------------------------------- 513 // Field : M0PLUS_NVIC_IPR6_IP_24 514 // Description : Priority of interrupt 24 515 #define M0PLUS_NVIC_IPR6_IP_24_RESET 0x0 516 #define M0PLUS_NVIC_IPR6_IP_24_BITS 0x000000c0 517 #define M0PLUS_NVIC_IPR6_IP_24_MSB 7 518 #define M0PLUS_NVIC_IPR6_IP_24_LSB 6 519 #define M0PLUS_NVIC_IPR6_IP_24_ACCESS "RW" 520 // ============================================================================= 521 // Register : M0PLUS_NVIC_IPR7 522 // Description : Use the Interrupt Priority Registers to assign a priority from 523 // 0 to 3 to each of the available interrupts. 0 is the highest 524 // priority, and 3 is the lowest. 525 #define M0PLUS_NVIC_IPR7_OFFSET 0x0000e41c 526 #define M0PLUS_NVIC_IPR7_BITS 0xc0c0c0c0 527 #define M0PLUS_NVIC_IPR7_RESET 0x00000000 528 // ----------------------------------------------------------------------------- 529 // Field : M0PLUS_NVIC_IPR7_IP_31 530 // Description : Priority of interrupt 31 531 #define M0PLUS_NVIC_IPR7_IP_31_RESET 0x0 532 #define M0PLUS_NVIC_IPR7_IP_31_BITS 0xc0000000 533 #define M0PLUS_NVIC_IPR7_IP_31_MSB 31 534 #define M0PLUS_NVIC_IPR7_IP_31_LSB 30 535 #define M0PLUS_NVIC_IPR7_IP_31_ACCESS "RW" 536 // ----------------------------------------------------------------------------- 537 // Field : M0PLUS_NVIC_IPR7_IP_30 538 // Description : Priority of interrupt 30 539 #define M0PLUS_NVIC_IPR7_IP_30_RESET 0x0 540 #define M0PLUS_NVIC_IPR7_IP_30_BITS 0x00c00000 541 #define M0PLUS_NVIC_IPR7_IP_30_MSB 23 542 #define M0PLUS_NVIC_IPR7_IP_30_LSB 22 543 #define M0PLUS_NVIC_IPR7_IP_30_ACCESS "RW" 544 // ----------------------------------------------------------------------------- 545 // Field : M0PLUS_NVIC_IPR7_IP_29 546 // Description : Priority of interrupt 29 547 #define M0PLUS_NVIC_IPR7_IP_29_RESET 0x0 548 #define M0PLUS_NVIC_IPR7_IP_29_BITS 0x0000c000 549 #define M0PLUS_NVIC_IPR7_IP_29_MSB 15 550 #define M0PLUS_NVIC_IPR7_IP_29_LSB 14 551 #define M0PLUS_NVIC_IPR7_IP_29_ACCESS "RW" 552 // ----------------------------------------------------------------------------- 553 // Field : M0PLUS_NVIC_IPR7_IP_28 554 // Description : Priority of interrupt 28 555 #define M0PLUS_NVIC_IPR7_IP_28_RESET 0x0 556 #define M0PLUS_NVIC_IPR7_IP_28_BITS 0x000000c0 557 #define M0PLUS_NVIC_IPR7_IP_28_MSB 7 558 #define M0PLUS_NVIC_IPR7_IP_28_LSB 6 559 #define M0PLUS_NVIC_IPR7_IP_28_ACCESS "RW" 560 // ============================================================================= 561 // Register : M0PLUS_CPUID 562 // Description : Read the CPU ID Base Register to determine: the ID number of 563 // the processor core, the version number of the processor core, 564 // the implementation details of the processor core. 565 #define M0PLUS_CPUID_OFFSET 0x0000ed00 566 #define M0PLUS_CPUID_BITS 0xffffffff 567 #define M0PLUS_CPUID_RESET 0x410cc601 568 // ----------------------------------------------------------------------------- 569 // Field : M0PLUS_CPUID_IMPLEMENTER 570 // Description : Implementor code: 0x41 = ARM 571 #define M0PLUS_CPUID_IMPLEMENTER_RESET 0x41 572 #define M0PLUS_CPUID_IMPLEMENTER_BITS 0xff000000 573 #define M0PLUS_CPUID_IMPLEMENTER_MSB 31 574 #define M0PLUS_CPUID_IMPLEMENTER_LSB 24 575 #define M0PLUS_CPUID_IMPLEMENTER_ACCESS "RO" 576 // ----------------------------------------------------------------------------- 577 // Field : M0PLUS_CPUID_VARIANT 578 // Description : Major revision number n in the rnpm revision status: 579 // 0x0 = Revision 0. 580 #define M0PLUS_CPUID_VARIANT_RESET 0x0 581 #define M0PLUS_CPUID_VARIANT_BITS 0x00f00000 582 #define M0PLUS_CPUID_VARIANT_MSB 23 583 #define M0PLUS_CPUID_VARIANT_LSB 20 584 #define M0PLUS_CPUID_VARIANT_ACCESS "RO" 585 // ----------------------------------------------------------------------------- 586 // Field : M0PLUS_CPUID_ARCHITECTURE 587 // Description : Constant that defines the architecture of the processor: 588 // 0xC = ARMv6-M architecture. 589 #define M0PLUS_CPUID_ARCHITECTURE_RESET 0xc 590 #define M0PLUS_CPUID_ARCHITECTURE_BITS 0x000f0000 591 #define M0PLUS_CPUID_ARCHITECTURE_MSB 19 592 #define M0PLUS_CPUID_ARCHITECTURE_LSB 16 593 #define M0PLUS_CPUID_ARCHITECTURE_ACCESS "RO" 594 // ----------------------------------------------------------------------------- 595 // Field : M0PLUS_CPUID_PARTNO 596 // Description : Number of processor within family: 0xC60 = Cortex-M0+ 597 #define M0PLUS_CPUID_PARTNO_RESET 0xc60 598 #define M0PLUS_CPUID_PARTNO_BITS 0x0000fff0 599 #define M0PLUS_CPUID_PARTNO_MSB 15 600 #define M0PLUS_CPUID_PARTNO_LSB 4 601 #define M0PLUS_CPUID_PARTNO_ACCESS "RO" 602 // ----------------------------------------------------------------------------- 603 // Field : M0PLUS_CPUID_REVISION 604 // Description : Minor revision number m in the rnpm revision status: 605 // 0x1 = Patch 1. 606 #define M0PLUS_CPUID_REVISION_RESET 0x1 607 #define M0PLUS_CPUID_REVISION_BITS 0x0000000f 608 #define M0PLUS_CPUID_REVISION_MSB 3 609 #define M0PLUS_CPUID_REVISION_LSB 0 610 #define M0PLUS_CPUID_REVISION_ACCESS "RO" 611 // ============================================================================= 612 // Register : M0PLUS_ICSR 613 // Description : Use the Interrupt Control State Register to set a pending 614 // Non-Maskable Interrupt (NMI), set or clear a pending PendSV, 615 // set or clear a pending SysTick, check for pending exceptions, 616 // check the vector number of the highest priority pended 617 // exception, check the vector number of the active exception. 618 #define M0PLUS_ICSR_OFFSET 0x0000ed04 619 #define M0PLUS_ICSR_BITS 0x9edff1ff 620 #define M0PLUS_ICSR_RESET 0x00000000 621 // ----------------------------------------------------------------------------- 622 // Field : M0PLUS_ICSR_NMIPENDSET 623 // Description : Setting this bit will activate an NMI. Since NMI is the highest 624 // priority exception, it will activate as soon as it is 625 // registered. 626 // NMI set-pending bit. 627 // Write: 628 // 0 = No effect. 629 // 1 = Changes NMI exception state to pending. 630 // Read: 631 // 0 = NMI exception is not pending. 632 // 1 = NMI exception is pending. 633 // Because NMI is the highest-priority exception, normally the 634 // processor enters the NMI 635 // exception handler as soon as it detects a write of 1 to this 636 // bit. Entering the handler then clears 637 // this bit to 0. This means a read of this bit by the NMI 638 // exception handler returns 1 only if the 639 // NMI signal is reasserted while the processor is executing that 640 // handler. 641 #define M0PLUS_ICSR_NMIPENDSET_RESET 0x0 642 #define M0PLUS_ICSR_NMIPENDSET_BITS 0x80000000 643 #define M0PLUS_ICSR_NMIPENDSET_MSB 31 644 #define M0PLUS_ICSR_NMIPENDSET_LSB 31 645 #define M0PLUS_ICSR_NMIPENDSET_ACCESS "RW" 646 // ----------------------------------------------------------------------------- 647 // Field : M0PLUS_ICSR_PENDSVSET 648 // Description : PendSV set-pending bit. 649 // Write: 650 // 0 = No effect. 651 // 1 = Changes PendSV exception state to pending. 652 // Read: 653 // 0 = PendSV exception is not pending. 654 // 1 = PendSV exception is pending. 655 // Writing 1 to this bit is the only way to set the PendSV 656 // exception state to pending. 657 #define M0PLUS_ICSR_PENDSVSET_RESET 0x0 658 #define M0PLUS_ICSR_PENDSVSET_BITS 0x10000000 659 #define M0PLUS_ICSR_PENDSVSET_MSB 28 660 #define M0PLUS_ICSR_PENDSVSET_LSB 28 661 #define M0PLUS_ICSR_PENDSVSET_ACCESS "RW" 662 // ----------------------------------------------------------------------------- 663 // Field : M0PLUS_ICSR_PENDSVCLR 664 // Description : PendSV clear-pending bit. 665 // Write: 666 // 0 = No effect. 667 // 1 = Removes the pending state from the PendSV exception. 668 #define M0PLUS_ICSR_PENDSVCLR_RESET 0x0 669 #define M0PLUS_ICSR_PENDSVCLR_BITS 0x08000000 670 #define M0PLUS_ICSR_PENDSVCLR_MSB 27 671 #define M0PLUS_ICSR_PENDSVCLR_LSB 27 672 #define M0PLUS_ICSR_PENDSVCLR_ACCESS "RW" 673 // ----------------------------------------------------------------------------- 674 // Field : M0PLUS_ICSR_PENDSTSET 675 // Description : SysTick exception set-pending bit. 676 // Write: 677 // 0 = No effect. 678 // 1 = Changes SysTick exception state to pending. 679 // Read: 680 // 0 = SysTick exception is not pending. 681 // 1 = SysTick exception is pending. 682 #define M0PLUS_ICSR_PENDSTSET_RESET 0x0 683 #define M0PLUS_ICSR_PENDSTSET_BITS 0x04000000 684 #define M0PLUS_ICSR_PENDSTSET_MSB 26 685 #define M0PLUS_ICSR_PENDSTSET_LSB 26 686 #define M0PLUS_ICSR_PENDSTSET_ACCESS "RW" 687 // ----------------------------------------------------------------------------- 688 // Field : M0PLUS_ICSR_PENDSTCLR 689 // Description : SysTick exception clear-pending bit. 690 // Write: 691 // 0 = No effect. 692 // 1 = Removes the pending state from the SysTick exception. 693 // This bit is WO. On a register read its value is Unknown. 694 #define M0PLUS_ICSR_PENDSTCLR_RESET 0x0 695 #define M0PLUS_ICSR_PENDSTCLR_BITS 0x02000000 696 #define M0PLUS_ICSR_PENDSTCLR_MSB 25 697 #define M0PLUS_ICSR_PENDSTCLR_LSB 25 698 #define M0PLUS_ICSR_PENDSTCLR_ACCESS "RW" 699 // ----------------------------------------------------------------------------- 700 // Field : M0PLUS_ICSR_ISRPREEMPT 701 // Description : The system can only access this bit when the core is halted. It 702 // indicates that a pending interrupt is to be taken in the next 703 // running cycle. If C_MASKINTS is clear in the Debug Halting 704 // Control and Status Register, the interrupt is serviced. 705 #define M0PLUS_ICSR_ISRPREEMPT_RESET 0x0 706 #define M0PLUS_ICSR_ISRPREEMPT_BITS 0x00800000 707 #define M0PLUS_ICSR_ISRPREEMPT_MSB 23 708 #define M0PLUS_ICSR_ISRPREEMPT_LSB 23 709 #define M0PLUS_ICSR_ISRPREEMPT_ACCESS "RO" 710 // ----------------------------------------------------------------------------- 711 // Field : M0PLUS_ICSR_ISRPENDING 712 // Description : External interrupt pending flag 713 #define M0PLUS_ICSR_ISRPENDING_RESET 0x0 714 #define M0PLUS_ICSR_ISRPENDING_BITS 0x00400000 715 #define M0PLUS_ICSR_ISRPENDING_MSB 22 716 #define M0PLUS_ICSR_ISRPENDING_LSB 22 717 #define M0PLUS_ICSR_ISRPENDING_ACCESS "RO" 718 // ----------------------------------------------------------------------------- 719 // Field : M0PLUS_ICSR_VECTPENDING 720 // Description : Indicates the exception number for the highest priority pending 721 // exception: 0 = no pending exceptions. Non zero = The pending 722 // state includes the effect of memory-mapped enable and mask 723 // registers. It does not include the PRIMASK special-purpose 724 // register qualifier. 725 #define M0PLUS_ICSR_VECTPENDING_RESET 0x000 726 #define M0PLUS_ICSR_VECTPENDING_BITS 0x001ff000 727 #define M0PLUS_ICSR_VECTPENDING_MSB 20 728 #define M0PLUS_ICSR_VECTPENDING_LSB 12 729 #define M0PLUS_ICSR_VECTPENDING_ACCESS "RO" 730 // ----------------------------------------------------------------------------- 731 // Field : M0PLUS_ICSR_VECTACTIVE 732 // Description : Active exception number field. Reset clears the VECTACTIVE 733 // field. 734 #define M0PLUS_ICSR_VECTACTIVE_RESET 0x000 735 #define M0PLUS_ICSR_VECTACTIVE_BITS 0x000001ff 736 #define M0PLUS_ICSR_VECTACTIVE_MSB 8 737 #define M0PLUS_ICSR_VECTACTIVE_LSB 0 738 #define M0PLUS_ICSR_VECTACTIVE_ACCESS "RO" 739 // ============================================================================= 740 // Register : M0PLUS_VTOR 741 // Description : The VTOR holds the vector table offset address. 742 #define M0PLUS_VTOR_OFFSET 0x0000ed08 743 #define M0PLUS_VTOR_BITS 0xffffff00 744 #define M0PLUS_VTOR_RESET 0x00000000 745 // ----------------------------------------------------------------------------- 746 // Field : M0PLUS_VTOR_TBLOFF 747 // Description : Bits [31:8] of the indicate the vector table offset address. 748 #define M0PLUS_VTOR_TBLOFF_RESET 0x000000 749 #define M0PLUS_VTOR_TBLOFF_BITS 0xffffff00 750 #define M0PLUS_VTOR_TBLOFF_MSB 31 751 #define M0PLUS_VTOR_TBLOFF_LSB 8 752 #define M0PLUS_VTOR_TBLOFF_ACCESS "RW" 753 // ============================================================================= 754 // Register : M0PLUS_AIRCR 755 // Description : Use the Application Interrupt and Reset Control Register to: 756 // determine data endianness, clear all active state information 757 // from debug halt mode, request a system reset. 758 #define M0PLUS_AIRCR_OFFSET 0x0000ed0c 759 #define M0PLUS_AIRCR_BITS 0xffff8006 760 #define M0PLUS_AIRCR_RESET 0x00000000 761 // ----------------------------------------------------------------------------- 762 // Field : M0PLUS_AIRCR_VECTKEY 763 // Description : Register key: 764 // Reads as Unknown 765 // On writes, write 0x05FA to VECTKEY, otherwise the write is 766 // ignored. 767 #define M0PLUS_AIRCR_VECTKEY_RESET 0x0000 768 #define M0PLUS_AIRCR_VECTKEY_BITS 0xffff0000 769 #define M0PLUS_AIRCR_VECTKEY_MSB 31 770 #define M0PLUS_AIRCR_VECTKEY_LSB 16 771 #define M0PLUS_AIRCR_VECTKEY_ACCESS "RW" 772 // ----------------------------------------------------------------------------- 773 // Field : M0PLUS_AIRCR_ENDIANESS 774 // Description : Data endianness implemented: 775 // 0 = Little-endian. 776 #define M0PLUS_AIRCR_ENDIANESS_RESET 0x0 777 #define M0PLUS_AIRCR_ENDIANESS_BITS 0x00008000 778 #define M0PLUS_AIRCR_ENDIANESS_MSB 15 779 #define M0PLUS_AIRCR_ENDIANESS_LSB 15 780 #define M0PLUS_AIRCR_ENDIANESS_ACCESS "RO" 781 // ----------------------------------------------------------------------------- 782 // Field : M0PLUS_AIRCR_SYSRESETREQ 783 // Description : Writing 1 to this bit causes the SYSRESETREQ signal to the 784 // outer system to be asserted to request a reset. The intention 785 // is to force a large system reset of all major components except 786 // for debug. The C_HALT bit in the DHCSR is cleared as a result 787 // of the system reset requested. The debugger does not lose 788 // contact with the device. 789 #define M0PLUS_AIRCR_SYSRESETREQ_RESET 0x0 790 #define M0PLUS_AIRCR_SYSRESETREQ_BITS 0x00000004 791 #define M0PLUS_AIRCR_SYSRESETREQ_MSB 2 792 #define M0PLUS_AIRCR_SYSRESETREQ_LSB 2 793 #define M0PLUS_AIRCR_SYSRESETREQ_ACCESS "RW" 794 // ----------------------------------------------------------------------------- 795 // Field : M0PLUS_AIRCR_VECTCLRACTIVE 796 // Description : Clears all active state information for fixed and configurable 797 // exceptions. This bit: is self-clearing, can only be set by the 798 // DAP when the core is halted. When set: clears all active 799 // exception status of the processor, forces a return to Thread 800 // mode, forces an IPSR of 0. A debugger must re-initialize the 801 // stack. 802 #define M0PLUS_AIRCR_VECTCLRACTIVE_RESET 0x0 803 #define M0PLUS_AIRCR_VECTCLRACTIVE_BITS 0x00000002 804 #define M0PLUS_AIRCR_VECTCLRACTIVE_MSB 1 805 #define M0PLUS_AIRCR_VECTCLRACTIVE_LSB 1 806 #define M0PLUS_AIRCR_VECTCLRACTIVE_ACCESS "RW" 807 // ============================================================================= 808 // Register : M0PLUS_SCR 809 // Description : System Control Register. Use the System Control Register for 810 // power-management functions: signal to the system when the 811 // processor can enter a low power state, control how the 812 // processor enters and exits low power states. 813 #define M0PLUS_SCR_OFFSET 0x0000ed10 814 #define M0PLUS_SCR_BITS 0x00000016 815 #define M0PLUS_SCR_RESET 0x00000000 816 // ----------------------------------------------------------------------------- 817 // Field : M0PLUS_SCR_SEVONPEND 818 // Description : Send Event on Pending bit: 819 // 0 = Only enabled interrupts or events can wakeup the processor, 820 // disabled interrupts are excluded. 821 // 1 = Enabled events and all interrupts, including disabled 822 // interrupts, can wakeup the processor. 823 // When an event or interrupt becomes pending, the event signal 824 // wakes up the processor from WFE. If the 825 // processor is not waiting for an event, the event is registered 826 // and affects the next WFE. 827 // The processor also wakes up on execution of an SEV instruction 828 // or an external event. 829 #define M0PLUS_SCR_SEVONPEND_RESET 0x0 830 #define M0PLUS_SCR_SEVONPEND_BITS 0x00000010 831 #define M0PLUS_SCR_SEVONPEND_MSB 4 832 #define M0PLUS_SCR_SEVONPEND_LSB 4 833 #define M0PLUS_SCR_SEVONPEND_ACCESS "RW" 834 // ----------------------------------------------------------------------------- 835 // Field : M0PLUS_SCR_SLEEPDEEP 836 // Description : Controls whether the processor uses sleep or deep sleep as its 837 // low power mode: 838 // 0 = Sleep. 839 // 1 = Deep sleep. 840 #define M0PLUS_SCR_SLEEPDEEP_RESET 0x0 841 #define M0PLUS_SCR_SLEEPDEEP_BITS 0x00000004 842 #define M0PLUS_SCR_SLEEPDEEP_MSB 2 843 #define M0PLUS_SCR_SLEEPDEEP_LSB 2 844 #define M0PLUS_SCR_SLEEPDEEP_ACCESS "RW" 845 // ----------------------------------------------------------------------------- 846 // Field : M0PLUS_SCR_SLEEPONEXIT 847 // Description : Indicates sleep-on-exit when returning from Handler mode to 848 // Thread mode: 849 // 0 = Do not sleep when returning to Thread mode. 850 // 1 = Enter sleep, or deep sleep, on return from an ISR to Thread 851 // mode. 852 // Setting this bit to 1 enables an interrupt driven application 853 // to avoid returning to an empty main application. 854 #define M0PLUS_SCR_SLEEPONEXIT_RESET 0x0 855 #define M0PLUS_SCR_SLEEPONEXIT_BITS 0x00000002 856 #define M0PLUS_SCR_SLEEPONEXIT_MSB 1 857 #define M0PLUS_SCR_SLEEPONEXIT_LSB 1 858 #define M0PLUS_SCR_SLEEPONEXIT_ACCESS "RW" 859 // ============================================================================= 860 // Register : M0PLUS_CCR 861 // Description : The Configuration and Control Register permanently enables 862 // stack alignment and causes unaligned accesses to result in a 863 // Hard Fault. 864 #define M0PLUS_CCR_OFFSET 0x0000ed14 865 #define M0PLUS_CCR_BITS 0x00000208 866 #define M0PLUS_CCR_RESET 0x00000000 867 // ----------------------------------------------------------------------------- 868 // Field : M0PLUS_CCR_STKALIGN 869 // Description : Always reads as one, indicates 8-byte stack alignment on 870 // exception entry. On exception entry, the processor uses bit[9] 871 // of the stacked PSR to indicate the stack alignment. On return 872 // from the exception it uses this stacked bit to restore the 873 // correct stack alignment. 874 #define M0PLUS_CCR_STKALIGN_RESET 0x0 875 #define M0PLUS_CCR_STKALIGN_BITS 0x00000200 876 #define M0PLUS_CCR_STKALIGN_MSB 9 877 #define M0PLUS_CCR_STKALIGN_LSB 9 878 #define M0PLUS_CCR_STKALIGN_ACCESS "RO" 879 // ----------------------------------------------------------------------------- 880 // Field : M0PLUS_CCR_UNALIGN_TRP 881 // Description : Always reads as one, indicates that all unaligned accesses 882 // generate a HardFault. 883 #define M0PLUS_CCR_UNALIGN_TRP_RESET 0x0 884 #define M0PLUS_CCR_UNALIGN_TRP_BITS 0x00000008 885 #define M0PLUS_CCR_UNALIGN_TRP_MSB 3 886 #define M0PLUS_CCR_UNALIGN_TRP_LSB 3 887 #define M0PLUS_CCR_UNALIGN_TRP_ACCESS "RO" 888 // ============================================================================= 889 // Register : M0PLUS_SHPR2 890 // Description : System handlers are a special class of exception handler that 891 // can have their priority set to any of the priority levels. Use 892 // the System Handler Priority Register 2 to set the priority of 893 // SVCall. 894 #define M0PLUS_SHPR2_OFFSET 0x0000ed1c 895 #define M0PLUS_SHPR2_BITS 0xc0000000 896 #define M0PLUS_SHPR2_RESET 0x00000000 897 // ----------------------------------------------------------------------------- 898 // Field : M0PLUS_SHPR2_PRI_11 899 // Description : Priority of system handler 11, SVCall 900 #define M0PLUS_SHPR2_PRI_11_RESET 0x0 901 #define M0PLUS_SHPR2_PRI_11_BITS 0xc0000000 902 #define M0PLUS_SHPR2_PRI_11_MSB 31 903 #define M0PLUS_SHPR2_PRI_11_LSB 30 904 #define M0PLUS_SHPR2_PRI_11_ACCESS "RW" 905 // ============================================================================= 906 // Register : M0PLUS_SHPR3 907 // Description : System handlers are a special class of exception handler that 908 // can have their priority set to any of the priority levels. Use 909 // the System Handler Priority Register 3 to set the priority of 910 // PendSV and SysTick. 911 #define M0PLUS_SHPR3_OFFSET 0x0000ed20 912 #define M0PLUS_SHPR3_BITS 0xc0c00000 913 #define M0PLUS_SHPR3_RESET 0x00000000 914 // ----------------------------------------------------------------------------- 915 // Field : M0PLUS_SHPR3_PRI_15 916 // Description : Priority of system handler 15, SysTick 917 #define M0PLUS_SHPR3_PRI_15_RESET 0x0 918 #define M0PLUS_SHPR3_PRI_15_BITS 0xc0000000 919 #define M0PLUS_SHPR3_PRI_15_MSB 31 920 #define M0PLUS_SHPR3_PRI_15_LSB 30 921 #define M0PLUS_SHPR3_PRI_15_ACCESS "RW" 922 // ----------------------------------------------------------------------------- 923 // Field : M0PLUS_SHPR3_PRI_14 924 // Description : Priority of system handler 14, PendSV 925 #define M0PLUS_SHPR3_PRI_14_RESET 0x0 926 #define M0PLUS_SHPR3_PRI_14_BITS 0x00c00000 927 #define M0PLUS_SHPR3_PRI_14_MSB 23 928 #define M0PLUS_SHPR3_PRI_14_LSB 22 929 #define M0PLUS_SHPR3_PRI_14_ACCESS "RW" 930 // ============================================================================= 931 // Register : M0PLUS_SHCSR 932 // Description : Use the System Handler Control and State Register to determine 933 // or clear the pending status of SVCall. 934 #define M0PLUS_SHCSR_OFFSET 0x0000ed24 935 #define M0PLUS_SHCSR_BITS 0x00008000 936 #define M0PLUS_SHCSR_RESET 0x00000000 937 // ----------------------------------------------------------------------------- 938 // Field : M0PLUS_SHCSR_SVCALLPENDED 939 // Description : Reads as 1 if SVCall is Pending. Write 1 to set pending 940 // SVCall, write 0 to clear pending SVCall. 941 #define M0PLUS_SHCSR_SVCALLPENDED_RESET 0x0 942 #define M0PLUS_SHCSR_SVCALLPENDED_BITS 0x00008000 943 #define M0PLUS_SHCSR_SVCALLPENDED_MSB 15 944 #define M0PLUS_SHCSR_SVCALLPENDED_LSB 15 945 #define M0PLUS_SHCSR_SVCALLPENDED_ACCESS "RW" 946 // ============================================================================= 947 // Register : M0PLUS_MPU_TYPE 948 // Description : Read the MPU Type Register to determine if the processor 949 // implements an MPU, and how many regions the MPU supports. 950 #define M0PLUS_MPU_TYPE_OFFSET 0x0000ed90 951 #define M0PLUS_MPU_TYPE_BITS 0x00ffff01 952 #define M0PLUS_MPU_TYPE_RESET 0x00000800 953 // ----------------------------------------------------------------------------- 954 // Field : M0PLUS_MPU_TYPE_IREGION 955 // Description : Instruction region. Reads as zero as ARMv6-M only supports a 956 // unified MPU. 957 #define M0PLUS_MPU_TYPE_IREGION_RESET 0x00 958 #define M0PLUS_MPU_TYPE_IREGION_BITS 0x00ff0000 959 #define M0PLUS_MPU_TYPE_IREGION_MSB 23 960 #define M0PLUS_MPU_TYPE_IREGION_LSB 16 961 #define M0PLUS_MPU_TYPE_IREGION_ACCESS "RO" 962 // ----------------------------------------------------------------------------- 963 // Field : M0PLUS_MPU_TYPE_DREGION 964 // Description : Number of regions supported by the MPU. 965 #define M0PLUS_MPU_TYPE_DREGION_RESET 0x08 966 #define M0PLUS_MPU_TYPE_DREGION_BITS 0x0000ff00 967 #define M0PLUS_MPU_TYPE_DREGION_MSB 15 968 #define M0PLUS_MPU_TYPE_DREGION_LSB 8 969 #define M0PLUS_MPU_TYPE_DREGION_ACCESS "RO" 970 // ----------------------------------------------------------------------------- 971 // Field : M0PLUS_MPU_TYPE_SEPARATE 972 // Description : Indicates support for separate instruction and data address 973 // maps. Reads as 0 as ARMv6-M only supports a unified MPU. 974 #define M0PLUS_MPU_TYPE_SEPARATE_RESET 0x0 975 #define M0PLUS_MPU_TYPE_SEPARATE_BITS 0x00000001 976 #define M0PLUS_MPU_TYPE_SEPARATE_MSB 0 977 #define M0PLUS_MPU_TYPE_SEPARATE_LSB 0 978 #define M0PLUS_MPU_TYPE_SEPARATE_ACCESS "RO" 979 // ============================================================================= 980 // Register : M0PLUS_MPU_CTRL 981 // Description : Use the MPU Control Register to enable and disable the MPU, and 982 // to control whether the default memory map is enabled as a 983 // background region for privileged accesses, and whether the MPU 984 // is enabled for HardFaults and NMIs. 985 #define M0PLUS_MPU_CTRL_OFFSET 0x0000ed94 986 #define M0PLUS_MPU_CTRL_BITS 0x00000007 987 #define M0PLUS_MPU_CTRL_RESET 0x00000000 988 // ----------------------------------------------------------------------------- 989 // Field : M0PLUS_MPU_CTRL_PRIVDEFENA 990 // Description : Controls whether the default memory map is enabled as a 991 // background region for privileged accesses. This bit is ignored 992 // when ENABLE is clear. 993 // 0 = If the MPU is enabled, disables use of the default memory 994 // map. Any memory access to a location not 995 // covered by any enabled region causes a fault. 996 // 1 = If the MPU is enabled, enables use of the default memory 997 // map as a background region for privileged software accesses. 998 // When enabled, the background region acts as if it is region 999 // number -1. Any region that is defined and enabled has priority 1000 // over this default map. 1001 #define M0PLUS_MPU_CTRL_PRIVDEFENA_RESET 0x0 1002 #define M0PLUS_MPU_CTRL_PRIVDEFENA_BITS 0x00000004 1003 #define M0PLUS_MPU_CTRL_PRIVDEFENA_MSB 2 1004 #define M0PLUS_MPU_CTRL_PRIVDEFENA_LSB 2 1005 #define M0PLUS_MPU_CTRL_PRIVDEFENA_ACCESS "RW" 1006 // ----------------------------------------------------------------------------- 1007 // Field : M0PLUS_MPU_CTRL_HFNMIENA 1008 // Description : Controls the use of the MPU for HardFaults and NMIs. Setting 1009 // this bit when ENABLE is clear results in UNPREDICTABLE 1010 // behaviour. 1011 // When the MPU is enabled: 1012 // 0 = MPU is disabled during HardFault and NMI handlers, 1013 // regardless of the value of the ENABLE bit. 1014 // 1 = the MPU is enabled during HardFault and NMI handlers. 1015 #define M0PLUS_MPU_CTRL_HFNMIENA_RESET 0x0 1016 #define M0PLUS_MPU_CTRL_HFNMIENA_BITS 0x00000002 1017 #define M0PLUS_MPU_CTRL_HFNMIENA_MSB 1 1018 #define M0PLUS_MPU_CTRL_HFNMIENA_LSB 1 1019 #define M0PLUS_MPU_CTRL_HFNMIENA_ACCESS "RW" 1020 // ----------------------------------------------------------------------------- 1021 // Field : M0PLUS_MPU_CTRL_ENABLE 1022 // Description : Enables the MPU. If the MPU is disabled, privileged and 1023 // unprivileged accesses use the default memory map. 1024 // 0 = MPU disabled. 1025 // 1 = MPU enabled. 1026 #define M0PLUS_MPU_CTRL_ENABLE_RESET 0x0 1027 #define M0PLUS_MPU_CTRL_ENABLE_BITS 0x00000001 1028 #define M0PLUS_MPU_CTRL_ENABLE_MSB 0 1029 #define M0PLUS_MPU_CTRL_ENABLE_LSB 0 1030 #define M0PLUS_MPU_CTRL_ENABLE_ACCESS "RW" 1031 // ============================================================================= 1032 // Register : M0PLUS_MPU_RNR 1033 // Description : Use the MPU Region Number Register to select the region 1034 // currently accessed by MPU_RBAR and MPU_RASR. 1035 #define M0PLUS_MPU_RNR_OFFSET 0x0000ed98 1036 #define M0PLUS_MPU_RNR_BITS 0x0000000f 1037 #define M0PLUS_MPU_RNR_RESET 0x00000000 1038 // ----------------------------------------------------------------------------- 1039 // Field : M0PLUS_MPU_RNR_REGION 1040 // Description : Indicates the MPU region referenced by the MPU_RBAR and 1041 // MPU_RASR registers. 1042 // The MPU supports 8 memory regions, so the permitted values of 1043 // this field are 0-7. 1044 #define M0PLUS_MPU_RNR_REGION_RESET 0x0 1045 #define M0PLUS_MPU_RNR_REGION_BITS 0x0000000f 1046 #define M0PLUS_MPU_RNR_REGION_MSB 3 1047 #define M0PLUS_MPU_RNR_REGION_LSB 0 1048 #define M0PLUS_MPU_RNR_REGION_ACCESS "RW" 1049 // ============================================================================= 1050 // Register : M0PLUS_MPU_RBAR 1051 // Description : Read the MPU Region Base Address Register to determine the base 1052 // address of the region identified by MPU_RNR. Write to update 1053 // the base address of said region or that of a specified region, 1054 // with whose number MPU_RNR will also be updated. 1055 #define M0PLUS_MPU_RBAR_OFFSET 0x0000ed9c 1056 #define M0PLUS_MPU_RBAR_BITS 0xffffff1f 1057 #define M0PLUS_MPU_RBAR_RESET 0x00000000 1058 // ----------------------------------------------------------------------------- 1059 // Field : M0PLUS_MPU_RBAR_ADDR 1060 // Description : Base address of the region. 1061 #define M0PLUS_MPU_RBAR_ADDR_RESET 0x000000 1062 #define M0PLUS_MPU_RBAR_ADDR_BITS 0xffffff00 1063 #define M0PLUS_MPU_RBAR_ADDR_MSB 31 1064 #define M0PLUS_MPU_RBAR_ADDR_LSB 8 1065 #define M0PLUS_MPU_RBAR_ADDR_ACCESS "RW" 1066 // ----------------------------------------------------------------------------- 1067 // Field : M0PLUS_MPU_RBAR_VALID 1068 // Description : On writes, indicates whether the write must update the base 1069 // address of the region identified by the REGION field, updating 1070 // the MPU_RNR to indicate this new region. 1071 // Write: 1072 // 0 = MPU_RNR not changed, and the processor: 1073 // Updates the base address for the region specified in the 1074 // MPU_RNR. 1075 // Ignores the value of the REGION field. 1076 // 1 = The processor: 1077 // Updates the value of the MPU_RNR to the value of the REGION 1078 // field. 1079 // Updates the base address for the region specified in the REGION 1080 // field. 1081 // Always reads as zero. 1082 #define M0PLUS_MPU_RBAR_VALID_RESET 0x0 1083 #define M0PLUS_MPU_RBAR_VALID_BITS 0x00000010 1084 #define M0PLUS_MPU_RBAR_VALID_MSB 4 1085 #define M0PLUS_MPU_RBAR_VALID_LSB 4 1086 #define M0PLUS_MPU_RBAR_VALID_ACCESS "RW" 1087 // ----------------------------------------------------------------------------- 1088 // Field : M0PLUS_MPU_RBAR_REGION 1089 // Description : On writes, specifies the number of the region whose base 1090 // address to update provided VALID is set written as 1. On reads, 1091 // returns bits [3:0] of MPU_RNR. 1092 #define M0PLUS_MPU_RBAR_REGION_RESET 0x0 1093 #define M0PLUS_MPU_RBAR_REGION_BITS 0x0000000f 1094 #define M0PLUS_MPU_RBAR_REGION_MSB 3 1095 #define M0PLUS_MPU_RBAR_REGION_LSB 0 1096 #define M0PLUS_MPU_RBAR_REGION_ACCESS "RW" 1097 // ============================================================================= 1098 // Register : M0PLUS_MPU_RASR 1099 // Description : Use the MPU Region Attribute and Size Register to define the 1100 // size, access behaviour and memory type of the region identified 1101 // by MPU_RNR, and enable that region. 1102 #define M0PLUS_MPU_RASR_OFFSET 0x0000eda0 1103 #define M0PLUS_MPU_RASR_BITS 0xffffff3f 1104 #define M0PLUS_MPU_RASR_RESET 0x00000000 1105 // ----------------------------------------------------------------------------- 1106 // Field : M0PLUS_MPU_RASR_ATTRS 1107 // Description : The MPU Region Attribute field. Use to define the region 1108 // attribute control. 1109 // 28 = XN: Instruction access disable bit: 1110 // 0 = Instruction fetches enabled. 1111 // 1 = Instruction fetches disabled. 1112 // 26:24 = AP: Access permission field 1113 // 18 = S: Shareable bit 1114 // 17 = C: Cacheable bit 1115 // 16 = B: Bufferable bit 1116 #define M0PLUS_MPU_RASR_ATTRS_RESET 0x0000 1117 #define M0PLUS_MPU_RASR_ATTRS_BITS 0xffff0000 1118 #define M0PLUS_MPU_RASR_ATTRS_MSB 31 1119 #define M0PLUS_MPU_RASR_ATTRS_LSB 16 1120 #define M0PLUS_MPU_RASR_ATTRS_ACCESS "RW" 1121 // ----------------------------------------------------------------------------- 1122 // Field : M0PLUS_MPU_RASR_SRD 1123 // Description : Subregion Disable. For regions of 256 bytes or larger, each bit 1124 // of this field controls whether one of the eight equal 1125 // subregions is enabled. 1126 #define M0PLUS_MPU_RASR_SRD_RESET 0x00 1127 #define M0PLUS_MPU_RASR_SRD_BITS 0x0000ff00 1128 #define M0PLUS_MPU_RASR_SRD_MSB 15 1129 #define M0PLUS_MPU_RASR_SRD_LSB 8 1130 #define M0PLUS_MPU_RASR_SRD_ACCESS "RW" 1131 // ----------------------------------------------------------------------------- 1132 // Field : M0PLUS_MPU_RASR_SIZE 1133 // Description : Indicates the region size. Region size in bytes = 2^(SIZE+1). 1134 // The minimum permitted value is 7 (b00111) = 256Bytes 1135 #define M0PLUS_MPU_RASR_SIZE_RESET 0x00 1136 #define M0PLUS_MPU_RASR_SIZE_BITS 0x0000003e 1137 #define M0PLUS_MPU_RASR_SIZE_MSB 5 1138 #define M0PLUS_MPU_RASR_SIZE_LSB 1 1139 #define M0PLUS_MPU_RASR_SIZE_ACCESS "RW" 1140 // ----------------------------------------------------------------------------- 1141 // Field : M0PLUS_MPU_RASR_ENABLE 1142 // Description : Enables the region. 1143 #define M0PLUS_MPU_RASR_ENABLE_RESET 0x0 1144 #define M0PLUS_MPU_RASR_ENABLE_BITS 0x00000001 1145 #define M0PLUS_MPU_RASR_ENABLE_MSB 0 1146 #define M0PLUS_MPU_RASR_ENABLE_LSB 0 1147 #define M0PLUS_MPU_RASR_ENABLE_ACCESS "RW" 1148 // ============================================================================= 1149 #endif // HARDWARE_REGS_M0PLUS_DEFINED 1150