1 /** 2 * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 // ============================================================================= 7 // Register block : PLL 8 // Version : 1 9 // Bus type : apb 10 // Description : None 11 // ============================================================================= 12 #ifndef HARDWARE_REGS_PLL_DEFINED 13 #define HARDWARE_REGS_PLL_DEFINED 14 // ============================================================================= 15 // Register : PLL_CS 16 // Description : Control and Status 17 // GENERAL CONSTRAINTS: 18 // Reference clock frequency min=5MHz, max=800MHz 19 // Feedback divider min=16, max=320 20 // VCO frequency min=400MHz, max=1600MHz 21 #define PLL_CS_OFFSET 0x00000000 22 #define PLL_CS_BITS 0x8000013f 23 #define PLL_CS_RESET 0x00000001 24 // ----------------------------------------------------------------------------- 25 // Field : PLL_CS_LOCK 26 // Description : PLL is locked 27 #define PLL_CS_LOCK_RESET 0x0 28 #define PLL_CS_LOCK_BITS 0x80000000 29 #define PLL_CS_LOCK_MSB 31 30 #define PLL_CS_LOCK_LSB 31 31 #define PLL_CS_LOCK_ACCESS "RO" 32 // ----------------------------------------------------------------------------- 33 // Field : PLL_CS_BYPASS 34 // Description : Passes the reference clock to the output instead of the divided 35 // VCO. The VCO continues to run so the user can switch between 36 // the reference clock and the divided VCO but the output will 37 // glitch when doing so. 38 #define PLL_CS_BYPASS_RESET 0x0 39 #define PLL_CS_BYPASS_BITS 0x00000100 40 #define PLL_CS_BYPASS_MSB 8 41 #define PLL_CS_BYPASS_LSB 8 42 #define PLL_CS_BYPASS_ACCESS "RW" 43 // ----------------------------------------------------------------------------- 44 // Field : PLL_CS_REFDIV 45 // Description : Divides the PLL input reference clock. 46 // Behaviour is undefined for div=0. 47 // PLL output will be unpredictable during refdiv changes, wait 48 // for lock=1 before using it. 49 #define PLL_CS_REFDIV_RESET 0x01 50 #define PLL_CS_REFDIV_BITS 0x0000003f 51 #define PLL_CS_REFDIV_MSB 5 52 #define PLL_CS_REFDIV_LSB 0 53 #define PLL_CS_REFDIV_ACCESS "RW" 54 // ============================================================================= 55 // Register : PLL_PWR 56 // Description : Controls the PLL power modes. 57 #define PLL_PWR_OFFSET 0x00000004 58 #define PLL_PWR_BITS 0x0000002d 59 #define PLL_PWR_RESET 0x0000002d 60 // ----------------------------------------------------------------------------- 61 // Field : PLL_PWR_VCOPD 62 // Description : PLL VCO powerdown 63 // To save power set high when PLL output not required or 64 // bypass=1. 65 #define PLL_PWR_VCOPD_RESET 0x1 66 #define PLL_PWR_VCOPD_BITS 0x00000020 67 #define PLL_PWR_VCOPD_MSB 5 68 #define PLL_PWR_VCOPD_LSB 5 69 #define PLL_PWR_VCOPD_ACCESS "RW" 70 // ----------------------------------------------------------------------------- 71 // Field : PLL_PWR_POSTDIVPD 72 // Description : PLL post divider powerdown 73 // To save power set high when PLL output not required or 74 // bypass=1. 75 #define PLL_PWR_POSTDIVPD_RESET 0x1 76 #define PLL_PWR_POSTDIVPD_BITS 0x00000008 77 #define PLL_PWR_POSTDIVPD_MSB 3 78 #define PLL_PWR_POSTDIVPD_LSB 3 79 #define PLL_PWR_POSTDIVPD_ACCESS "RW" 80 // ----------------------------------------------------------------------------- 81 // Field : PLL_PWR_DSMPD 82 // Description : PLL DSM powerdown 83 // Nothing is achieved by setting this low. 84 #define PLL_PWR_DSMPD_RESET 0x1 85 #define PLL_PWR_DSMPD_BITS 0x00000004 86 #define PLL_PWR_DSMPD_MSB 2 87 #define PLL_PWR_DSMPD_LSB 2 88 #define PLL_PWR_DSMPD_ACCESS "RW" 89 // ----------------------------------------------------------------------------- 90 // Field : PLL_PWR_PD 91 // Description : PLL powerdown 92 // To save power set high when PLL output not required. 93 #define PLL_PWR_PD_RESET 0x1 94 #define PLL_PWR_PD_BITS 0x00000001 95 #define PLL_PWR_PD_MSB 0 96 #define PLL_PWR_PD_LSB 0 97 #define PLL_PWR_PD_ACCESS "RW" 98 // ============================================================================= 99 // Register : PLL_FBDIV_INT 100 // Description : Feedback divisor 101 // (note: this PLL does not support fractional division) 102 // see ctrl reg description for constraints 103 #define PLL_FBDIV_INT_OFFSET 0x00000008 104 #define PLL_FBDIV_INT_BITS 0x00000fff 105 #define PLL_FBDIV_INT_RESET 0x00000000 106 #define PLL_FBDIV_INT_MSB 11 107 #define PLL_FBDIV_INT_LSB 0 108 #define PLL_FBDIV_INT_ACCESS "RW" 109 // ============================================================================= 110 // Register : PLL_PRIM 111 // Description : Controls the PLL post dividers for the primary output 112 // (note: this PLL does not have a secondary output) 113 // the primary output is driven from VCO divided by 114 // postdiv1*postdiv2 115 #define PLL_PRIM_OFFSET 0x0000000c 116 #define PLL_PRIM_BITS 0x00077000 117 #define PLL_PRIM_RESET 0x00077000 118 // ----------------------------------------------------------------------------- 119 // Field : PLL_PRIM_POSTDIV1 120 // Description : divide by 1-7 121 #define PLL_PRIM_POSTDIV1_RESET 0x7 122 #define PLL_PRIM_POSTDIV1_BITS 0x00070000 123 #define PLL_PRIM_POSTDIV1_MSB 18 124 #define PLL_PRIM_POSTDIV1_LSB 16 125 #define PLL_PRIM_POSTDIV1_ACCESS "RW" 126 // ----------------------------------------------------------------------------- 127 // Field : PLL_PRIM_POSTDIV2 128 // Description : divide by 1-7 129 #define PLL_PRIM_POSTDIV2_RESET 0x7 130 #define PLL_PRIM_POSTDIV2_BITS 0x00007000 131 #define PLL_PRIM_POSTDIV2_MSB 14 132 #define PLL_PRIM_POSTDIV2_LSB 12 133 #define PLL_PRIM_POSTDIV2_ACCESS "RW" 134 // ============================================================================= 135 #endif // HARDWARE_REGS_PLL_DEFINED 136