1 /**
2  * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 // =============================================================================
7 // Register block : PSM
8 // Version        : 1
9 // Bus type       : apb
10 // Description    : None
11 // =============================================================================
12 #ifndef HARDWARE_REGS_PSM_DEFINED
13 #define HARDWARE_REGS_PSM_DEFINED
14 // =============================================================================
15 // Register    : PSM_FRCE_ON
16 // Description : Force block out of reset (i.e. power it on)
17 #define PSM_FRCE_ON_OFFSET 0x00000000
18 #define PSM_FRCE_ON_BITS   0x0001ffff
19 #define PSM_FRCE_ON_RESET  0x00000000
20 // -----------------------------------------------------------------------------
21 // Field       : PSM_FRCE_ON_PROC1
22 // Description : None
23 #define PSM_FRCE_ON_PROC1_RESET  0x0
24 #define PSM_FRCE_ON_PROC1_BITS   0x00010000
25 #define PSM_FRCE_ON_PROC1_MSB    16
26 #define PSM_FRCE_ON_PROC1_LSB    16
27 #define PSM_FRCE_ON_PROC1_ACCESS "RW"
28 // -----------------------------------------------------------------------------
29 // Field       : PSM_FRCE_ON_PROC0
30 // Description : None
31 #define PSM_FRCE_ON_PROC0_RESET  0x0
32 #define PSM_FRCE_ON_PROC0_BITS   0x00008000
33 #define PSM_FRCE_ON_PROC0_MSB    15
34 #define PSM_FRCE_ON_PROC0_LSB    15
35 #define PSM_FRCE_ON_PROC0_ACCESS "RW"
36 // -----------------------------------------------------------------------------
37 // Field       : PSM_FRCE_ON_SIO
38 // Description : None
39 #define PSM_FRCE_ON_SIO_RESET  0x0
40 #define PSM_FRCE_ON_SIO_BITS   0x00004000
41 #define PSM_FRCE_ON_SIO_MSB    14
42 #define PSM_FRCE_ON_SIO_LSB    14
43 #define PSM_FRCE_ON_SIO_ACCESS "RW"
44 // -----------------------------------------------------------------------------
45 // Field       : PSM_FRCE_ON_VREG_AND_CHIP_RESET
46 // Description : None
47 #define PSM_FRCE_ON_VREG_AND_CHIP_RESET_RESET  0x0
48 #define PSM_FRCE_ON_VREG_AND_CHIP_RESET_BITS   0x00002000
49 #define PSM_FRCE_ON_VREG_AND_CHIP_RESET_MSB    13
50 #define PSM_FRCE_ON_VREG_AND_CHIP_RESET_LSB    13
51 #define PSM_FRCE_ON_VREG_AND_CHIP_RESET_ACCESS "RW"
52 // -----------------------------------------------------------------------------
53 // Field       : PSM_FRCE_ON_XIP
54 // Description : None
55 #define PSM_FRCE_ON_XIP_RESET  0x0
56 #define PSM_FRCE_ON_XIP_BITS   0x00001000
57 #define PSM_FRCE_ON_XIP_MSB    12
58 #define PSM_FRCE_ON_XIP_LSB    12
59 #define PSM_FRCE_ON_XIP_ACCESS "RW"
60 // -----------------------------------------------------------------------------
61 // Field       : PSM_FRCE_ON_SRAM5
62 // Description : None
63 #define PSM_FRCE_ON_SRAM5_RESET  0x0
64 #define PSM_FRCE_ON_SRAM5_BITS   0x00000800
65 #define PSM_FRCE_ON_SRAM5_MSB    11
66 #define PSM_FRCE_ON_SRAM5_LSB    11
67 #define PSM_FRCE_ON_SRAM5_ACCESS "RW"
68 // -----------------------------------------------------------------------------
69 // Field       : PSM_FRCE_ON_SRAM4
70 // Description : None
71 #define PSM_FRCE_ON_SRAM4_RESET  0x0
72 #define PSM_FRCE_ON_SRAM4_BITS   0x00000400
73 #define PSM_FRCE_ON_SRAM4_MSB    10
74 #define PSM_FRCE_ON_SRAM4_LSB    10
75 #define PSM_FRCE_ON_SRAM4_ACCESS "RW"
76 // -----------------------------------------------------------------------------
77 // Field       : PSM_FRCE_ON_SRAM3
78 // Description : None
79 #define PSM_FRCE_ON_SRAM3_RESET  0x0
80 #define PSM_FRCE_ON_SRAM3_BITS   0x00000200
81 #define PSM_FRCE_ON_SRAM3_MSB    9
82 #define PSM_FRCE_ON_SRAM3_LSB    9
83 #define PSM_FRCE_ON_SRAM3_ACCESS "RW"
84 // -----------------------------------------------------------------------------
85 // Field       : PSM_FRCE_ON_SRAM2
86 // Description : None
87 #define PSM_FRCE_ON_SRAM2_RESET  0x0
88 #define PSM_FRCE_ON_SRAM2_BITS   0x00000100
89 #define PSM_FRCE_ON_SRAM2_MSB    8
90 #define PSM_FRCE_ON_SRAM2_LSB    8
91 #define PSM_FRCE_ON_SRAM2_ACCESS "RW"
92 // -----------------------------------------------------------------------------
93 // Field       : PSM_FRCE_ON_SRAM1
94 // Description : None
95 #define PSM_FRCE_ON_SRAM1_RESET  0x0
96 #define PSM_FRCE_ON_SRAM1_BITS   0x00000080
97 #define PSM_FRCE_ON_SRAM1_MSB    7
98 #define PSM_FRCE_ON_SRAM1_LSB    7
99 #define PSM_FRCE_ON_SRAM1_ACCESS "RW"
100 // -----------------------------------------------------------------------------
101 // Field       : PSM_FRCE_ON_SRAM0
102 // Description : None
103 #define PSM_FRCE_ON_SRAM0_RESET  0x0
104 #define PSM_FRCE_ON_SRAM0_BITS   0x00000040
105 #define PSM_FRCE_ON_SRAM0_MSB    6
106 #define PSM_FRCE_ON_SRAM0_LSB    6
107 #define PSM_FRCE_ON_SRAM0_ACCESS "RW"
108 // -----------------------------------------------------------------------------
109 // Field       : PSM_FRCE_ON_ROM
110 // Description : None
111 #define PSM_FRCE_ON_ROM_RESET  0x0
112 #define PSM_FRCE_ON_ROM_BITS   0x00000020
113 #define PSM_FRCE_ON_ROM_MSB    5
114 #define PSM_FRCE_ON_ROM_LSB    5
115 #define PSM_FRCE_ON_ROM_ACCESS "RW"
116 // -----------------------------------------------------------------------------
117 // Field       : PSM_FRCE_ON_BUSFABRIC
118 // Description : None
119 #define PSM_FRCE_ON_BUSFABRIC_RESET  0x0
120 #define PSM_FRCE_ON_BUSFABRIC_BITS   0x00000010
121 #define PSM_FRCE_ON_BUSFABRIC_MSB    4
122 #define PSM_FRCE_ON_BUSFABRIC_LSB    4
123 #define PSM_FRCE_ON_BUSFABRIC_ACCESS "RW"
124 // -----------------------------------------------------------------------------
125 // Field       : PSM_FRCE_ON_RESETS
126 // Description : None
127 #define PSM_FRCE_ON_RESETS_RESET  0x0
128 #define PSM_FRCE_ON_RESETS_BITS   0x00000008
129 #define PSM_FRCE_ON_RESETS_MSB    3
130 #define PSM_FRCE_ON_RESETS_LSB    3
131 #define PSM_FRCE_ON_RESETS_ACCESS "RW"
132 // -----------------------------------------------------------------------------
133 // Field       : PSM_FRCE_ON_CLOCKS
134 // Description : None
135 #define PSM_FRCE_ON_CLOCKS_RESET  0x0
136 #define PSM_FRCE_ON_CLOCKS_BITS   0x00000004
137 #define PSM_FRCE_ON_CLOCKS_MSB    2
138 #define PSM_FRCE_ON_CLOCKS_LSB    2
139 #define PSM_FRCE_ON_CLOCKS_ACCESS "RW"
140 // -----------------------------------------------------------------------------
141 // Field       : PSM_FRCE_ON_XOSC
142 // Description : None
143 #define PSM_FRCE_ON_XOSC_RESET  0x0
144 #define PSM_FRCE_ON_XOSC_BITS   0x00000002
145 #define PSM_FRCE_ON_XOSC_MSB    1
146 #define PSM_FRCE_ON_XOSC_LSB    1
147 #define PSM_FRCE_ON_XOSC_ACCESS "RW"
148 // -----------------------------------------------------------------------------
149 // Field       : PSM_FRCE_ON_ROSC
150 // Description : None
151 #define PSM_FRCE_ON_ROSC_RESET  0x0
152 #define PSM_FRCE_ON_ROSC_BITS   0x00000001
153 #define PSM_FRCE_ON_ROSC_MSB    0
154 #define PSM_FRCE_ON_ROSC_LSB    0
155 #define PSM_FRCE_ON_ROSC_ACCESS "RW"
156 // =============================================================================
157 // Register    : PSM_FRCE_OFF
158 // Description : Force into reset (i.e. power it off)
159 #define PSM_FRCE_OFF_OFFSET 0x00000004
160 #define PSM_FRCE_OFF_BITS   0x0001ffff
161 #define PSM_FRCE_OFF_RESET  0x00000000
162 // -----------------------------------------------------------------------------
163 // Field       : PSM_FRCE_OFF_PROC1
164 // Description : None
165 #define PSM_FRCE_OFF_PROC1_RESET  0x0
166 #define PSM_FRCE_OFF_PROC1_BITS   0x00010000
167 #define PSM_FRCE_OFF_PROC1_MSB    16
168 #define PSM_FRCE_OFF_PROC1_LSB    16
169 #define PSM_FRCE_OFF_PROC1_ACCESS "RW"
170 // -----------------------------------------------------------------------------
171 // Field       : PSM_FRCE_OFF_PROC0
172 // Description : None
173 #define PSM_FRCE_OFF_PROC0_RESET  0x0
174 #define PSM_FRCE_OFF_PROC0_BITS   0x00008000
175 #define PSM_FRCE_OFF_PROC0_MSB    15
176 #define PSM_FRCE_OFF_PROC0_LSB    15
177 #define PSM_FRCE_OFF_PROC0_ACCESS "RW"
178 // -----------------------------------------------------------------------------
179 // Field       : PSM_FRCE_OFF_SIO
180 // Description : None
181 #define PSM_FRCE_OFF_SIO_RESET  0x0
182 #define PSM_FRCE_OFF_SIO_BITS   0x00004000
183 #define PSM_FRCE_OFF_SIO_MSB    14
184 #define PSM_FRCE_OFF_SIO_LSB    14
185 #define PSM_FRCE_OFF_SIO_ACCESS "RW"
186 // -----------------------------------------------------------------------------
187 // Field       : PSM_FRCE_OFF_VREG_AND_CHIP_RESET
188 // Description : None
189 #define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_RESET  0x0
190 #define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_BITS   0x00002000
191 #define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_MSB    13
192 #define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_LSB    13
193 #define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_ACCESS "RW"
194 // -----------------------------------------------------------------------------
195 // Field       : PSM_FRCE_OFF_XIP
196 // Description : None
197 #define PSM_FRCE_OFF_XIP_RESET  0x0
198 #define PSM_FRCE_OFF_XIP_BITS   0x00001000
199 #define PSM_FRCE_OFF_XIP_MSB    12
200 #define PSM_FRCE_OFF_XIP_LSB    12
201 #define PSM_FRCE_OFF_XIP_ACCESS "RW"
202 // -----------------------------------------------------------------------------
203 // Field       : PSM_FRCE_OFF_SRAM5
204 // Description : None
205 #define PSM_FRCE_OFF_SRAM5_RESET  0x0
206 #define PSM_FRCE_OFF_SRAM5_BITS   0x00000800
207 #define PSM_FRCE_OFF_SRAM5_MSB    11
208 #define PSM_FRCE_OFF_SRAM5_LSB    11
209 #define PSM_FRCE_OFF_SRAM5_ACCESS "RW"
210 // -----------------------------------------------------------------------------
211 // Field       : PSM_FRCE_OFF_SRAM4
212 // Description : None
213 #define PSM_FRCE_OFF_SRAM4_RESET  0x0
214 #define PSM_FRCE_OFF_SRAM4_BITS   0x00000400
215 #define PSM_FRCE_OFF_SRAM4_MSB    10
216 #define PSM_FRCE_OFF_SRAM4_LSB    10
217 #define PSM_FRCE_OFF_SRAM4_ACCESS "RW"
218 // -----------------------------------------------------------------------------
219 // Field       : PSM_FRCE_OFF_SRAM3
220 // Description : None
221 #define PSM_FRCE_OFF_SRAM3_RESET  0x0
222 #define PSM_FRCE_OFF_SRAM3_BITS   0x00000200
223 #define PSM_FRCE_OFF_SRAM3_MSB    9
224 #define PSM_FRCE_OFF_SRAM3_LSB    9
225 #define PSM_FRCE_OFF_SRAM3_ACCESS "RW"
226 // -----------------------------------------------------------------------------
227 // Field       : PSM_FRCE_OFF_SRAM2
228 // Description : None
229 #define PSM_FRCE_OFF_SRAM2_RESET  0x0
230 #define PSM_FRCE_OFF_SRAM2_BITS   0x00000100
231 #define PSM_FRCE_OFF_SRAM2_MSB    8
232 #define PSM_FRCE_OFF_SRAM2_LSB    8
233 #define PSM_FRCE_OFF_SRAM2_ACCESS "RW"
234 // -----------------------------------------------------------------------------
235 // Field       : PSM_FRCE_OFF_SRAM1
236 // Description : None
237 #define PSM_FRCE_OFF_SRAM1_RESET  0x0
238 #define PSM_FRCE_OFF_SRAM1_BITS   0x00000080
239 #define PSM_FRCE_OFF_SRAM1_MSB    7
240 #define PSM_FRCE_OFF_SRAM1_LSB    7
241 #define PSM_FRCE_OFF_SRAM1_ACCESS "RW"
242 // -----------------------------------------------------------------------------
243 // Field       : PSM_FRCE_OFF_SRAM0
244 // Description : None
245 #define PSM_FRCE_OFF_SRAM0_RESET  0x0
246 #define PSM_FRCE_OFF_SRAM0_BITS   0x00000040
247 #define PSM_FRCE_OFF_SRAM0_MSB    6
248 #define PSM_FRCE_OFF_SRAM0_LSB    6
249 #define PSM_FRCE_OFF_SRAM0_ACCESS "RW"
250 // -----------------------------------------------------------------------------
251 // Field       : PSM_FRCE_OFF_ROM
252 // Description : None
253 #define PSM_FRCE_OFF_ROM_RESET  0x0
254 #define PSM_FRCE_OFF_ROM_BITS   0x00000020
255 #define PSM_FRCE_OFF_ROM_MSB    5
256 #define PSM_FRCE_OFF_ROM_LSB    5
257 #define PSM_FRCE_OFF_ROM_ACCESS "RW"
258 // -----------------------------------------------------------------------------
259 // Field       : PSM_FRCE_OFF_BUSFABRIC
260 // Description : None
261 #define PSM_FRCE_OFF_BUSFABRIC_RESET  0x0
262 #define PSM_FRCE_OFF_BUSFABRIC_BITS   0x00000010
263 #define PSM_FRCE_OFF_BUSFABRIC_MSB    4
264 #define PSM_FRCE_OFF_BUSFABRIC_LSB    4
265 #define PSM_FRCE_OFF_BUSFABRIC_ACCESS "RW"
266 // -----------------------------------------------------------------------------
267 // Field       : PSM_FRCE_OFF_RESETS
268 // Description : None
269 #define PSM_FRCE_OFF_RESETS_RESET  0x0
270 #define PSM_FRCE_OFF_RESETS_BITS   0x00000008
271 #define PSM_FRCE_OFF_RESETS_MSB    3
272 #define PSM_FRCE_OFF_RESETS_LSB    3
273 #define PSM_FRCE_OFF_RESETS_ACCESS "RW"
274 // -----------------------------------------------------------------------------
275 // Field       : PSM_FRCE_OFF_CLOCKS
276 // Description : None
277 #define PSM_FRCE_OFF_CLOCKS_RESET  0x0
278 #define PSM_FRCE_OFF_CLOCKS_BITS   0x00000004
279 #define PSM_FRCE_OFF_CLOCKS_MSB    2
280 #define PSM_FRCE_OFF_CLOCKS_LSB    2
281 #define PSM_FRCE_OFF_CLOCKS_ACCESS "RW"
282 // -----------------------------------------------------------------------------
283 // Field       : PSM_FRCE_OFF_XOSC
284 // Description : None
285 #define PSM_FRCE_OFF_XOSC_RESET  0x0
286 #define PSM_FRCE_OFF_XOSC_BITS   0x00000002
287 #define PSM_FRCE_OFF_XOSC_MSB    1
288 #define PSM_FRCE_OFF_XOSC_LSB    1
289 #define PSM_FRCE_OFF_XOSC_ACCESS "RW"
290 // -----------------------------------------------------------------------------
291 // Field       : PSM_FRCE_OFF_ROSC
292 // Description : None
293 #define PSM_FRCE_OFF_ROSC_RESET  0x0
294 #define PSM_FRCE_OFF_ROSC_BITS   0x00000001
295 #define PSM_FRCE_OFF_ROSC_MSB    0
296 #define PSM_FRCE_OFF_ROSC_LSB    0
297 #define PSM_FRCE_OFF_ROSC_ACCESS "RW"
298 // =============================================================================
299 // Register    : PSM_WDSEL
300 // Description : Set to 1 if this peripheral should be reset when the watchdog
301 //               fires.
302 #define PSM_WDSEL_OFFSET 0x00000008
303 #define PSM_WDSEL_BITS   0x0001ffff
304 #define PSM_WDSEL_RESET  0x00000000
305 // -----------------------------------------------------------------------------
306 // Field       : PSM_WDSEL_PROC1
307 // Description : None
308 #define PSM_WDSEL_PROC1_RESET  0x0
309 #define PSM_WDSEL_PROC1_BITS   0x00010000
310 #define PSM_WDSEL_PROC1_MSB    16
311 #define PSM_WDSEL_PROC1_LSB    16
312 #define PSM_WDSEL_PROC1_ACCESS "RW"
313 // -----------------------------------------------------------------------------
314 // Field       : PSM_WDSEL_PROC0
315 // Description : None
316 #define PSM_WDSEL_PROC0_RESET  0x0
317 #define PSM_WDSEL_PROC0_BITS   0x00008000
318 #define PSM_WDSEL_PROC0_MSB    15
319 #define PSM_WDSEL_PROC0_LSB    15
320 #define PSM_WDSEL_PROC0_ACCESS "RW"
321 // -----------------------------------------------------------------------------
322 // Field       : PSM_WDSEL_SIO
323 // Description : None
324 #define PSM_WDSEL_SIO_RESET  0x0
325 #define PSM_WDSEL_SIO_BITS   0x00004000
326 #define PSM_WDSEL_SIO_MSB    14
327 #define PSM_WDSEL_SIO_LSB    14
328 #define PSM_WDSEL_SIO_ACCESS "RW"
329 // -----------------------------------------------------------------------------
330 // Field       : PSM_WDSEL_VREG_AND_CHIP_RESET
331 // Description : None
332 #define PSM_WDSEL_VREG_AND_CHIP_RESET_RESET  0x0
333 #define PSM_WDSEL_VREG_AND_CHIP_RESET_BITS   0x00002000
334 #define PSM_WDSEL_VREG_AND_CHIP_RESET_MSB    13
335 #define PSM_WDSEL_VREG_AND_CHIP_RESET_LSB    13
336 #define PSM_WDSEL_VREG_AND_CHIP_RESET_ACCESS "RW"
337 // -----------------------------------------------------------------------------
338 // Field       : PSM_WDSEL_XIP
339 // Description : None
340 #define PSM_WDSEL_XIP_RESET  0x0
341 #define PSM_WDSEL_XIP_BITS   0x00001000
342 #define PSM_WDSEL_XIP_MSB    12
343 #define PSM_WDSEL_XIP_LSB    12
344 #define PSM_WDSEL_XIP_ACCESS "RW"
345 // -----------------------------------------------------------------------------
346 // Field       : PSM_WDSEL_SRAM5
347 // Description : None
348 #define PSM_WDSEL_SRAM5_RESET  0x0
349 #define PSM_WDSEL_SRAM5_BITS   0x00000800
350 #define PSM_WDSEL_SRAM5_MSB    11
351 #define PSM_WDSEL_SRAM5_LSB    11
352 #define PSM_WDSEL_SRAM5_ACCESS "RW"
353 // -----------------------------------------------------------------------------
354 // Field       : PSM_WDSEL_SRAM4
355 // Description : None
356 #define PSM_WDSEL_SRAM4_RESET  0x0
357 #define PSM_WDSEL_SRAM4_BITS   0x00000400
358 #define PSM_WDSEL_SRAM4_MSB    10
359 #define PSM_WDSEL_SRAM4_LSB    10
360 #define PSM_WDSEL_SRAM4_ACCESS "RW"
361 // -----------------------------------------------------------------------------
362 // Field       : PSM_WDSEL_SRAM3
363 // Description : None
364 #define PSM_WDSEL_SRAM3_RESET  0x0
365 #define PSM_WDSEL_SRAM3_BITS   0x00000200
366 #define PSM_WDSEL_SRAM3_MSB    9
367 #define PSM_WDSEL_SRAM3_LSB    9
368 #define PSM_WDSEL_SRAM3_ACCESS "RW"
369 // -----------------------------------------------------------------------------
370 // Field       : PSM_WDSEL_SRAM2
371 // Description : None
372 #define PSM_WDSEL_SRAM2_RESET  0x0
373 #define PSM_WDSEL_SRAM2_BITS   0x00000100
374 #define PSM_WDSEL_SRAM2_MSB    8
375 #define PSM_WDSEL_SRAM2_LSB    8
376 #define PSM_WDSEL_SRAM2_ACCESS "RW"
377 // -----------------------------------------------------------------------------
378 // Field       : PSM_WDSEL_SRAM1
379 // Description : None
380 #define PSM_WDSEL_SRAM1_RESET  0x0
381 #define PSM_WDSEL_SRAM1_BITS   0x00000080
382 #define PSM_WDSEL_SRAM1_MSB    7
383 #define PSM_WDSEL_SRAM1_LSB    7
384 #define PSM_WDSEL_SRAM1_ACCESS "RW"
385 // -----------------------------------------------------------------------------
386 // Field       : PSM_WDSEL_SRAM0
387 // Description : None
388 #define PSM_WDSEL_SRAM0_RESET  0x0
389 #define PSM_WDSEL_SRAM0_BITS   0x00000040
390 #define PSM_WDSEL_SRAM0_MSB    6
391 #define PSM_WDSEL_SRAM0_LSB    6
392 #define PSM_WDSEL_SRAM0_ACCESS "RW"
393 // -----------------------------------------------------------------------------
394 // Field       : PSM_WDSEL_ROM
395 // Description : None
396 #define PSM_WDSEL_ROM_RESET  0x0
397 #define PSM_WDSEL_ROM_BITS   0x00000020
398 #define PSM_WDSEL_ROM_MSB    5
399 #define PSM_WDSEL_ROM_LSB    5
400 #define PSM_WDSEL_ROM_ACCESS "RW"
401 // -----------------------------------------------------------------------------
402 // Field       : PSM_WDSEL_BUSFABRIC
403 // Description : None
404 #define PSM_WDSEL_BUSFABRIC_RESET  0x0
405 #define PSM_WDSEL_BUSFABRIC_BITS   0x00000010
406 #define PSM_WDSEL_BUSFABRIC_MSB    4
407 #define PSM_WDSEL_BUSFABRIC_LSB    4
408 #define PSM_WDSEL_BUSFABRIC_ACCESS "RW"
409 // -----------------------------------------------------------------------------
410 // Field       : PSM_WDSEL_RESETS
411 // Description : None
412 #define PSM_WDSEL_RESETS_RESET  0x0
413 #define PSM_WDSEL_RESETS_BITS   0x00000008
414 #define PSM_WDSEL_RESETS_MSB    3
415 #define PSM_WDSEL_RESETS_LSB    3
416 #define PSM_WDSEL_RESETS_ACCESS "RW"
417 // -----------------------------------------------------------------------------
418 // Field       : PSM_WDSEL_CLOCKS
419 // Description : None
420 #define PSM_WDSEL_CLOCKS_RESET  0x0
421 #define PSM_WDSEL_CLOCKS_BITS   0x00000004
422 #define PSM_WDSEL_CLOCKS_MSB    2
423 #define PSM_WDSEL_CLOCKS_LSB    2
424 #define PSM_WDSEL_CLOCKS_ACCESS "RW"
425 // -----------------------------------------------------------------------------
426 // Field       : PSM_WDSEL_XOSC
427 // Description : None
428 #define PSM_WDSEL_XOSC_RESET  0x0
429 #define PSM_WDSEL_XOSC_BITS   0x00000002
430 #define PSM_WDSEL_XOSC_MSB    1
431 #define PSM_WDSEL_XOSC_LSB    1
432 #define PSM_WDSEL_XOSC_ACCESS "RW"
433 // -----------------------------------------------------------------------------
434 // Field       : PSM_WDSEL_ROSC
435 // Description : None
436 #define PSM_WDSEL_ROSC_RESET  0x0
437 #define PSM_WDSEL_ROSC_BITS   0x00000001
438 #define PSM_WDSEL_ROSC_MSB    0
439 #define PSM_WDSEL_ROSC_LSB    0
440 #define PSM_WDSEL_ROSC_ACCESS "RW"
441 // =============================================================================
442 // Register    : PSM_DONE
443 // Description : Indicates the peripheral's registers are ready to access.
444 #define PSM_DONE_OFFSET 0x0000000c
445 #define PSM_DONE_BITS   0x0001ffff
446 #define PSM_DONE_RESET  0x00000000
447 // -----------------------------------------------------------------------------
448 // Field       : PSM_DONE_PROC1
449 // Description : None
450 #define PSM_DONE_PROC1_RESET  0x0
451 #define PSM_DONE_PROC1_BITS   0x00010000
452 #define PSM_DONE_PROC1_MSB    16
453 #define PSM_DONE_PROC1_LSB    16
454 #define PSM_DONE_PROC1_ACCESS "RO"
455 // -----------------------------------------------------------------------------
456 // Field       : PSM_DONE_PROC0
457 // Description : None
458 #define PSM_DONE_PROC0_RESET  0x0
459 #define PSM_DONE_PROC0_BITS   0x00008000
460 #define PSM_DONE_PROC0_MSB    15
461 #define PSM_DONE_PROC0_LSB    15
462 #define PSM_DONE_PROC0_ACCESS "RO"
463 // -----------------------------------------------------------------------------
464 // Field       : PSM_DONE_SIO
465 // Description : None
466 #define PSM_DONE_SIO_RESET  0x0
467 #define PSM_DONE_SIO_BITS   0x00004000
468 #define PSM_DONE_SIO_MSB    14
469 #define PSM_DONE_SIO_LSB    14
470 #define PSM_DONE_SIO_ACCESS "RO"
471 // -----------------------------------------------------------------------------
472 // Field       : PSM_DONE_VREG_AND_CHIP_RESET
473 // Description : None
474 #define PSM_DONE_VREG_AND_CHIP_RESET_RESET  0x0
475 #define PSM_DONE_VREG_AND_CHIP_RESET_BITS   0x00002000
476 #define PSM_DONE_VREG_AND_CHIP_RESET_MSB    13
477 #define PSM_DONE_VREG_AND_CHIP_RESET_LSB    13
478 #define PSM_DONE_VREG_AND_CHIP_RESET_ACCESS "RO"
479 // -----------------------------------------------------------------------------
480 // Field       : PSM_DONE_XIP
481 // Description : None
482 #define PSM_DONE_XIP_RESET  0x0
483 #define PSM_DONE_XIP_BITS   0x00001000
484 #define PSM_DONE_XIP_MSB    12
485 #define PSM_DONE_XIP_LSB    12
486 #define PSM_DONE_XIP_ACCESS "RO"
487 // -----------------------------------------------------------------------------
488 // Field       : PSM_DONE_SRAM5
489 // Description : None
490 #define PSM_DONE_SRAM5_RESET  0x0
491 #define PSM_DONE_SRAM5_BITS   0x00000800
492 #define PSM_DONE_SRAM5_MSB    11
493 #define PSM_DONE_SRAM5_LSB    11
494 #define PSM_DONE_SRAM5_ACCESS "RO"
495 // -----------------------------------------------------------------------------
496 // Field       : PSM_DONE_SRAM4
497 // Description : None
498 #define PSM_DONE_SRAM4_RESET  0x0
499 #define PSM_DONE_SRAM4_BITS   0x00000400
500 #define PSM_DONE_SRAM4_MSB    10
501 #define PSM_DONE_SRAM4_LSB    10
502 #define PSM_DONE_SRAM4_ACCESS "RO"
503 // -----------------------------------------------------------------------------
504 // Field       : PSM_DONE_SRAM3
505 // Description : None
506 #define PSM_DONE_SRAM3_RESET  0x0
507 #define PSM_DONE_SRAM3_BITS   0x00000200
508 #define PSM_DONE_SRAM3_MSB    9
509 #define PSM_DONE_SRAM3_LSB    9
510 #define PSM_DONE_SRAM3_ACCESS "RO"
511 // -----------------------------------------------------------------------------
512 // Field       : PSM_DONE_SRAM2
513 // Description : None
514 #define PSM_DONE_SRAM2_RESET  0x0
515 #define PSM_DONE_SRAM2_BITS   0x00000100
516 #define PSM_DONE_SRAM2_MSB    8
517 #define PSM_DONE_SRAM2_LSB    8
518 #define PSM_DONE_SRAM2_ACCESS "RO"
519 // -----------------------------------------------------------------------------
520 // Field       : PSM_DONE_SRAM1
521 // Description : None
522 #define PSM_DONE_SRAM1_RESET  0x0
523 #define PSM_DONE_SRAM1_BITS   0x00000080
524 #define PSM_DONE_SRAM1_MSB    7
525 #define PSM_DONE_SRAM1_LSB    7
526 #define PSM_DONE_SRAM1_ACCESS "RO"
527 // -----------------------------------------------------------------------------
528 // Field       : PSM_DONE_SRAM0
529 // Description : None
530 #define PSM_DONE_SRAM0_RESET  0x0
531 #define PSM_DONE_SRAM0_BITS   0x00000040
532 #define PSM_DONE_SRAM0_MSB    6
533 #define PSM_DONE_SRAM0_LSB    6
534 #define PSM_DONE_SRAM0_ACCESS "RO"
535 // -----------------------------------------------------------------------------
536 // Field       : PSM_DONE_ROM
537 // Description : None
538 #define PSM_DONE_ROM_RESET  0x0
539 #define PSM_DONE_ROM_BITS   0x00000020
540 #define PSM_DONE_ROM_MSB    5
541 #define PSM_DONE_ROM_LSB    5
542 #define PSM_DONE_ROM_ACCESS "RO"
543 // -----------------------------------------------------------------------------
544 // Field       : PSM_DONE_BUSFABRIC
545 // Description : None
546 #define PSM_DONE_BUSFABRIC_RESET  0x0
547 #define PSM_DONE_BUSFABRIC_BITS   0x00000010
548 #define PSM_DONE_BUSFABRIC_MSB    4
549 #define PSM_DONE_BUSFABRIC_LSB    4
550 #define PSM_DONE_BUSFABRIC_ACCESS "RO"
551 // -----------------------------------------------------------------------------
552 // Field       : PSM_DONE_RESETS
553 // Description : None
554 #define PSM_DONE_RESETS_RESET  0x0
555 #define PSM_DONE_RESETS_BITS   0x00000008
556 #define PSM_DONE_RESETS_MSB    3
557 #define PSM_DONE_RESETS_LSB    3
558 #define PSM_DONE_RESETS_ACCESS "RO"
559 // -----------------------------------------------------------------------------
560 // Field       : PSM_DONE_CLOCKS
561 // Description : None
562 #define PSM_DONE_CLOCKS_RESET  0x0
563 #define PSM_DONE_CLOCKS_BITS   0x00000004
564 #define PSM_DONE_CLOCKS_MSB    2
565 #define PSM_DONE_CLOCKS_LSB    2
566 #define PSM_DONE_CLOCKS_ACCESS "RO"
567 // -----------------------------------------------------------------------------
568 // Field       : PSM_DONE_XOSC
569 // Description : None
570 #define PSM_DONE_XOSC_RESET  0x0
571 #define PSM_DONE_XOSC_BITS   0x00000002
572 #define PSM_DONE_XOSC_MSB    1
573 #define PSM_DONE_XOSC_LSB    1
574 #define PSM_DONE_XOSC_ACCESS "RO"
575 // -----------------------------------------------------------------------------
576 // Field       : PSM_DONE_ROSC
577 // Description : None
578 #define PSM_DONE_ROSC_RESET  0x0
579 #define PSM_DONE_ROSC_BITS   0x00000001
580 #define PSM_DONE_ROSC_MSB    0
581 #define PSM_DONE_ROSC_LSB    0
582 #define PSM_DONE_ROSC_ACCESS "RO"
583 // =============================================================================
584 #endif // HARDWARE_REGS_PSM_DEFINED
585