1 /** 2 * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 // ============================================================================= 7 // Register block : PWM 8 // Version : 1 9 // Bus type : apb 10 // Description : Simple PWM 11 // ============================================================================= 12 #ifndef HARDWARE_REGS_PWM_DEFINED 13 #define HARDWARE_REGS_PWM_DEFINED 14 // ============================================================================= 15 // Register : PWM_CH0_CSR 16 // Description : Control and status register 17 #define PWM_CH0_CSR_OFFSET 0x00000000 18 #define PWM_CH0_CSR_BITS 0x000000ff 19 #define PWM_CH0_CSR_RESET 0x00000000 20 // ----------------------------------------------------------------------------- 21 // Field : PWM_CH0_CSR_PH_ADV 22 // Description : Advance the phase of the counter by 1 count, while it is 23 // running. 24 // Self-clearing. Write a 1, and poll until low. Counter must be 25 // running 26 // at less than full speed (div_int + div_frac / 16 > 1) 27 #define PWM_CH0_CSR_PH_ADV_RESET 0x0 28 #define PWM_CH0_CSR_PH_ADV_BITS 0x00000080 29 #define PWM_CH0_CSR_PH_ADV_MSB 7 30 #define PWM_CH0_CSR_PH_ADV_LSB 7 31 #define PWM_CH0_CSR_PH_ADV_ACCESS "SC" 32 // ----------------------------------------------------------------------------- 33 // Field : PWM_CH0_CSR_PH_RET 34 // Description : Retard the phase of the counter by 1 count, while it is 35 // running. 36 // Self-clearing. Write a 1, and poll until low. Counter must be 37 // running. 38 #define PWM_CH0_CSR_PH_RET_RESET 0x0 39 #define PWM_CH0_CSR_PH_RET_BITS 0x00000040 40 #define PWM_CH0_CSR_PH_RET_MSB 6 41 #define PWM_CH0_CSR_PH_RET_LSB 6 42 #define PWM_CH0_CSR_PH_RET_ACCESS "SC" 43 // ----------------------------------------------------------------------------- 44 // Field : PWM_CH0_CSR_DIVMODE 45 // Description : 0x0 -> Free-running counting at rate dictated by fractional 46 // divider 47 // 0x1 -> Fractional divider operation is gated by the PWM B pin. 48 // 0x2 -> Counter advances with each rising edge of the PWM B pin. 49 // 0x3 -> Counter advances with each falling edge of the PWM B 50 // pin. 51 #define PWM_CH0_CSR_DIVMODE_RESET 0x0 52 #define PWM_CH0_CSR_DIVMODE_BITS 0x00000030 53 #define PWM_CH0_CSR_DIVMODE_MSB 5 54 #define PWM_CH0_CSR_DIVMODE_LSB 4 55 #define PWM_CH0_CSR_DIVMODE_ACCESS "RW" 56 #define PWM_CH0_CSR_DIVMODE_VALUE_DIV 0x0 57 #define PWM_CH0_CSR_DIVMODE_VALUE_LEVEL 0x1 58 #define PWM_CH0_CSR_DIVMODE_VALUE_RISE 0x2 59 #define PWM_CH0_CSR_DIVMODE_VALUE_FALL 0x3 60 // ----------------------------------------------------------------------------- 61 // Field : PWM_CH0_CSR_B_INV 62 // Description : Invert output B 63 #define PWM_CH0_CSR_B_INV_RESET 0x0 64 #define PWM_CH0_CSR_B_INV_BITS 0x00000008 65 #define PWM_CH0_CSR_B_INV_MSB 3 66 #define PWM_CH0_CSR_B_INV_LSB 3 67 #define PWM_CH0_CSR_B_INV_ACCESS "RW" 68 // ----------------------------------------------------------------------------- 69 // Field : PWM_CH0_CSR_A_INV 70 // Description : Invert output A 71 #define PWM_CH0_CSR_A_INV_RESET 0x0 72 #define PWM_CH0_CSR_A_INV_BITS 0x00000004 73 #define PWM_CH0_CSR_A_INV_MSB 2 74 #define PWM_CH0_CSR_A_INV_LSB 2 75 #define PWM_CH0_CSR_A_INV_ACCESS "RW" 76 // ----------------------------------------------------------------------------- 77 // Field : PWM_CH0_CSR_PH_CORRECT 78 // Description : 1: Enable phase-correct modulation. 0: Trailing-edge 79 #define PWM_CH0_CSR_PH_CORRECT_RESET 0x0 80 #define PWM_CH0_CSR_PH_CORRECT_BITS 0x00000002 81 #define PWM_CH0_CSR_PH_CORRECT_MSB 1 82 #define PWM_CH0_CSR_PH_CORRECT_LSB 1 83 #define PWM_CH0_CSR_PH_CORRECT_ACCESS "RW" 84 // ----------------------------------------------------------------------------- 85 // Field : PWM_CH0_CSR_EN 86 // Description : Enable the PWM channel. 87 #define PWM_CH0_CSR_EN_RESET 0x0 88 #define PWM_CH0_CSR_EN_BITS 0x00000001 89 #define PWM_CH0_CSR_EN_MSB 0 90 #define PWM_CH0_CSR_EN_LSB 0 91 #define PWM_CH0_CSR_EN_ACCESS "RW" 92 // ============================================================================= 93 // Register : PWM_CH0_DIV 94 // Description : INT and FRAC form a fixed-point fractional number. 95 // Counting rate is system clock frequency divided by this number. 96 // Fractional division uses simple 1st-order sigma-delta. 97 #define PWM_CH0_DIV_OFFSET 0x00000004 98 #define PWM_CH0_DIV_BITS 0x00000fff 99 #define PWM_CH0_DIV_RESET 0x00000010 100 // ----------------------------------------------------------------------------- 101 // Field : PWM_CH0_DIV_INT 102 // Description : None 103 #define PWM_CH0_DIV_INT_RESET 0x01 104 #define PWM_CH0_DIV_INT_BITS 0x00000ff0 105 #define PWM_CH0_DIV_INT_MSB 11 106 #define PWM_CH0_DIV_INT_LSB 4 107 #define PWM_CH0_DIV_INT_ACCESS "RW" 108 // ----------------------------------------------------------------------------- 109 // Field : PWM_CH0_DIV_FRAC 110 // Description : None 111 #define PWM_CH0_DIV_FRAC_RESET 0x0 112 #define PWM_CH0_DIV_FRAC_BITS 0x0000000f 113 #define PWM_CH0_DIV_FRAC_MSB 3 114 #define PWM_CH0_DIV_FRAC_LSB 0 115 #define PWM_CH0_DIV_FRAC_ACCESS "RW" 116 // ============================================================================= 117 // Register : PWM_CH0_CTR 118 // Description : Direct access to the PWM counter 119 #define PWM_CH0_CTR_OFFSET 0x00000008 120 #define PWM_CH0_CTR_BITS 0x0000ffff 121 #define PWM_CH0_CTR_RESET 0x00000000 122 #define PWM_CH0_CTR_MSB 15 123 #define PWM_CH0_CTR_LSB 0 124 #define PWM_CH0_CTR_ACCESS "RW" 125 // ============================================================================= 126 // Register : PWM_CH0_CC 127 // Description : Counter compare values 128 #define PWM_CH0_CC_OFFSET 0x0000000c 129 #define PWM_CH0_CC_BITS 0xffffffff 130 #define PWM_CH0_CC_RESET 0x00000000 131 // ----------------------------------------------------------------------------- 132 // Field : PWM_CH0_CC_B 133 // Description : None 134 #define PWM_CH0_CC_B_RESET 0x0000 135 #define PWM_CH0_CC_B_BITS 0xffff0000 136 #define PWM_CH0_CC_B_MSB 31 137 #define PWM_CH0_CC_B_LSB 16 138 #define PWM_CH0_CC_B_ACCESS "RW" 139 // ----------------------------------------------------------------------------- 140 // Field : PWM_CH0_CC_A 141 // Description : None 142 #define PWM_CH0_CC_A_RESET 0x0000 143 #define PWM_CH0_CC_A_BITS 0x0000ffff 144 #define PWM_CH0_CC_A_MSB 15 145 #define PWM_CH0_CC_A_LSB 0 146 #define PWM_CH0_CC_A_ACCESS "RW" 147 // ============================================================================= 148 // Register : PWM_CH0_TOP 149 // Description : Counter wrap value 150 #define PWM_CH0_TOP_OFFSET 0x00000010 151 #define PWM_CH0_TOP_BITS 0x0000ffff 152 #define PWM_CH0_TOP_RESET 0x0000ffff 153 #define PWM_CH0_TOP_MSB 15 154 #define PWM_CH0_TOP_LSB 0 155 #define PWM_CH0_TOP_ACCESS "RW" 156 // ============================================================================= 157 // Register : PWM_CH1_CSR 158 // Description : Control and status register 159 #define PWM_CH1_CSR_OFFSET 0x00000014 160 #define PWM_CH1_CSR_BITS 0x000000ff 161 #define PWM_CH1_CSR_RESET 0x00000000 162 // ----------------------------------------------------------------------------- 163 // Field : PWM_CH1_CSR_PH_ADV 164 // Description : Advance the phase of the counter by 1 count, while it is 165 // running. 166 // Self-clearing. Write a 1, and poll until low. Counter must be 167 // running 168 // at less than full speed (div_int + div_frac / 16 > 1) 169 #define PWM_CH1_CSR_PH_ADV_RESET 0x0 170 #define PWM_CH1_CSR_PH_ADV_BITS 0x00000080 171 #define PWM_CH1_CSR_PH_ADV_MSB 7 172 #define PWM_CH1_CSR_PH_ADV_LSB 7 173 #define PWM_CH1_CSR_PH_ADV_ACCESS "SC" 174 // ----------------------------------------------------------------------------- 175 // Field : PWM_CH1_CSR_PH_RET 176 // Description : Retard the phase of the counter by 1 count, while it is 177 // running. 178 // Self-clearing. Write a 1, and poll until low. Counter must be 179 // running. 180 #define PWM_CH1_CSR_PH_RET_RESET 0x0 181 #define PWM_CH1_CSR_PH_RET_BITS 0x00000040 182 #define PWM_CH1_CSR_PH_RET_MSB 6 183 #define PWM_CH1_CSR_PH_RET_LSB 6 184 #define PWM_CH1_CSR_PH_RET_ACCESS "SC" 185 // ----------------------------------------------------------------------------- 186 // Field : PWM_CH1_CSR_DIVMODE 187 // Description : 0x0 -> Free-running counting at rate dictated by fractional 188 // divider 189 // 0x1 -> Fractional divider operation is gated by the PWM B pin. 190 // 0x2 -> Counter advances with each rising edge of the PWM B pin. 191 // 0x3 -> Counter advances with each falling edge of the PWM B 192 // pin. 193 #define PWM_CH1_CSR_DIVMODE_RESET 0x0 194 #define PWM_CH1_CSR_DIVMODE_BITS 0x00000030 195 #define PWM_CH1_CSR_DIVMODE_MSB 5 196 #define PWM_CH1_CSR_DIVMODE_LSB 4 197 #define PWM_CH1_CSR_DIVMODE_ACCESS "RW" 198 #define PWM_CH1_CSR_DIVMODE_VALUE_DIV 0x0 199 #define PWM_CH1_CSR_DIVMODE_VALUE_LEVEL 0x1 200 #define PWM_CH1_CSR_DIVMODE_VALUE_RISE 0x2 201 #define PWM_CH1_CSR_DIVMODE_VALUE_FALL 0x3 202 // ----------------------------------------------------------------------------- 203 // Field : PWM_CH1_CSR_B_INV 204 // Description : Invert output B 205 #define PWM_CH1_CSR_B_INV_RESET 0x0 206 #define PWM_CH1_CSR_B_INV_BITS 0x00000008 207 #define PWM_CH1_CSR_B_INV_MSB 3 208 #define PWM_CH1_CSR_B_INV_LSB 3 209 #define PWM_CH1_CSR_B_INV_ACCESS "RW" 210 // ----------------------------------------------------------------------------- 211 // Field : PWM_CH1_CSR_A_INV 212 // Description : Invert output A 213 #define PWM_CH1_CSR_A_INV_RESET 0x0 214 #define PWM_CH1_CSR_A_INV_BITS 0x00000004 215 #define PWM_CH1_CSR_A_INV_MSB 2 216 #define PWM_CH1_CSR_A_INV_LSB 2 217 #define PWM_CH1_CSR_A_INV_ACCESS "RW" 218 // ----------------------------------------------------------------------------- 219 // Field : PWM_CH1_CSR_PH_CORRECT 220 // Description : 1: Enable phase-correct modulation. 0: Trailing-edge 221 #define PWM_CH1_CSR_PH_CORRECT_RESET 0x0 222 #define PWM_CH1_CSR_PH_CORRECT_BITS 0x00000002 223 #define PWM_CH1_CSR_PH_CORRECT_MSB 1 224 #define PWM_CH1_CSR_PH_CORRECT_LSB 1 225 #define PWM_CH1_CSR_PH_CORRECT_ACCESS "RW" 226 // ----------------------------------------------------------------------------- 227 // Field : PWM_CH1_CSR_EN 228 // Description : Enable the PWM channel. 229 #define PWM_CH1_CSR_EN_RESET 0x0 230 #define PWM_CH1_CSR_EN_BITS 0x00000001 231 #define PWM_CH1_CSR_EN_MSB 0 232 #define PWM_CH1_CSR_EN_LSB 0 233 #define PWM_CH1_CSR_EN_ACCESS "RW" 234 // ============================================================================= 235 // Register : PWM_CH1_DIV 236 // Description : INT and FRAC form a fixed-point fractional number. 237 // Counting rate is system clock frequency divided by this number. 238 // Fractional division uses simple 1st-order sigma-delta. 239 #define PWM_CH1_DIV_OFFSET 0x00000018 240 #define PWM_CH1_DIV_BITS 0x00000fff 241 #define PWM_CH1_DIV_RESET 0x00000010 242 // ----------------------------------------------------------------------------- 243 // Field : PWM_CH1_DIV_INT 244 // Description : None 245 #define PWM_CH1_DIV_INT_RESET 0x01 246 #define PWM_CH1_DIV_INT_BITS 0x00000ff0 247 #define PWM_CH1_DIV_INT_MSB 11 248 #define PWM_CH1_DIV_INT_LSB 4 249 #define PWM_CH1_DIV_INT_ACCESS "RW" 250 // ----------------------------------------------------------------------------- 251 // Field : PWM_CH1_DIV_FRAC 252 // Description : None 253 #define PWM_CH1_DIV_FRAC_RESET 0x0 254 #define PWM_CH1_DIV_FRAC_BITS 0x0000000f 255 #define PWM_CH1_DIV_FRAC_MSB 3 256 #define PWM_CH1_DIV_FRAC_LSB 0 257 #define PWM_CH1_DIV_FRAC_ACCESS "RW" 258 // ============================================================================= 259 // Register : PWM_CH1_CTR 260 // Description : Direct access to the PWM counter 261 #define PWM_CH1_CTR_OFFSET 0x0000001c 262 #define PWM_CH1_CTR_BITS 0x0000ffff 263 #define PWM_CH1_CTR_RESET 0x00000000 264 #define PWM_CH1_CTR_MSB 15 265 #define PWM_CH1_CTR_LSB 0 266 #define PWM_CH1_CTR_ACCESS "RW" 267 // ============================================================================= 268 // Register : PWM_CH1_CC 269 // Description : Counter compare values 270 #define PWM_CH1_CC_OFFSET 0x00000020 271 #define PWM_CH1_CC_BITS 0xffffffff 272 #define PWM_CH1_CC_RESET 0x00000000 273 // ----------------------------------------------------------------------------- 274 // Field : PWM_CH1_CC_B 275 // Description : None 276 #define PWM_CH1_CC_B_RESET 0x0000 277 #define PWM_CH1_CC_B_BITS 0xffff0000 278 #define PWM_CH1_CC_B_MSB 31 279 #define PWM_CH1_CC_B_LSB 16 280 #define PWM_CH1_CC_B_ACCESS "RW" 281 // ----------------------------------------------------------------------------- 282 // Field : PWM_CH1_CC_A 283 // Description : None 284 #define PWM_CH1_CC_A_RESET 0x0000 285 #define PWM_CH1_CC_A_BITS 0x0000ffff 286 #define PWM_CH1_CC_A_MSB 15 287 #define PWM_CH1_CC_A_LSB 0 288 #define PWM_CH1_CC_A_ACCESS "RW" 289 // ============================================================================= 290 // Register : PWM_CH1_TOP 291 // Description : Counter wrap value 292 #define PWM_CH1_TOP_OFFSET 0x00000024 293 #define PWM_CH1_TOP_BITS 0x0000ffff 294 #define PWM_CH1_TOP_RESET 0x0000ffff 295 #define PWM_CH1_TOP_MSB 15 296 #define PWM_CH1_TOP_LSB 0 297 #define PWM_CH1_TOP_ACCESS "RW" 298 // ============================================================================= 299 // Register : PWM_CH2_CSR 300 // Description : Control and status register 301 #define PWM_CH2_CSR_OFFSET 0x00000028 302 #define PWM_CH2_CSR_BITS 0x000000ff 303 #define PWM_CH2_CSR_RESET 0x00000000 304 // ----------------------------------------------------------------------------- 305 // Field : PWM_CH2_CSR_PH_ADV 306 // Description : Advance the phase of the counter by 1 count, while it is 307 // running. 308 // Self-clearing. Write a 1, and poll until low. Counter must be 309 // running 310 // at less than full speed (div_int + div_frac / 16 > 1) 311 #define PWM_CH2_CSR_PH_ADV_RESET 0x0 312 #define PWM_CH2_CSR_PH_ADV_BITS 0x00000080 313 #define PWM_CH2_CSR_PH_ADV_MSB 7 314 #define PWM_CH2_CSR_PH_ADV_LSB 7 315 #define PWM_CH2_CSR_PH_ADV_ACCESS "SC" 316 // ----------------------------------------------------------------------------- 317 // Field : PWM_CH2_CSR_PH_RET 318 // Description : Retard the phase of the counter by 1 count, while it is 319 // running. 320 // Self-clearing. Write a 1, and poll until low. Counter must be 321 // running. 322 #define PWM_CH2_CSR_PH_RET_RESET 0x0 323 #define PWM_CH2_CSR_PH_RET_BITS 0x00000040 324 #define PWM_CH2_CSR_PH_RET_MSB 6 325 #define PWM_CH2_CSR_PH_RET_LSB 6 326 #define PWM_CH2_CSR_PH_RET_ACCESS "SC" 327 // ----------------------------------------------------------------------------- 328 // Field : PWM_CH2_CSR_DIVMODE 329 // Description : 0x0 -> Free-running counting at rate dictated by fractional 330 // divider 331 // 0x1 -> Fractional divider operation is gated by the PWM B pin. 332 // 0x2 -> Counter advances with each rising edge of the PWM B pin. 333 // 0x3 -> Counter advances with each falling edge of the PWM B 334 // pin. 335 #define PWM_CH2_CSR_DIVMODE_RESET 0x0 336 #define PWM_CH2_CSR_DIVMODE_BITS 0x00000030 337 #define PWM_CH2_CSR_DIVMODE_MSB 5 338 #define PWM_CH2_CSR_DIVMODE_LSB 4 339 #define PWM_CH2_CSR_DIVMODE_ACCESS "RW" 340 #define PWM_CH2_CSR_DIVMODE_VALUE_DIV 0x0 341 #define PWM_CH2_CSR_DIVMODE_VALUE_LEVEL 0x1 342 #define PWM_CH2_CSR_DIVMODE_VALUE_RISE 0x2 343 #define PWM_CH2_CSR_DIVMODE_VALUE_FALL 0x3 344 // ----------------------------------------------------------------------------- 345 // Field : PWM_CH2_CSR_B_INV 346 // Description : Invert output B 347 #define PWM_CH2_CSR_B_INV_RESET 0x0 348 #define PWM_CH2_CSR_B_INV_BITS 0x00000008 349 #define PWM_CH2_CSR_B_INV_MSB 3 350 #define PWM_CH2_CSR_B_INV_LSB 3 351 #define PWM_CH2_CSR_B_INV_ACCESS "RW" 352 // ----------------------------------------------------------------------------- 353 // Field : PWM_CH2_CSR_A_INV 354 // Description : Invert output A 355 #define PWM_CH2_CSR_A_INV_RESET 0x0 356 #define PWM_CH2_CSR_A_INV_BITS 0x00000004 357 #define PWM_CH2_CSR_A_INV_MSB 2 358 #define PWM_CH2_CSR_A_INV_LSB 2 359 #define PWM_CH2_CSR_A_INV_ACCESS "RW" 360 // ----------------------------------------------------------------------------- 361 // Field : PWM_CH2_CSR_PH_CORRECT 362 // Description : 1: Enable phase-correct modulation. 0: Trailing-edge 363 #define PWM_CH2_CSR_PH_CORRECT_RESET 0x0 364 #define PWM_CH2_CSR_PH_CORRECT_BITS 0x00000002 365 #define PWM_CH2_CSR_PH_CORRECT_MSB 1 366 #define PWM_CH2_CSR_PH_CORRECT_LSB 1 367 #define PWM_CH2_CSR_PH_CORRECT_ACCESS "RW" 368 // ----------------------------------------------------------------------------- 369 // Field : PWM_CH2_CSR_EN 370 // Description : Enable the PWM channel. 371 #define PWM_CH2_CSR_EN_RESET 0x0 372 #define PWM_CH2_CSR_EN_BITS 0x00000001 373 #define PWM_CH2_CSR_EN_MSB 0 374 #define PWM_CH2_CSR_EN_LSB 0 375 #define PWM_CH2_CSR_EN_ACCESS "RW" 376 // ============================================================================= 377 // Register : PWM_CH2_DIV 378 // Description : INT and FRAC form a fixed-point fractional number. 379 // Counting rate is system clock frequency divided by this number. 380 // Fractional division uses simple 1st-order sigma-delta. 381 #define PWM_CH2_DIV_OFFSET 0x0000002c 382 #define PWM_CH2_DIV_BITS 0x00000fff 383 #define PWM_CH2_DIV_RESET 0x00000010 384 // ----------------------------------------------------------------------------- 385 // Field : PWM_CH2_DIV_INT 386 // Description : None 387 #define PWM_CH2_DIV_INT_RESET 0x01 388 #define PWM_CH2_DIV_INT_BITS 0x00000ff0 389 #define PWM_CH2_DIV_INT_MSB 11 390 #define PWM_CH2_DIV_INT_LSB 4 391 #define PWM_CH2_DIV_INT_ACCESS "RW" 392 // ----------------------------------------------------------------------------- 393 // Field : PWM_CH2_DIV_FRAC 394 // Description : None 395 #define PWM_CH2_DIV_FRAC_RESET 0x0 396 #define PWM_CH2_DIV_FRAC_BITS 0x0000000f 397 #define PWM_CH2_DIV_FRAC_MSB 3 398 #define PWM_CH2_DIV_FRAC_LSB 0 399 #define PWM_CH2_DIV_FRAC_ACCESS "RW" 400 // ============================================================================= 401 // Register : PWM_CH2_CTR 402 // Description : Direct access to the PWM counter 403 #define PWM_CH2_CTR_OFFSET 0x00000030 404 #define PWM_CH2_CTR_BITS 0x0000ffff 405 #define PWM_CH2_CTR_RESET 0x00000000 406 #define PWM_CH2_CTR_MSB 15 407 #define PWM_CH2_CTR_LSB 0 408 #define PWM_CH2_CTR_ACCESS "RW" 409 // ============================================================================= 410 // Register : PWM_CH2_CC 411 // Description : Counter compare values 412 #define PWM_CH2_CC_OFFSET 0x00000034 413 #define PWM_CH2_CC_BITS 0xffffffff 414 #define PWM_CH2_CC_RESET 0x00000000 415 // ----------------------------------------------------------------------------- 416 // Field : PWM_CH2_CC_B 417 // Description : None 418 #define PWM_CH2_CC_B_RESET 0x0000 419 #define PWM_CH2_CC_B_BITS 0xffff0000 420 #define PWM_CH2_CC_B_MSB 31 421 #define PWM_CH2_CC_B_LSB 16 422 #define PWM_CH2_CC_B_ACCESS "RW" 423 // ----------------------------------------------------------------------------- 424 // Field : PWM_CH2_CC_A 425 // Description : None 426 #define PWM_CH2_CC_A_RESET 0x0000 427 #define PWM_CH2_CC_A_BITS 0x0000ffff 428 #define PWM_CH2_CC_A_MSB 15 429 #define PWM_CH2_CC_A_LSB 0 430 #define PWM_CH2_CC_A_ACCESS "RW" 431 // ============================================================================= 432 // Register : PWM_CH2_TOP 433 // Description : Counter wrap value 434 #define PWM_CH2_TOP_OFFSET 0x00000038 435 #define PWM_CH2_TOP_BITS 0x0000ffff 436 #define PWM_CH2_TOP_RESET 0x0000ffff 437 #define PWM_CH2_TOP_MSB 15 438 #define PWM_CH2_TOP_LSB 0 439 #define PWM_CH2_TOP_ACCESS "RW" 440 // ============================================================================= 441 // Register : PWM_CH3_CSR 442 // Description : Control and status register 443 #define PWM_CH3_CSR_OFFSET 0x0000003c 444 #define PWM_CH3_CSR_BITS 0x000000ff 445 #define PWM_CH3_CSR_RESET 0x00000000 446 // ----------------------------------------------------------------------------- 447 // Field : PWM_CH3_CSR_PH_ADV 448 // Description : Advance the phase of the counter by 1 count, while it is 449 // running. 450 // Self-clearing. Write a 1, and poll until low. Counter must be 451 // running 452 // at less than full speed (div_int + div_frac / 16 > 1) 453 #define PWM_CH3_CSR_PH_ADV_RESET 0x0 454 #define PWM_CH3_CSR_PH_ADV_BITS 0x00000080 455 #define PWM_CH3_CSR_PH_ADV_MSB 7 456 #define PWM_CH3_CSR_PH_ADV_LSB 7 457 #define PWM_CH3_CSR_PH_ADV_ACCESS "SC" 458 // ----------------------------------------------------------------------------- 459 // Field : PWM_CH3_CSR_PH_RET 460 // Description : Retard the phase of the counter by 1 count, while it is 461 // running. 462 // Self-clearing. Write a 1, and poll until low. Counter must be 463 // running. 464 #define PWM_CH3_CSR_PH_RET_RESET 0x0 465 #define PWM_CH3_CSR_PH_RET_BITS 0x00000040 466 #define PWM_CH3_CSR_PH_RET_MSB 6 467 #define PWM_CH3_CSR_PH_RET_LSB 6 468 #define PWM_CH3_CSR_PH_RET_ACCESS "SC" 469 // ----------------------------------------------------------------------------- 470 // Field : PWM_CH3_CSR_DIVMODE 471 // Description : 0x0 -> Free-running counting at rate dictated by fractional 472 // divider 473 // 0x1 -> Fractional divider operation is gated by the PWM B pin. 474 // 0x2 -> Counter advances with each rising edge of the PWM B pin. 475 // 0x3 -> Counter advances with each falling edge of the PWM B 476 // pin. 477 #define PWM_CH3_CSR_DIVMODE_RESET 0x0 478 #define PWM_CH3_CSR_DIVMODE_BITS 0x00000030 479 #define PWM_CH3_CSR_DIVMODE_MSB 5 480 #define PWM_CH3_CSR_DIVMODE_LSB 4 481 #define PWM_CH3_CSR_DIVMODE_ACCESS "RW" 482 #define PWM_CH3_CSR_DIVMODE_VALUE_DIV 0x0 483 #define PWM_CH3_CSR_DIVMODE_VALUE_LEVEL 0x1 484 #define PWM_CH3_CSR_DIVMODE_VALUE_RISE 0x2 485 #define PWM_CH3_CSR_DIVMODE_VALUE_FALL 0x3 486 // ----------------------------------------------------------------------------- 487 // Field : PWM_CH3_CSR_B_INV 488 // Description : Invert output B 489 #define PWM_CH3_CSR_B_INV_RESET 0x0 490 #define PWM_CH3_CSR_B_INV_BITS 0x00000008 491 #define PWM_CH3_CSR_B_INV_MSB 3 492 #define PWM_CH3_CSR_B_INV_LSB 3 493 #define PWM_CH3_CSR_B_INV_ACCESS "RW" 494 // ----------------------------------------------------------------------------- 495 // Field : PWM_CH3_CSR_A_INV 496 // Description : Invert output A 497 #define PWM_CH3_CSR_A_INV_RESET 0x0 498 #define PWM_CH3_CSR_A_INV_BITS 0x00000004 499 #define PWM_CH3_CSR_A_INV_MSB 2 500 #define PWM_CH3_CSR_A_INV_LSB 2 501 #define PWM_CH3_CSR_A_INV_ACCESS "RW" 502 // ----------------------------------------------------------------------------- 503 // Field : PWM_CH3_CSR_PH_CORRECT 504 // Description : 1: Enable phase-correct modulation. 0: Trailing-edge 505 #define PWM_CH3_CSR_PH_CORRECT_RESET 0x0 506 #define PWM_CH3_CSR_PH_CORRECT_BITS 0x00000002 507 #define PWM_CH3_CSR_PH_CORRECT_MSB 1 508 #define PWM_CH3_CSR_PH_CORRECT_LSB 1 509 #define PWM_CH3_CSR_PH_CORRECT_ACCESS "RW" 510 // ----------------------------------------------------------------------------- 511 // Field : PWM_CH3_CSR_EN 512 // Description : Enable the PWM channel. 513 #define PWM_CH3_CSR_EN_RESET 0x0 514 #define PWM_CH3_CSR_EN_BITS 0x00000001 515 #define PWM_CH3_CSR_EN_MSB 0 516 #define PWM_CH3_CSR_EN_LSB 0 517 #define PWM_CH3_CSR_EN_ACCESS "RW" 518 // ============================================================================= 519 // Register : PWM_CH3_DIV 520 // Description : INT and FRAC form a fixed-point fractional number. 521 // Counting rate is system clock frequency divided by this number. 522 // Fractional division uses simple 1st-order sigma-delta. 523 #define PWM_CH3_DIV_OFFSET 0x00000040 524 #define PWM_CH3_DIV_BITS 0x00000fff 525 #define PWM_CH3_DIV_RESET 0x00000010 526 // ----------------------------------------------------------------------------- 527 // Field : PWM_CH3_DIV_INT 528 // Description : None 529 #define PWM_CH3_DIV_INT_RESET 0x01 530 #define PWM_CH3_DIV_INT_BITS 0x00000ff0 531 #define PWM_CH3_DIV_INT_MSB 11 532 #define PWM_CH3_DIV_INT_LSB 4 533 #define PWM_CH3_DIV_INT_ACCESS "RW" 534 // ----------------------------------------------------------------------------- 535 // Field : PWM_CH3_DIV_FRAC 536 // Description : None 537 #define PWM_CH3_DIV_FRAC_RESET 0x0 538 #define PWM_CH3_DIV_FRAC_BITS 0x0000000f 539 #define PWM_CH3_DIV_FRAC_MSB 3 540 #define PWM_CH3_DIV_FRAC_LSB 0 541 #define PWM_CH3_DIV_FRAC_ACCESS "RW" 542 // ============================================================================= 543 // Register : PWM_CH3_CTR 544 // Description : Direct access to the PWM counter 545 #define PWM_CH3_CTR_OFFSET 0x00000044 546 #define PWM_CH3_CTR_BITS 0x0000ffff 547 #define PWM_CH3_CTR_RESET 0x00000000 548 #define PWM_CH3_CTR_MSB 15 549 #define PWM_CH3_CTR_LSB 0 550 #define PWM_CH3_CTR_ACCESS "RW" 551 // ============================================================================= 552 // Register : PWM_CH3_CC 553 // Description : Counter compare values 554 #define PWM_CH3_CC_OFFSET 0x00000048 555 #define PWM_CH3_CC_BITS 0xffffffff 556 #define PWM_CH3_CC_RESET 0x00000000 557 // ----------------------------------------------------------------------------- 558 // Field : PWM_CH3_CC_B 559 // Description : None 560 #define PWM_CH3_CC_B_RESET 0x0000 561 #define PWM_CH3_CC_B_BITS 0xffff0000 562 #define PWM_CH3_CC_B_MSB 31 563 #define PWM_CH3_CC_B_LSB 16 564 #define PWM_CH3_CC_B_ACCESS "RW" 565 // ----------------------------------------------------------------------------- 566 // Field : PWM_CH3_CC_A 567 // Description : None 568 #define PWM_CH3_CC_A_RESET 0x0000 569 #define PWM_CH3_CC_A_BITS 0x0000ffff 570 #define PWM_CH3_CC_A_MSB 15 571 #define PWM_CH3_CC_A_LSB 0 572 #define PWM_CH3_CC_A_ACCESS "RW" 573 // ============================================================================= 574 // Register : PWM_CH3_TOP 575 // Description : Counter wrap value 576 #define PWM_CH3_TOP_OFFSET 0x0000004c 577 #define PWM_CH3_TOP_BITS 0x0000ffff 578 #define PWM_CH3_TOP_RESET 0x0000ffff 579 #define PWM_CH3_TOP_MSB 15 580 #define PWM_CH3_TOP_LSB 0 581 #define PWM_CH3_TOP_ACCESS "RW" 582 // ============================================================================= 583 // Register : PWM_CH4_CSR 584 // Description : Control and status register 585 #define PWM_CH4_CSR_OFFSET 0x00000050 586 #define PWM_CH4_CSR_BITS 0x000000ff 587 #define PWM_CH4_CSR_RESET 0x00000000 588 // ----------------------------------------------------------------------------- 589 // Field : PWM_CH4_CSR_PH_ADV 590 // Description : Advance the phase of the counter by 1 count, while it is 591 // running. 592 // Self-clearing. Write a 1, and poll until low. Counter must be 593 // running 594 // at less than full speed (div_int + div_frac / 16 > 1) 595 #define PWM_CH4_CSR_PH_ADV_RESET 0x0 596 #define PWM_CH4_CSR_PH_ADV_BITS 0x00000080 597 #define PWM_CH4_CSR_PH_ADV_MSB 7 598 #define PWM_CH4_CSR_PH_ADV_LSB 7 599 #define PWM_CH4_CSR_PH_ADV_ACCESS "SC" 600 // ----------------------------------------------------------------------------- 601 // Field : PWM_CH4_CSR_PH_RET 602 // Description : Retard the phase of the counter by 1 count, while it is 603 // running. 604 // Self-clearing. Write a 1, and poll until low. Counter must be 605 // running. 606 #define PWM_CH4_CSR_PH_RET_RESET 0x0 607 #define PWM_CH4_CSR_PH_RET_BITS 0x00000040 608 #define PWM_CH4_CSR_PH_RET_MSB 6 609 #define PWM_CH4_CSR_PH_RET_LSB 6 610 #define PWM_CH4_CSR_PH_RET_ACCESS "SC" 611 // ----------------------------------------------------------------------------- 612 // Field : PWM_CH4_CSR_DIVMODE 613 // Description : 0x0 -> Free-running counting at rate dictated by fractional 614 // divider 615 // 0x1 -> Fractional divider operation is gated by the PWM B pin. 616 // 0x2 -> Counter advances with each rising edge of the PWM B pin. 617 // 0x3 -> Counter advances with each falling edge of the PWM B 618 // pin. 619 #define PWM_CH4_CSR_DIVMODE_RESET 0x0 620 #define PWM_CH4_CSR_DIVMODE_BITS 0x00000030 621 #define PWM_CH4_CSR_DIVMODE_MSB 5 622 #define PWM_CH4_CSR_DIVMODE_LSB 4 623 #define PWM_CH4_CSR_DIVMODE_ACCESS "RW" 624 #define PWM_CH4_CSR_DIVMODE_VALUE_DIV 0x0 625 #define PWM_CH4_CSR_DIVMODE_VALUE_LEVEL 0x1 626 #define PWM_CH4_CSR_DIVMODE_VALUE_RISE 0x2 627 #define PWM_CH4_CSR_DIVMODE_VALUE_FALL 0x3 628 // ----------------------------------------------------------------------------- 629 // Field : PWM_CH4_CSR_B_INV 630 // Description : Invert output B 631 #define PWM_CH4_CSR_B_INV_RESET 0x0 632 #define PWM_CH4_CSR_B_INV_BITS 0x00000008 633 #define PWM_CH4_CSR_B_INV_MSB 3 634 #define PWM_CH4_CSR_B_INV_LSB 3 635 #define PWM_CH4_CSR_B_INV_ACCESS "RW" 636 // ----------------------------------------------------------------------------- 637 // Field : PWM_CH4_CSR_A_INV 638 // Description : Invert output A 639 #define PWM_CH4_CSR_A_INV_RESET 0x0 640 #define PWM_CH4_CSR_A_INV_BITS 0x00000004 641 #define PWM_CH4_CSR_A_INV_MSB 2 642 #define PWM_CH4_CSR_A_INV_LSB 2 643 #define PWM_CH4_CSR_A_INV_ACCESS "RW" 644 // ----------------------------------------------------------------------------- 645 // Field : PWM_CH4_CSR_PH_CORRECT 646 // Description : 1: Enable phase-correct modulation. 0: Trailing-edge 647 #define PWM_CH4_CSR_PH_CORRECT_RESET 0x0 648 #define PWM_CH4_CSR_PH_CORRECT_BITS 0x00000002 649 #define PWM_CH4_CSR_PH_CORRECT_MSB 1 650 #define PWM_CH4_CSR_PH_CORRECT_LSB 1 651 #define PWM_CH4_CSR_PH_CORRECT_ACCESS "RW" 652 // ----------------------------------------------------------------------------- 653 // Field : PWM_CH4_CSR_EN 654 // Description : Enable the PWM channel. 655 #define PWM_CH4_CSR_EN_RESET 0x0 656 #define PWM_CH4_CSR_EN_BITS 0x00000001 657 #define PWM_CH4_CSR_EN_MSB 0 658 #define PWM_CH4_CSR_EN_LSB 0 659 #define PWM_CH4_CSR_EN_ACCESS "RW" 660 // ============================================================================= 661 // Register : PWM_CH4_DIV 662 // Description : INT and FRAC form a fixed-point fractional number. 663 // Counting rate is system clock frequency divided by this number. 664 // Fractional division uses simple 1st-order sigma-delta. 665 #define PWM_CH4_DIV_OFFSET 0x00000054 666 #define PWM_CH4_DIV_BITS 0x00000fff 667 #define PWM_CH4_DIV_RESET 0x00000010 668 // ----------------------------------------------------------------------------- 669 // Field : PWM_CH4_DIV_INT 670 // Description : None 671 #define PWM_CH4_DIV_INT_RESET 0x01 672 #define PWM_CH4_DIV_INT_BITS 0x00000ff0 673 #define PWM_CH4_DIV_INT_MSB 11 674 #define PWM_CH4_DIV_INT_LSB 4 675 #define PWM_CH4_DIV_INT_ACCESS "RW" 676 // ----------------------------------------------------------------------------- 677 // Field : PWM_CH4_DIV_FRAC 678 // Description : None 679 #define PWM_CH4_DIV_FRAC_RESET 0x0 680 #define PWM_CH4_DIV_FRAC_BITS 0x0000000f 681 #define PWM_CH4_DIV_FRAC_MSB 3 682 #define PWM_CH4_DIV_FRAC_LSB 0 683 #define PWM_CH4_DIV_FRAC_ACCESS "RW" 684 // ============================================================================= 685 // Register : PWM_CH4_CTR 686 // Description : Direct access to the PWM counter 687 #define PWM_CH4_CTR_OFFSET 0x00000058 688 #define PWM_CH4_CTR_BITS 0x0000ffff 689 #define PWM_CH4_CTR_RESET 0x00000000 690 #define PWM_CH4_CTR_MSB 15 691 #define PWM_CH4_CTR_LSB 0 692 #define PWM_CH4_CTR_ACCESS "RW" 693 // ============================================================================= 694 // Register : PWM_CH4_CC 695 // Description : Counter compare values 696 #define PWM_CH4_CC_OFFSET 0x0000005c 697 #define PWM_CH4_CC_BITS 0xffffffff 698 #define PWM_CH4_CC_RESET 0x00000000 699 // ----------------------------------------------------------------------------- 700 // Field : PWM_CH4_CC_B 701 // Description : None 702 #define PWM_CH4_CC_B_RESET 0x0000 703 #define PWM_CH4_CC_B_BITS 0xffff0000 704 #define PWM_CH4_CC_B_MSB 31 705 #define PWM_CH4_CC_B_LSB 16 706 #define PWM_CH4_CC_B_ACCESS "RW" 707 // ----------------------------------------------------------------------------- 708 // Field : PWM_CH4_CC_A 709 // Description : None 710 #define PWM_CH4_CC_A_RESET 0x0000 711 #define PWM_CH4_CC_A_BITS 0x0000ffff 712 #define PWM_CH4_CC_A_MSB 15 713 #define PWM_CH4_CC_A_LSB 0 714 #define PWM_CH4_CC_A_ACCESS "RW" 715 // ============================================================================= 716 // Register : PWM_CH4_TOP 717 // Description : Counter wrap value 718 #define PWM_CH4_TOP_OFFSET 0x00000060 719 #define PWM_CH4_TOP_BITS 0x0000ffff 720 #define PWM_CH4_TOP_RESET 0x0000ffff 721 #define PWM_CH4_TOP_MSB 15 722 #define PWM_CH4_TOP_LSB 0 723 #define PWM_CH4_TOP_ACCESS "RW" 724 // ============================================================================= 725 // Register : PWM_CH5_CSR 726 // Description : Control and status register 727 #define PWM_CH5_CSR_OFFSET 0x00000064 728 #define PWM_CH5_CSR_BITS 0x000000ff 729 #define PWM_CH5_CSR_RESET 0x00000000 730 // ----------------------------------------------------------------------------- 731 // Field : PWM_CH5_CSR_PH_ADV 732 // Description : Advance the phase of the counter by 1 count, while it is 733 // running. 734 // Self-clearing. Write a 1, and poll until low. Counter must be 735 // running 736 // at less than full speed (div_int + div_frac / 16 > 1) 737 #define PWM_CH5_CSR_PH_ADV_RESET 0x0 738 #define PWM_CH5_CSR_PH_ADV_BITS 0x00000080 739 #define PWM_CH5_CSR_PH_ADV_MSB 7 740 #define PWM_CH5_CSR_PH_ADV_LSB 7 741 #define PWM_CH5_CSR_PH_ADV_ACCESS "SC" 742 // ----------------------------------------------------------------------------- 743 // Field : PWM_CH5_CSR_PH_RET 744 // Description : Retard the phase of the counter by 1 count, while it is 745 // running. 746 // Self-clearing. Write a 1, and poll until low. Counter must be 747 // running. 748 #define PWM_CH5_CSR_PH_RET_RESET 0x0 749 #define PWM_CH5_CSR_PH_RET_BITS 0x00000040 750 #define PWM_CH5_CSR_PH_RET_MSB 6 751 #define PWM_CH5_CSR_PH_RET_LSB 6 752 #define PWM_CH5_CSR_PH_RET_ACCESS "SC" 753 // ----------------------------------------------------------------------------- 754 // Field : PWM_CH5_CSR_DIVMODE 755 // Description : 0x0 -> Free-running counting at rate dictated by fractional 756 // divider 757 // 0x1 -> Fractional divider operation is gated by the PWM B pin. 758 // 0x2 -> Counter advances with each rising edge of the PWM B pin. 759 // 0x3 -> Counter advances with each falling edge of the PWM B 760 // pin. 761 #define PWM_CH5_CSR_DIVMODE_RESET 0x0 762 #define PWM_CH5_CSR_DIVMODE_BITS 0x00000030 763 #define PWM_CH5_CSR_DIVMODE_MSB 5 764 #define PWM_CH5_CSR_DIVMODE_LSB 4 765 #define PWM_CH5_CSR_DIVMODE_ACCESS "RW" 766 #define PWM_CH5_CSR_DIVMODE_VALUE_DIV 0x0 767 #define PWM_CH5_CSR_DIVMODE_VALUE_LEVEL 0x1 768 #define PWM_CH5_CSR_DIVMODE_VALUE_RISE 0x2 769 #define PWM_CH5_CSR_DIVMODE_VALUE_FALL 0x3 770 // ----------------------------------------------------------------------------- 771 // Field : PWM_CH5_CSR_B_INV 772 // Description : Invert output B 773 #define PWM_CH5_CSR_B_INV_RESET 0x0 774 #define PWM_CH5_CSR_B_INV_BITS 0x00000008 775 #define PWM_CH5_CSR_B_INV_MSB 3 776 #define PWM_CH5_CSR_B_INV_LSB 3 777 #define PWM_CH5_CSR_B_INV_ACCESS "RW" 778 // ----------------------------------------------------------------------------- 779 // Field : PWM_CH5_CSR_A_INV 780 // Description : Invert output A 781 #define PWM_CH5_CSR_A_INV_RESET 0x0 782 #define PWM_CH5_CSR_A_INV_BITS 0x00000004 783 #define PWM_CH5_CSR_A_INV_MSB 2 784 #define PWM_CH5_CSR_A_INV_LSB 2 785 #define PWM_CH5_CSR_A_INV_ACCESS "RW" 786 // ----------------------------------------------------------------------------- 787 // Field : PWM_CH5_CSR_PH_CORRECT 788 // Description : 1: Enable phase-correct modulation. 0: Trailing-edge 789 #define PWM_CH5_CSR_PH_CORRECT_RESET 0x0 790 #define PWM_CH5_CSR_PH_CORRECT_BITS 0x00000002 791 #define PWM_CH5_CSR_PH_CORRECT_MSB 1 792 #define PWM_CH5_CSR_PH_CORRECT_LSB 1 793 #define PWM_CH5_CSR_PH_CORRECT_ACCESS "RW" 794 // ----------------------------------------------------------------------------- 795 // Field : PWM_CH5_CSR_EN 796 // Description : Enable the PWM channel. 797 #define PWM_CH5_CSR_EN_RESET 0x0 798 #define PWM_CH5_CSR_EN_BITS 0x00000001 799 #define PWM_CH5_CSR_EN_MSB 0 800 #define PWM_CH5_CSR_EN_LSB 0 801 #define PWM_CH5_CSR_EN_ACCESS "RW" 802 // ============================================================================= 803 // Register : PWM_CH5_DIV 804 // Description : INT and FRAC form a fixed-point fractional number. 805 // Counting rate is system clock frequency divided by this number. 806 // Fractional division uses simple 1st-order sigma-delta. 807 #define PWM_CH5_DIV_OFFSET 0x00000068 808 #define PWM_CH5_DIV_BITS 0x00000fff 809 #define PWM_CH5_DIV_RESET 0x00000010 810 // ----------------------------------------------------------------------------- 811 // Field : PWM_CH5_DIV_INT 812 // Description : None 813 #define PWM_CH5_DIV_INT_RESET 0x01 814 #define PWM_CH5_DIV_INT_BITS 0x00000ff0 815 #define PWM_CH5_DIV_INT_MSB 11 816 #define PWM_CH5_DIV_INT_LSB 4 817 #define PWM_CH5_DIV_INT_ACCESS "RW" 818 // ----------------------------------------------------------------------------- 819 // Field : PWM_CH5_DIV_FRAC 820 // Description : None 821 #define PWM_CH5_DIV_FRAC_RESET 0x0 822 #define PWM_CH5_DIV_FRAC_BITS 0x0000000f 823 #define PWM_CH5_DIV_FRAC_MSB 3 824 #define PWM_CH5_DIV_FRAC_LSB 0 825 #define PWM_CH5_DIV_FRAC_ACCESS "RW" 826 // ============================================================================= 827 // Register : PWM_CH5_CTR 828 // Description : Direct access to the PWM counter 829 #define PWM_CH5_CTR_OFFSET 0x0000006c 830 #define PWM_CH5_CTR_BITS 0x0000ffff 831 #define PWM_CH5_CTR_RESET 0x00000000 832 #define PWM_CH5_CTR_MSB 15 833 #define PWM_CH5_CTR_LSB 0 834 #define PWM_CH5_CTR_ACCESS "RW" 835 // ============================================================================= 836 // Register : PWM_CH5_CC 837 // Description : Counter compare values 838 #define PWM_CH5_CC_OFFSET 0x00000070 839 #define PWM_CH5_CC_BITS 0xffffffff 840 #define PWM_CH5_CC_RESET 0x00000000 841 // ----------------------------------------------------------------------------- 842 // Field : PWM_CH5_CC_B 843 // Description : None 844 #define PWM_CH5_CC_B_RESET 0x0000 845 #define PWM_CH5_CC_B_BITS 0xffff0000 846 #define PWM_CH5_CC_B_MSB 31 847 #define PWM_CH5_CC_B_LSB 16 848 #define PWM_CH5_CC_B_ACCESS "RW" 849 // ----------------------------------------------------------------------------- 850 // Field : PWM_CH5_CC_A 851 // Description : None 852 #define PWM_CH5_CC_A_RESET 0x0000 853 #define PWM_CH5_CC_A_BITS 0x0000ffff 854 #define PWM_CH5_CC_A_MSB 15 855 #define PWM_CH5_CC_A_LSB 0 856 #define PWM_CH5_CC_A_ACCESS "RW" 857 // ============================================================================= 858 // Register : PWM_CH5_TOP 859 // Description : Counter wrap value 860 #define PWM_CH5_TOP_OFFSET 0x00000074 861 #define PWM_CH5_TOP_BITS 0x0000ffff 862 #define PWM_CH5_TOP_RESET 0x0000ffff 863 #define PWM_CH5_TOP_MSB 15 864 #define PWM_CH5_TOP_LSB 0 865 #define PWM_CH5_TOP_ACCESS "RW" 866 // ============================================================================= 867 // Register : PWM_CH6_CSR 868 // Description : Control and status register 869 #define PWM_CH6_CSR_OFFSET 0x00000078 870 #define PWM_CH6_CSR_BITS 0x000000ff 871 #define PWM_CH6_CSR_RESET 0x00000000 872 // ----------------------------------------------------------------------------- 873 // Field : PWM_CH6_CSR_PH_ADV 874 // Description : Advance the phase of the counter by 1 count, while it is 875 // running. 876 // Self-clearing. Write a 1, and poll until low. Counter must be 877 // running 878 // at less than full speed (div_int + div_frac / 16 > 1) 879 #define PWM_CH6_CSR_PH_ADV_RESET 0x0 880 #define PWM_CH6_CSR_PH_ADV_BITS 0x00000080 881 #define PWM_CH6_CSR_PH_ADV_MSB 7 882 #define PWM_CH6_CSR_PH_ADV_LSB 7 883 #define PWM_CH6_CSR_PH_ADV_ACCESS "SC" 884 // ----------------------------------------------------------------------------- 885 // Field : PWM_CH6_CSR_PH_RET 886 // Description : Retard the phase of the counter by 1 count, while it is 887 // running. 888 // Self-clearing. Write a 1, and poll until low. Counter must be 889 // running. 890 #define PWM_CH6_CSR_PH_RET_RESET 0x0 891 #define PWM_CH6_CSR_PH_RET_BITS 0x00000040 892 #define PWM_CH6_CSR_PH_RET_MSB 6 893 #define PWM_CH6_CSR_PH_RET_LSB 6 894 #define PWM_CH6_CSR_PH_RET_ACCESS "SC" 895 // ----------------------------------------------------------------------------- 896 // Field : PWM_CH6_CSR_DIVMODE 897 // Description : 0x0 -> Free-running counting at rate dictated by fractional 898 // divider 899 // 0x1 -> Fractional divider operation is gated by the PWM B pin. 900 // 0x2 -> Counter advances with each rising edge of the PWM B pin. 901 // 0x3 -> Counter advances with each falling edge of the PWM B 902 // pin. 903 #define PWM_CH6_CSR_DIVMODE_RESET 0x0 904 #define PWM_CH6_CSR_DIVMODE_BITS 0x00000030 905 #define PWM_CH6_CSR_DIVMODE_MSB 5 906 #define PWM_CH6_CSR_DIVMODE_LSB 4 907 #define PWM_CH6_CSR_DIVMODE_ACCESS "RW" 908 #define PWM_CH6_CSR_DIVMODE_VALUE_DIV 0x0 909 #define PWM_CH6_CSR_DIVMODE_VALUE_LEVEL 0x1 910 #define PWM_CH6_CSR_DIVMODE_VALUE_RISE 0x2 911 #define PWM_CH6_CSR_DIVMODE_VALUE_FALL 0x3 912 // ----------------------------------------------------------------------------- 913 // Field : PWM_CH6_CSR_B_INV 914 // Description : Invert output B 915 #define PWM_CH6_CSR_B_INV_RESET 0x0 916 #define PWM_CH6_CSR_B_INV_BITS 0x00000008 917 #define PWM_CH6_CSR_B_INV_MSB 3 918 #define PWM_CH6_CSR_B_INV_LSB 3 919 #define PWM_CH6_CSR_B_INV_ACCESS "RW" 920 // ----------------------------------------------------------------------------- 921 // Field : PWM_CH6_CSR_A_INV 922 // Description : Invert output A 923 #define PWM_CH6_CSR_A_INV_RESET 0x0 924 #define PWM_CH6_CSR_A_INV_BITS 0x00000004 925 #define PWM_CH6_CSR_A_INV_MSB 2 926 #define PWM_CH6_CSR_A_INV_LSB 2 927 #define PWM_CH6_CSR_A_INV_ACCESS "RW" 928 // ----------------------------------------------------------------------------- 929 // Field : PWM_CH6_CSR_PH_CORRECT 930 // Description : 1: Enable phase-correct modulation. 0: Trailing-edge 931 #define PWM_CH6_CSR_PH_CORRECT_RESET 0x0 932 #define PWM_CH6_CSR_PH_CORRECT_BITS 0x00000002 933 #define PWM_CH6_CSR_PH_CORRECT_MSB 1 934 #define PWM_CH6_CSR_PH_CORRECT_LSB 1 935 #define PWM_CH6_CSR_PH_CORRECT_ACCESS "RW" 936 // ----------------------------------------------------------------------------- 937 // Field : PWM_CH6_CSR_EN 938 // Description : Enable the PWM channel. 939 #define PWM_CH6_CSR_EN_RESET 0x0 940 #define PWM_CH6_CSR_EN_BITS 0x00000001 941 #define PWM_CH6_CSR_EN_MSB 0 942 #define PWM_CH6_CSR_EN_LSB 0 943 #define PWM_CH6_CSR_EN_ACCESS "RW" 944 // ============================================================================= 945 // Register : PWM_CH6_DIV 946 // Description : INT and FRAC form a fixed-point fractional number. 947 // Counting rate is system clock frequency divided by this number. 948 // Fractional division uses simple 1st-order sigma-delta. 949 #define PWM_CH6_DIV_OFFSET 0x0000007c 950 #define PWM_CH6_DIV_BITS 0x00000fff 951 #define PWM_CH6_DIV_RESET 0x00000010 952 // ----------------------------------------------------------------------------- 953 // Field : PWM_CH6_DIV_INT 954 // Description : None 955 #define PWM_CH6_DIV_INT_RESET 0x01 956 #define PWM_CH6_DIV_INT_BITS 0x00000ff0 957 #define PWM_CH6_DIV_INT_MSB 11 958 #define PWM_CH6_DIV_INT_LSB 4 959 #define PWM_CH6_DIV_INT_ACCESS "RW" 960 // ----------------------------------------------------------------------------- 961 // Field : PWM_CH6_DIV_FRAC 962 // Description : None 963 #define PWM_CH6_DIV_FRAC_RESET 0x0 964 #define PWM_CH6_DIV_FRAC_BITS 0x0000000f 965 #define PWM_CH6_DIV_FRAC_MSB 3 966 #define PWM_CH6_DIV_FRAC_LSB 0 967 #define PWM_CH6_DIV_FRAC_ACCESS "RW" 968 // ============================================================================= 969 // Register : PWM_CH6_CTR 970 // Description : Direct access to the PWM counter 971 #define PWM_CH6_CTR_OFFSET 0x00000080 972 #define PWM_CH6_CTR_BITS 0x0000ffff 973 #define PWM_CH6_CTR_RESET 0x00000000 974 #define PWM_CH6_CTR_MSB 15 975 #define PWM_CH6_CTR_LSB 0 976 #define PWM_CH6_CTR_ACCESS "RW" 977 // ============================================================================= 978 // Register : PWM_CH6_CC 979 // Description : Counter compare values 980 #define PWM_CH6_CC_OFFSET 0x00000084 981 #define PWM_CH6_CC_BITS 0xffffffff 982 #define PWM_CH6_CC_RESET 0x00000000 983 // ----------------------------------------------------------------------------- 984 // Field : PWM_CH6_CC_B 985 // Description : None 986 #define PWM_CH6_CC_B_RESET 0x0000 987 #define PWM_CH6_CC_B_BITS 0xffff0000 988 #define PWM_CH6_CC_B_MSB 31 989 #define PWM_CH6_CC_B_LSB 16 990 #define PWM_CH6_CC_B_ACCESS "RW" 991 // ----------------------------------------------------------------------------- 992 // Field : PWM_CH6_CC_A 993 // Description : None 994 #define PWM_CH6_CC_A_RESET 0x0000 995 #define PWM_CH6_CC_A_BITS 0x0000ffff 996 #define PWM_CH6_CC_A_MSB 15 997 #define PWM_CH6_CC_A_LSB 0 998 #define PWM_CH6_CC_A_ACCESS "RW" 999 // ============================================================================= 1000 // Register : PWM_CH6_TOP 1001 // Description : Counter wrap value 1002 #define PWM_CH6_TOP_OFFSET 0x00000088 1003 #define PWM_CH6_TOP_BITS 0x0000ffff 1004 #define PWM_CH6_TOP_RESET 0x0000ffff 1005 #define PWM_CH6_TOP_MSB 15 1006 #define PWM_CH6_TOP_LSB 0 1007 #define PWM_CH6_TOP_ACCESS "RW" 1008 // ============================================================================= 1009 // Register : PWM_CH7_CSR 1010 // Description : Control and status register 1011 #define PWM_CH7_CSR_OFFSET 0x0000008c 1012 #define PWM_CH7_CSR_BITS 0x000000ff 1013 #define PWM_CH7_CSR_RESET 0x00000000 1014 // ----------------------------------------------------------------------------- 1015 // Field : PWM_CH7_CSR_PH_ADV 1016 // Description : Advance the phase of the counter by 1 count, while it is 1017 // running. 1018 // Self-clearing. Write a 1, and poll until low. Counter must be 1019 // running 1020 // at less than full speed (div_int + div_frac / 16 > 1) 1021 #define PWM_CH7_CSR_PH_ADV_RESET 0x0 1022 #define PWM_CH7_CSR_PH_ADV_BITS 0x00000080 1023 #define PWM_CH7_CSR_PH_ADV_MSB 7 1024 #define PWM_CH7_CSR_PH_ADV_LSB 7 1025 #define PWM_CH7_CSR_PH_ADV_ACCESS "SC" 1026 // ----------------------------------------------------------------------------- 1027 // Field : PWM_CH7_CSR_PH_RET 1028 // Description : Retard the phase of the counter by 1 count, while it is 1029 // running. 1030 // Self-clearing. Write a 1, and poll until low. Counter must be 1031 // running. 1032 #define PWM_CH7_CSR_PH_RET_RESET 0x0 1033 #define PWM_CH7_CSR_PH_RET_BITS 0x00000040 1034 #define PWM_CH7_CSR_PH_RET_MSB 6 1035 #define PWM_CH7_CSR_PH_RET_LSB 6 1036 #define PWM_CH7_CSR_PH_RET_ACCESS "SC" 1037 // ----------------------------------------------------------------------------- 1038 // Field : PWM_CH7_CSR_DIVMODE 1039 // Description : 0x0 -> Free-running counting at rate dictated by fractional 1040 // divider 1041 // 0x1 -> Fractional divider operation is gated by the PWM B pin. 1042 // 0x2 -> Counter advances with each rising edge of the PWM B pin. 1043 // 0x3 -> Counter advances with each falling edge of the PWM B 1044 // pin. 1045 #define PWM_CH7_CSR_DIVMODE_RESET 0x0 1046 #define PWM_CH7_CSR_DIVMODE_BITS 0x00000030 1047 #define PWM_CH7_CSR_DIVMODE_MSB 5 1048 #define PWM_CH7_CSR_DIVMODE_LSB 4 1049 #define PWM_CH7_CSR_DIVMODE_ACCESS "RW" 1050 #define PWM_CH7_CSR_DIVMODE_VALUE_DIV 0x0 1051 #define PWM_CH7_CSR_DIVMODE_VALUE_LEVEL 0x1 1052 #define PWM_CH7_CSR_DIVMODE_VALUE_RISE 0x2 1053 #define PWM_CH7_CSR_DIVMODE_VALUE_FALL 0x3 1054 // ----------------------------------------------------------------------------- 1055 // Field : PWM_CH7_CSR_B_INV 1056 // Description : Invert output B 1057 #define PWM_CH7_CSR_B_INV_RESET 0x0 1058 #define PWM_CH7_CSR_B_INV_BITS 0x00000008 1059 #define PWM_CH7_CSR_B_INV_MSB 3 1060 #define PWM_CH7_CSR_B_INV_LSB 3 1061 #define PWM_CH7_CSR_B_INV_ACCESS "RW" 1062 // ----------------------------------------------------------------------------- 1063 // Field : PWM_CH7_CSR_A_INV 1064 // Description : Invert output A 1065 #define PWM_CH7_CSR_A_INV_RESET 0x0 1066 #define PWM_CH7_CSR_A_INV_BITS 0x00000004 1067 #define PWM_CH7_CSR_A_INV_MSB 2 1068 #define PWM_CH7_CSR_A_INV_LSB 2 1069 #define PWM_CH7_CSR_A_INV_ACCESS "RW" 1070 // ----------------------------------------------------------------------------- 1071 // Field : PWM_CH7_CSR_PH_CORRECT 1072 // Description : 1: Enable phase-correct modulation. 0: Trailing-edge 1073 #define PWM_CH7_CSR_PH_CORRECT_RESET 0x0 1074 #define PWM_CH7_CSR_PH_CORRECT_BITS 0x00000002 1075 #define PWM_CH7_CSR_PH_CORRECT_MSB 1 1076 #define PWM_CH7_CSR_PH_CORRECT_LSB 1 1077 #define PWM_CH7_CSR_PH_CORRECT_ACCESS "RW" 1078 // ----------------------------------------------------------------------------- 1079 // Field : PWM_CH7_CSR_EN 1080 // Description : Enable the PWM channel. 1081 #define PWM_CH7_CSR_EN_RESET 0x0 1082 #define PWM_CH7_CSR_EN_BITS 0x00000001 1083 #define PWM_CH7_CSR_EN_MSB 0 1084 #define PWM_CH7_CSR_EN_LSB 0 1085 #define PWM_CH7_CSR_EN_ACCESS "RW" 1086 // ============================================================================= 1087 // Register : PWM_CH7_DIV 1088 // Description : INT and FRAC form a fixed-point fractional number. 1089 // Counting rate is system clock frequency divided by this number. 1090 // Fractional division uses simple 1st-order sigma-delta. 1091 #define PWM_CH7_DIV_OFFSET 0x00000090 1092 #define PWM_CH7_DIV_BITS 0x00000fff 1093 #define PWM_CH7_DIV_RESET 0x00000010 1094 // ----------------------------------------------------------------------------- 1095 // Field : PWM_CH7_DIV_INT 1096 // Description : None 1097 #define PWM_CH7_DIV_INT_RESET 0x01 1098 #define PWM_CH7_DIV_INT_BITS 0x00000ff0 1099 #define PWM_CH7_DIV_INT_MSB 11 1100 #define PWM_CH7_DIV_INT_LSB 4 1101 #define PWM_CH7_DIV_INT_ACCESS "RW" 1102 // ----------------------------------------------------------------------------- 1103 // Field : PWM_CH7_DIV_FRAC 1104 // Description : None 1105 #define PWM_CH7_DIV_FRAC_RESET 0x0 1106 #define PWM_CH7_DIV_FRAC_BITS 0x0000000f 1107 #define PWM_CH7_DIV_FRAC_MSB 3 1108 #define PWM_CH7_DIV_FRAC_LSB 0 1109 #define PWM_CH7_DIV_FRAC_ACCESS "RW" 1110 // ============================================================================= 1111 // Register : PWM_CH7_CTR 1112 // Description : Direct access to the PWM counter 1113 #define PWM_CH7_CTR_OFFSET 0x00000094 1114 #define PWM_CH7_CTR_BITS 0x0000ffff 1115 #define PWM_CH7_CTR_RESET 0x00000000 1116 #define PWM_CH7_CTR_MSB 15 1117 #define PWM_CH7_CTR_LSB 0 1118 #define PWM_CH7_CTR_ACCESS "RW" 1119 // ============================================================================= 1120 // Register : PWM_CH7_CC 1121 // Description : Counter compare values 1122 #define PWM_CH7_CC_OFFSET 0x00000098 1123 #define PWM_CH7_CC_BITS 0xffffffff 1124 #define PWM_CH7_CC_RESET 0x00000000 1125 // ----------------------------------------------------------------------------- 1126 // Field : PWM_CH7_CC_B 1127 // Description : None 1128 #define PWM_CH7_CC_B_RESET 0x0000 1129 #define PWM_CH7_CC_B_BITS 0xffff0000 1130 #define PWM_CH7_CC_B_MSB 31 1131 #define PWM_CH7_CC_B_LSB 16 1132 #define PWM_CH7_CC_B_ACCESS "RW" 1133 // ----------------------------------------------------------------------------- 1134 // Field : PWM_CH7_CC_A 1135 // Description : None 1136 #define PWM_CH7_CC_A_RESET 0x0000 1137 #define PWM_CH7_CC_A_BITS 0x0000ffff 1138 #define PWM_CH7_CC_A_MSB 15 1139 #define PWM_CH7_CC_A_LSB 0 1140 #define PWM_CH7_CC_A_ACCESS "RW" 1141 // ============================================================================= 1142 // Register : PWM_CH7_TOP 1143 // Description : Counter wrap value 1144 #define PWM_CH7_TOP_OFFSET 0x0000009c 1145 #define PWM_CH7_TOP_BITS 0x0000ffff 1146 #define PWM_CH7_TOP_RESET 0x0000ffff 1147 #define PWM_CH7_TOP_MSB 15 1148 #define PWM_CH7_TOP_LSB 0 1149 #define PWM_CH7_TOP_ACCESS "RW" 1150 // ============================================================================= 1151 // Register : PWM_EN 1152 // Description : This register aliases the CSR_EN bits for all channels. 1153 // Writing to this register allows multiple channels to be enabled 1154 // or disabled simultaneously, so they can run in perfect sync. 1155 // For each channel, there is only one physical EN register bit, 1156 // which can be accessed through here or CHx_CSR. 1157 #define PWM_EN_OFFSET 0x000000a0 1158 #define PWM_EN_BITS 0x000000ff 1159 #define PWM_EN_RESET 0x00000000 1160 // ----------------------------------------------------------------------------- 1161 // Field : PWM_EN_CH7 1162 // Description : None 1163 #define PWM_EN_CH7_RESET 0x0 1164 #define PWM_EN_CH7_BITS 0x00000080 1165 #define PWM_EN_CH7_MSB 7 1166 #define PWM_EN_CH7_LSB 7 1167 #define PWM_EN_CH7_ACCESS "RW" 1168 // ----------------------------------------------------------------------------- 1169 // Field : PWM_EN_CH6 1170 // Description : None 1171 #define PWM_EN_CH6_RESET 0x0 1172 #define PWM_EN_CH6_BITS 0x00000040 1173 #define PWM_EN_CH6_MSB 6 1174 #define PWM_EN_CH6_LSB 6 1175 #define PWM_EN_CH6_ACCESS "RW" 1176 // ----------------------------------------------------------------------------- 1177 // Field : PWM_EN_CH5 1178 // Description : None 1179 #define PWM_EN_CH5_RESET 0x0 1180 #define PWM_EN_CH5_BITS 0x00000020 1181 #define PWM_EN_CH5_MSB 5 1182 #define PWM_EN_CH5_LSB 5 1183 #define PWM_EN_CH5_ACCESS "RW" 1184 // ----------------------------------------------------------------------------- 1185 // Field : PWM_EN_CH4 1186 // Description : None 1187 #define PWM_EN_CH4_RESET 0x0 1188 #define PWM_EN_CH4_BITS 0x00000010 1189 #define PWM_EN_CH4_MSB 4 1190 #define PWM_EN_CH4_LSB 4 1191 #define PWM_EN_CH4_ACCESS "RW" 1192 // ----------------------------------------------------------------------------- 1193 // Field : PWM_EN_CH3 1194 // Description : None 1195 #define PWM_EN_CH3_RESET 0x0 1196 #define PWM_EN_CH3_BITS 0x00000008 1197 #define PWM_EN_CH3_MSB 3 1198 #define PWM_EN_CH3_LSB 3 1199 #define PWM_EN_CH3_ACCESS "RW" 1200 // ----------------------------------------------------------------------------- 1201 // Field : PWM_EN_CH2 1202 // Description : None 1203 #define PWM_EN_CH2_RESET 0x0 1204 #define PWM_EN_CH2_BITS 0x00000004 1205 #define PWM_EN_CH2_MSB 2 1206 #define PWM_EN_CH2_LSB 2 1207 #define PWM_EN_CH2_ACCESS "RW" 1208 // ----------------------------------------------------------------------------- 1209 // Field : PWM_EN_CH1 1210 // Description : None 1211 #define PWM_EN_CH1_RESET 0x0 1212 #define PWM_EN_CH1_BITS 0x00000002 1213 #define PWM_EN_CH1_MSB 1 1214 #define PWM_EN_CH1_LSB 1 1215 #define PWM_EN_CH1_ACCESS "RW" 1216 // ----------------------------------------------------------------------------- 1217 // Field : PWM_EN_CH0 1218 // Description : None 1219 #define PWM_EN_CH0_RESET 0x0 1220 #define PWM_EN_CH0_BITS 0x00000001 1221 #define PWM_EN_CH0_MSB 0 1222 #define PWM_EN_CH0_LSB 0 1223 #define PWM_EN_CH0_ACCESS "RW" 1224 // ============================================================================= 1225 // Register : PWM_INTR 1226 // Description : Raw Interrupts 1227 #define PWM_INTR_OFFSET 0x000000a4 1228 #define PWM_INTR_BITS 0x000000ff 1229 #define PWM_INTR_RESET 0x00000000 1230 // ----------------------------------------------------------------------------- 1231 // Field : PWM_INTR_CH7 1232 // Description : None 1233 #define PWM_INTR_CH7_RESET 0x0 1234 #define PWM_INTR_CH7_BITS 0x00000080 1235 #define PWM_INTR_CH7_MSB 7 1236 #define PWM_INTR_CH7_LSB 7 1237 #define PWM_INTR_CH7_ACCESS "WC" 1238 // ----------------------------------------------------------------------------- 1239 // Field : PWM_INTR_CH6 1240 // Description : None 1241 #define PWM_INTR_CH6_RESET 0x0 1242 #define PWM_INTR_CH6_BITS 0x00000040 1243 #define PWM_INTR_CH6_MSB 6 1244 #define PWM_INTR_CH6_LSB 6 1245 #define PWM_INTR_CH6_ACCESS "WC" 1246 // ----------------------------------------------------------------------------- 1247 // Field : PWM_INTR_CH5 1248 // Description : None 1249 #define PWM_INTR_CH5_RESET 0x0 1250 #define PWM_INTR_CH5_BITS 0x00000020 1251 #define PWM_INTR_CH5_MSB 5 1252 #define PWM_INTR_CH5_LSB 5 1253 #define PWM_INTR_CH5_ACCESS "WC" 1254 // ----------------------------------------------------------------------------- 1255 // Field : PWM_INTR_CH4 1256 // Description : None 1257 #define PWM_INTR_CH4_RESET 0x0 1258 #define PWM_INTR_CH4_BITS 0x00000010 1259 #define PWM_INTR_CH4_MSB 4 1260 #define PWM_INTR_CH4_LSB 4 1261 #define PWM_INTR_CH4_ACCESS "WC" 1262 // ----------------------------------------------------------------------------- 1263 // Field : PWM_INTR_CH3 1264 // Description : None 1265 #define PWM_INTR_CH3_RESET 0x0 1266 #define PWM_INTR_CH3_BITS 0x00000008 1267 #define PWM_INTR_CH3_MSB 3 1268 #define PWM_INTR_CH3_LSB 3 1269 #define PWM_INTR_CH3_ACCESS "WC" 1270 // ----------------------------------------------------------------------------- 1271 // Field : PWM_INTR_CH2 1272 // Description : None 1273 #define PWM_INTR_CH2_RESET 0x0 1274 #define PWM_INTR_CH2_BITS 0x00000004 1275 #define PWM_INTR_CH2_MSB 2 1276 #define PWM_INTR_CH2_LSB 2 1277 #define PWM_INTR_CH2_ACCESS "WC" 1278 // ----------------------------------------------------------------------------- 1279 // Field : PWM_INTR_CH1 1280 // Description : None 1281 #define PWM_INTR_CH1_RESET 0x0 1282 #define PWM_INTR_CH1_BITS 0x00000002 1283 #define PWM_INTR_CH1_MSB 1 1284 #define PWM_INTR_CH1_LSB 1 1285 #define PWM_INTR_CH1_ACCESS "WC" 1286 // ----------------------------------------------------------------------------- 1287 // Field : PWM_INTR_CH0 1288 // Description : None 1289 #define PWM_INTR_CH0_RESET 0x0 1290 #define PWM_INTR_CH0_BITS 0x00000001 1291 #define PWM_INTR_CH0_MSB 0 1292 #define PWM_INTR_CH0_LSB 0 1293 #define PWM_INTR_CH0_ACCESS "WC" 1294 // ============================================================================= 1295 // Register : PWM_INTE 1296 // Description : Interrupt Enable 1297 #define PWM_INTE_OFFSET 0x000000a8 1298 #define PWM_INTE_BITS 0x000000ff 1299 #define PWM_INTE_RESET 0x00000000 1300 // ----------------------------------------------------------------------------- 1301 // Field : PWM_INTE_CH7 1302 // Description : None 1303 #define PWM_INTE_CH7_RESET 0x0 1304 #define PWM_INTE_CH7_BITS 0x00000080 1305 #define PWM_INTE_CH7_MSB 7 1306 #define PWM_INTE_CH7_LSB 7 1307 #define PWM_INTE_CH7_ACCESS "RW" 1308 // ----------------------------------------------------------------------------- 1309 // Field : PWM_INTE_CH6 1310 // Description : None 1311 #define PWM_INTE_CH6_RESET 0x0 1312 #define PWM_INTE_CH6_BITS 0x00000040 1313 #define PWM_INTE_CH6_MSB 6 1314 #define PWM_INTE_CH6_LSB 6 1315 #define PWM_INTE_CH6_ACCESS "RW" 1316 // ----------------------------------------------------------------------------- 1317 // Field : PWM_INTE_CH5 1318 // Description : None 1319 #define PWM_INTE_CH5_RESET 0x0 1320 #define PWM_INTE_CH5_BITS 0x00000020 1321 #define PWM_INTE_CH5_MSB 5 1322 #define PWM_INTE_CH5_LSB 5 1323 #define PWM_INTE_CH5_ACCESS "RW" 1324 // ----------------------------------------------------------------------------- 1325 // Field : PWM_INTE_CH4 1326 // Description : None 1327 #define PWM_INTE_CH4_RESET 0x0 1328 #define PWM_INTE_CH4_BITS 0x00000010 1329 #define PWM_INTE_CH4_MSB 4 1330 #define PWM_INTE_CH4_LSB 4 1331 #define PWM_INTE_CH4_ACCESS "RW" 1332 // ----------------------------------------------------------------------------- 1333 // Field : PWM_INTE_CH3 1334 // Description : None 1335 #define PWM_INTE_CH3_RESET 0x0 1336 #define PWM_INTE_CH3_BITS 0x00000008 1337 #define PWM_INTE_CH3_MSB 3 1338 #define PWM_INTE_CH3_LSB 3 1339 #define PWM_INTE_CH3_ACCESS "RW" 1340 // ----------------------------------------------------------------------------- 1341 // Field : PWM_INTE_CH2 1342 // Description : None 1343 #define PWM_INTE_CH2_RESET 0x0 1344 #define PWM_INTE_CH2_BITS 0x00000004 1345 #define PWM_INTE_CH2_MSB 2 1346 #define PWM_INTE_CH2_LSB 2 1347 #define PWM_INTE_CH2_ACCESS "RW" 1348 // ----------------------------------------------------------------------------- 1349 // Field : PWM_INTE_CH1 1350 // Description : None 1351 #define PWM_INTE_CH1_RESET 0x0 1352 #define PWM_INTE_CH1_BITS 0x00000002 1353 #define PWM_INTE_CH1_MSB 1 1354 #define PWM_INTE_CH1_LSB 1 1355 #define PWM_INTE_CH1_ACCESS "RW" 1356 // ----------------------------------------------------------------------------- 1357 // Field : PWM_INTE_CH0 1358 // Description : None 1359 #define PWM_INTE_CH0_RESET 0x0 1360 #define PWM_INTE_CH0_BITS 0x00000001 1361 #define PWM_INTE_CH0_MSB 0 1362 #define PWM_INTE_CH0_LSB 0 1363 #define PWM_INTE_CH0_ACCESS "RW" 1364 // ============================================================================= 1365 // Register : PWM_INTF 1366 // Description : Interrupt Force 1367 #define PWM_INTF_OFFSET 0x000000ac 1368 #define PWM_INTF_BITS 0x000000ff 1369 #define PWM_INTF_RESET 0x00000000 1370 // ----------------------------------------------------------------------------- 1371 // Field : PWM_INTF_CH7 1372 // Description : None 1373 #define PWM_INTF_CH7_RESET 0x0 1374 #define PWM_INTF_CH7_BITS 0x00000080 1375 #define PWM_INTF_CH7_MSB 7 1376 #define PWM_INTF_CH7_LSB 7 1377 #define PWM_INTF_CH7_ACCESS "RW" 1378 // ----------------------------------------------------------------------------- 1379 // Field : PWM_INTF_CH6 1380 // Description : None 1381 #define PWM_INTF_CH6_RESET 0x0 1382 #define PWM_INTF_CH6_BITS 0x00000040 1383 #define PWM_INTF_CH6_MSB 6 1384 #define PWM_INTF_CH6_LSB 6 1385 #define PWM_INTF_CH6_ACCESS "RW" 1386 // ----------------------------------------------------------------------------- 1387 // Field : PWM_INTF_CH5 1388 // Description : None 1389 #define PWM_INTF_CH5_RESET 0x0 1390 #define PWM_INTF_CH5_BITS 0x00000020 1391 #define PWM_INTF_CH5_MSB 5 1392 #define PWM_INTF_CH5_LSB 5 1393 #define PWM_INTF_CH5_ACCESS "RW" 1394 // ----------------------------------------------------------------------------- 1395 // Field : PWM_INTF_CH4 1396 // Description : None 1397 #define PWM_INTF_CH4_RESET 0x0 1398 #define PWM_INTF_CH4_BITS 0x00000010 1399 #define PWM_INTF_CH4_MSB 4 1400 #define PWM_INTF_CH4_LSB 4 1401 #define PWM_INTF_CH4_ACCESS "RW" 1402 // ----------------------------------------------------------------------------- 1403 // Field : PWM_INTF_CH3 1404 // Description : None 1405 #define PWM_INTF_CH3_RESET 0x0 1406 #define PWM_INTF_CH3_BITS 0x00000008 1407 #define PWM_INTF_CH3_MSB 3 1408 #define PWM_INTF_CH3_LSB 3 1409 #define PWM_INTF_CH3_ACCESS "RW" 1410 // ----------------------------------------------------------------------------- 1411 // Field : PWM_INTF_CH2 1412 // Description : None 1413 #define PWM_INTF_CH2_RESET 0x0 1414 #define PWM_INTF_CH2_BITS 0x00000004 1415 #define PWM_INTF_CH2_MSB 2 1416 #define PWM_INTF_CH2_LSB 2 1417 #define PWM_INTF_CH2_ACCESS "RW" 1418 // ----------------------------------------------------------------------------- 1419 // Field : PWM_INTF_CH1 1420 // Description : None 1421 #define PWM_INTF_CH1_RESET 0x0 1422 #define PWM_INTF_CH1_BITS 0x00000002 1423 #define PWM_INTF_CH1_MSB 1 1424 #define PWM_INTF_CH1_LSB 1 1425 #define PWM_INTF_CH1_ACCESS "RW" 1426 // ----------------------------------------------------------------------------- 1427 // Field : PWM_INTF_CH0 1428 // Description : None 1429 #define PWM_INTF_CH0_RESET 0x0 1430 #define PWM_INTF_CH0_BITS 0x00000001 1431 #define PWM_INTF_CH0_MSB 0 1432 #define PWM_INTF_CH0_LSB 0 1433 #define PWM_INTF_CH0_ACCESS "RW" 1434 // ============================================================================= 1435 // Register : PWM_INTS 1436 // Description : Interrupt status after masking & forcing 1437 #define PWM_INTS_OFFSET 0x000000b0 1438 #define PWM_INTS_BITS 0x000000ff 1439 #define PWM_INTS_RESET 0x00000000 1440 // ----------------------------------------------------------------------------- 1441 // Field : PWM_INTS_CH7 1442 // Description : None 1443 #define PWM_INTS_CH7_RESET 0x0 1444 #define PWM_INTS_CH7_BITS 0x00000080 1445 #define PWM_INTS_CH7_MSB 7 1446 #define PWM_INTS_CH7_LSB 7 1447 #define PWM_INTS_CH7_ACCESS "RO" 1448 // ----------------------------------------------------------------------------- 1449 // Field : PWM_INTS_CH6 1450 // Description : None 1451 #define PWM_INTS_CH6_RESET 0x0 1452 #define PWM_INTS_CH6_BITS 0x00000040 1453 #define PWM_INTS_CH6_MSB 6 1454 #define PWM_INTS_CH6_LSB 6 1455 #define PWM_INTS_CH6_ACCESS "RO" 1456 // ----------------------------------------------------------------------------- 1457 // Field : PWM_INTS_CH5 1458 // Description : None 1459 #define PWM_INTS_CH5_RESET 0x0 1460 #define PWM_INTS_CH5_BITS 0x00000020 1461 #define PWM_INTS_CH5_MSB 5 1462 #define PWM_INTS_CH5_LSB 5 1463 #define PWM_INTS_CH5_ACCESS "RO" 1464 // ----------------------------------------------------------------------------- 1465 // Field : PWM_INTS_CH4 1466 // Description : None 1467 #define PWM_INTS_CH4_RESET 0x0 1468 #define PWM_INTS_CH4_BITS 0x00000010 1469 #define PWM_INTS_CH4_MSB 4 1470 #define PWM_INTS_CH4_LSB 4 1471 #define PWM_INTS_CH4_ACCESS "RO" 1472 // ----------------------------------------------------------------------------- 1473 // Field : PWM_INTS_CH3 1474 // Description : None 1475 #define PWM_INTS_CH3_RESET 0x0 1476 #define PWM_INTS_CH3_BITS 0x00000008 1477 #define PWM_INTS_CH3_MSB 3 1478 #define PWM_INTS_CH3_LSB 3 1479 #define PWM_INTS_CH3_ACCESS "RO" 1480 // ----------------------------------------------------------------------------- 1481 // Field : PWM_INTS_CH2 1482 // Description : None 1483 #define PWM_INTS_CH2_RESET 0x0 1484 #define PWM_INTS_CH2_BITS 0x00000004 1485 #define PWM_INTS_CH2_MSB 2 1486 #define PWM_INTS_CH2_LSB 2 1487 #define PWM_INTS_CH2_ACCESS "RO" 1488 // ----------------------------------------------------------------------------- 1489 // Field : PWM_INTS_CH1 1490 // Description : None 1491 #define PWM_INTS_CH1_RESET 0x0 1492 #define PWM_INTS_CH1_BITS 0x00000002 1493 #define PWM_INTS_CH1_MSB 1 1494 #define PWM_INTS_CH1_LSB 1 1495 #define PWM_INTS_CH1_ACCESS "RO" 1496 // ----------------------------------------------------------------------------- 1497 // Field : PWM_INTS_CH0 1498 // Description : None 1499 #define PWM_INTS_CH0_RESET 0x0 1500 #define PWM_INTS_CH0_BITS 0x00000001 1501 #define PWM_INTS_CH0_MSB 0 1502 #define PWM_INTS_CH0_LSB 0 1503 #define PWM_INTS_CH0_ACCESS "RO" 1504 // ============================================================================= 1505 #endif // HARDWARE_REGS_PWM_DEFINED 1506