1 /** 2 * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 // ============================================================================= 7 // Register block : ROSC 8 // Version : 1 9 // Bus type : apb 10 // Description : None 11 // ============================================================================= 12 #ifndef HARDWARE_REGS_ROSC_DEFINED 13 #define HARDWARE_REGS_ROSC_DEFINED 14 // ============================================================================= 15 // Register : ROSC_CTRL 16 // Description : Ring Oscillator control 17 #define ROSC_CTRL_OFFSET 0x00000000 18 #define ROSC_CTRL_BITS 0x00ffffff 19 #define ROSC_CTRL_RESET 0x00000aa0 20 // ----------------------------------------------------------------------------- 21 // Field : ROSC_CTRL_ENABLE 22 // Description : On power-up this field is initialised to ENABLE 23 // The system clock must be switched to another source before 24 // setting this field to DISABLE otherwise the chip will lock up 25 // The 12-bit code is intended to give some protection against 26 // accidental writes. An invalid setting will enable the 27 // oscillator. 28 // 0xd1e -> DISABLE 29 // 0xfab -> ENABLE 30 #define ROSC_CTRL_ENABLE_RESET "-" 31 #define ROSC_CTRL_ENABLE_BITS 0x00fff000 32 #define ROSC_CTRL_ENABLE_MSB 23 33 #define ROSC_CTRL_ENABLE_LSB 12 34 #define ROSC_CTRL_ENABLE_ACCESS "RW" 35 #define ROSC_CTRL_ENABLE_VALUE_DISABLE 0xd1e 36 #define ROSC_CTRL_ENABLE_VALUE_ENABLE 0xfab 37 // ----------------------------------------------------------------------------- 38 // Field : ROSC_CTRL_FREQ_RANGE 39 // Description : Controls the number of delay stages in the ROSC ring 40 // LOW uses stages 0 to 7 41 // MEDIUM uses stages 0 to 5 42 // HIGH uses stages 0 to 3 43 // TOOHIGH uses stages 0 to 1 and should not be used because its 44 // frequency exceeds design specifications 45 // The clock output will not glitch when changing the range up one 46 // step at a time 47 // The clock output will glitch when changing the range down 48 // Note: the values here are gray coded which is why HIGH comes 49 // before TOOHIGH 50 // 0xfa4 -> LOW 51 // 0xfa5 -> MEDIUM 52 // 0xfa7 -> HIGH 53 // 0xfa6 -> TOOHIGH 54 #define ROSC_CTRL_FREQ_RANGE_RESET 0xaa0 55 #define ROSC_CTRL_FREQ_RANGE_BITS 0x00000fff 56 #define ROSC_CTRL_FREQ_RANGE_MSB 11 57 #define ROSC_CTRL_FREQ_RANGE_LSB 0 58 #define ROSC_CTRL_FREQ_RANGE_ACCESS "RW" 59 #define ROSC_CTRL_FREQ_RANGE_VALUE_LOW 0xfa4 60 #define ROSC_CTRL_FREQ_RANGE_VALUE_MEDIUM 0xfa5 61 #define ROSC_CTRL_FREQ_RANGE_VALUE_HIGH 0xfa7 62 #define ROSC_CTRL_FREQ_RANGE_VALUE_TOOHIGH 0xfa6 63 // ============================================================================= 64 // Register : ROSC_FREQA 65 // Description : The FREQA & FREQB registers control the frequency by 66 // controlling the drive strength of each stage 67 // The drive strength has 4 levels determined by the number of 68 // bits set 69 // Increasing the number of bits set increases the drive strength 70 // and increases the oscillation frequency 71 // 0 bits set is the default drive strength 72 // 1 bit set doubles the drive strength 73 // 2 bits set triples drive strength 74 // 3 bits set quadruples drive strength 75 #define ROSC_FREQA_OFFSET 0x00000004 76 #define ROSC_FREQA_BITS 0xffff7777 77 #define ROSC_FREQA_RESET 0x00000000 78 // ----------------------------------------------------------------------------- 79 // Field : ROSC_FREQA_PASSWD 80 // Description : Set to 0x9696 to apply the settings 81 // Any other value in this field will set all drive strengths to 0 82 // 0x9696 -> PASS 83 #define ROSC_FREQA_PASSWD_RESET 0x0000 84 #define ROSC_FREQA_PASSWD_BITS 0xffff0000 85 #define ROSC_FREQA_PASSWD_MSB 31 86 #define ROSC_FREQA_PASSWD_LSB 16 87 #define ROSC_FREQA_PASSWD_ACCESS "RW" 88 #define ROSC_FREQA_PASSWD_VALUE_PASS 0x9696 89 // ----------------------------------------------------------------------------- 90 // Field : ROSC_FREQA_DS3 91 // Description : Stage 3 drive strength 92 #define ROSC_FREQA_DS3_RESET 0x0 93 #define ROSC_FREQA_DS3_BITS 0x00007000 94 #define ROSC_FREQA_DS3_MSB 14 95 #define ROSC_FREQA_DS3_LSB 12 96 #define ROSC_FREQA_DS3_ACCESS "RW" 97 // ----------------------------------------------------------------------------- 98 // Field : ROSC_FREQA_DS2 99 // Description : Stage 2 drive strength 100 #define ROSC_FREQA_DS2_RESET 0x0 101 #define ROSC_FREQA_DS2_BITS 0x00000700 102 #define ROSC_FREQA_DS2_MSB 10 103 #define ROSC_FREQA_DS2_LSB 8 104 #define ROSC_FREQA_DS2_ACCESS "RW" 105 // ----------------------------------------------------------------------------- 106 // Field : ROSC_FREQA_DS1 107 // Description : Stage 1 drive strength 108 #define ROSC_FREQA_DS1_RESET 0x0 109 #define ROSC_FREQA_DS1_BITS 0x00000070 110 #define ROSC_FREQA_DS1_MSB 6 111 #define ROSC_FREQA_DS1_LSB 4 112 #define ROSC_FREQA_DS1_ACCESS "RW" 113 // ----------------------------------------------------------------------------- 114 // Field : ROSC_FREQA_DS0 115 // Description : Stage 0 drive strength 116 #define ROSC_FREQA_DS0_RESET 0x0 117 #define ROSC_FREQA_DS0_BITS 0x00000007 118 #define ROSC_FREQA_DS0_MSB 2 119 #define ROSC_FREQA_DS0_LSB 0 120 #define ROSC_FREQA_DS0_ACCESS "RW" 121 // ============================================================================= 122 // Register : ROSC_FREQB 123 // Description : For a detailed description see freqa register 124 #define ROSC_FREQB_OFFSET 0x00000008 125 #define ROSC_FREQB_BITS 0xffff7777 126 #define ROSC_FREQB_RESET 0x00000000 127 // ----------------------------------------------------------------------------- 128 // Field : ROSC_FREQB_PASSWD 129 // Description : Set to 0x9696 to apply the settings 130 // Any other value in this field will set all drive strengths to 0 131 // 0x9696 -> PASS 132 #define ROSC_FREQB_PASSWD_RESET 0x0000 133 #define ROSC_FREQB_PASSWD_BITS 0xffff0000 134 #define ROSC_FREQB_PASSWD_MSB 31 135 #define ROSC_FREQB_PASSWD_LSB 16 136 #define ROSC_FREQB_PASSWD_ACCESS "RW" 137 #define ROSC_FREQB_PASSWD_VALUE_PASS 0x9696 138 // ----------------------------------------------------------------------------- 139 // Field : ROSC_FREQB_DS7 140 // Description : Stage 7 drive strength 141 #define ROSC_FREQB_DS7_RESET 0x0 142 #define ROSC_FREQB_DS7_BITS 0x00007000 143 #define ROSC_FREQB_DS7_MSB 14 144 #define ROSC_FREQB_DS7_LSB 12 145 #define ROSC_FREQB_DS7_ACCESS "RW" 146 // ----------------------------------------------------------------------------- 147 // Field : ROSC_FREQB_DS6 148 // Description : Stage 6 drive strength 149 #define ROSC_FREQB_DS6_RESET 0x0 150 #define ROSC_FREQB_DS6_BITS 0x00000700 151 #define ROSC_FREQB_DS6_MSB 10 152 #define ROSC_FREQB_DS6_LSB 8 153 #define ROSC_FREQB_DS6_ACCESS "RW" 154 // ----------------------------------------------------------------------------- 155 // Field : ROSC_FREQB_DS5 156 // Description : Stage 5 drive strength 157 #define ROSC_FREQB_DS5_RESET 0x0 158 #define ROSC_FREQB_DS5_BITS 0x00000070 159 #define ROSC_FREQB_DS5_MSB 6 160 #define ROSC_FREQB_DS5_LSB 4 161 #define ROSC_FREQB_DS5_ACCESS "RW" 162 // ----------------------------------------------------------------------------- 163 // Field : ROSC_FREQB_DS4 164 // Description : Stage 4 drive strength 165 #define ROSC_FREQB_DS4_RESET 0x0 166 #define ROSC_FREQB_DS4_BITS 0x00000007 167 #define ROSC_FREQB_DS4_MSB 2 168 #define ROSC_FREQB_DS4_LSB 0 169 #define ROSC_FREQB_DS4_ACCESS "RW" 170 // ============================================================================= 171 // Register : ROSC_DORMANT 172 // Description : Ring Oscillator pause control 173 // This is used to save power by pausing the ROSC 174 // On power-up this field is initialised to WAKE 175 // An invalid write will also select WAKE 176 // Warning: setup the irq before selecting dormant mode 177 // 0x636f6d61 -> DORMANT 178 // 0x77616b65 -> WAKE 179 #define ROSC_DORMANT_OFFSET 0x0000000c 180 #define ROSC_DORMANT_BITS 0xffffffff 181 #define ROSC_DORMANT_RESET "-" 182 #define ROSC_DORMANT_MSB 31 183 #define ROSC_DORMANT_LSB 0 184 #define ROSC_DORMANT_ACCESS "RW" 185 #define ROSC_DORMANT_VALUE_DORMANT 0x636f6d61 186 #define ROSC_DORMANT_VALUE_WAKE 0x77616b65 187 // ============================================================================= 188 // Register : ROSC_DIV 189 // Description : Controls the output divider 190 // set to 0xaa0 + div where 191 // div = 0 divides by 32 192 // div = 1-31 divides by div 193 // any other value sets div=0 and therefore divides by 32 194 // this register resets to div=16 195 // 0xaa0 -> PASS 196 #define ROSC_DIV_OFFSET 0x00000010 197 #define ROSC_DIV_BITS 0x00000fff 198 #define ROSC_DIV_RESET "-" 199 #define ROSC_DIV_MSB 11 200 #define ROSC_DIV_LSB 0 201 #define ROSC_DIV_ACCESS "RW" 202 #define ROSC_DIV_VALUE_PASS 0xaa0 203 // ============================================================================= 204 // Register : ROSC_PHASE 205 // Description : Controls the phase shifted output 206 #define ROSC_PHASE_OFFSET 0x00000014 207 #define ROSC_PHASE_BITS 0x00000fff 208 #define ROSC_PHASE_RESET 0x00000008 209 // ----------------------------------------------------------------------------- 210 // Field : ROSC_PHASE_PASSWD 211 // Description : set to 0xaa0 212 // any other value enables the output with shift=0 213 #define ROSC_PHASE_PASSWD_RESET 0x00 214 #define ROSC_PHASE_PASSWD_BITS 0x00000ff0 215 #define ROSC_PHASE_PASSWD_MSB 11 216 #define ROSC_PHASE_PASSWD_LSB 4 217 #define ROSC_PHASE_PASSWD_ACCESS "RW" 218 // ----------------------------------------------------------------------------- 219 // Field : ROSC_PHASE_ENABLE 220 // Description : enable the phase-shifted output 221 // this can be changed on-the-fly 222 #define ROSC_PHASE_ENABLE_RESET 0x1 223 #define ROSC_PHASE_ENABLE_BITS 0x00000008 224 #define ROSC_PHASE_ENABLE_MSB 3 225 #define ROSC_PHASE_ENABLE_LSB 3 226 #define ROSC_PHASE_ENABLE_ACCESS "RW" 227 // ----------------------------------------------------------------------------- 228 // Field : ROSC_PHASE_FLIP 229 // Description : invert the phase-shifted output 230 // this is ignored when div=1 231 #define ROSC_PHASE_FLIP_RESET 0x0 232 #define ROSC_PHASE_FLIP_BITS 0x00000004 233 #define ROSC_PHASE_FLIP_MSB 2 234 #define ROSC_PHASE_FLIP_LSB 2 235 #define ROSC_PHASE_FLIP_ACCESS "RW" 236 // ----------------------------------------------------------------------------- 237 // Field : ROSC_PHASE_SHIFT 238 // Description : phase shift the phase-shifted output by SHIFT input clocks 239 // this can be changed on-the-fly 240 // must be set to 0 before setting div=1 241 #define ROSC_PHASE_SHIFT_RESET 0x0 242 #define ROSC_PHASE_SHIFT_BITS 0x00000003 243 #define ROSC_PHASE_SHIFT_MSB 1 244 #define ROSC_PHASE_SHIFT_LSB 0 245 #define ROSC_PHASE_SHIFT_ACCESS "RW" 246 // ============================================================================= 247 // Register : ROSC_STATUS 248 // Description : Ring Oscillator Status 249 #define ROSC_STATUS_OFFSET 0x00000018 250 #define ROSC_STATUS_BITS 0x81011000 251 #define ROSC_STATUS_RESET 0x00000000 252 // ----------------------------------------------------------------------------- 253 // Field : ROSC_STATUS_STABLE 254 // Description : Oscillator is running and stable 255 #define ROSC_STATUS_STABLE_RESET 0x0 256 #define ROSC_STATUS_STABLE_BITS 0x80000000 257 #define ROSC_STATUS_STABLE_MSB 31 258 #define ROSC_STATUS_STABLE_LSB 31 259 #define ROSC_STATUS_STABLE_ACCESS "RO" 260 // ----------------------------------------------------------------------------- 261 // Field : ROSC_STATUS_BADWRITE 262 // Description : An invalid value has been written to CTRL_ENABLE or 263 // CTRL_FREQ_RANGE or FRFEQA or FREQB or DORMANT 264 #define ROSC_STATUS_BADWRITE_RESET 0x0 265 #define ROSC_STATUS_BADWRITE_BITS 0x01000000 266 #define ROSC_STATUS_BADWRITE_MSB 24 267 #define ROSC_STATUS_BADWRITE_LSB 24 268 #define ROSC_STATUS_BADWRITE_ACCESS "WC" 269 // ----------------------------------------------------------------------------- 270 // Field : ROSC_STATUS_DIV_RUNNING 271 // Description : post-divider is running 272 // this resets to 0 but transitions to 1 during chip startup 273 #define ROSC_STATUS_DIV_RUNNING_RESET "-" 274 #define ROSC_STATUS_DIV_RUNNING_BITS 0x00010000 275 #define ROSC_STATUS_DIV_RUNNING_MSB 16 276 #define ROSC_STATUS_DIV_RUNNING_LSB 16 277 #define ROSC_STATUS_DIV_RUNNING_ACCESS "RO" 278 // ----------------------------------------------------------------------------- 279 // Field : ROSC_STATUS_ENABLED 280 // Description : Oscillator is enabled but not necessarily running and stable 281 // this resets to 0 but transitions to 1 during chip startup 282 #define ROSC_STATUS_ENABLED_RESET "-" 283 #define ROSC_STATUS_ENABLED_BITS 0x00001000 284 #define ROSC_STATUS_ENABLED_MSB 12 285 #define ROSC_STATUS_ENABLED_LSB 12 286 #define ROSC_STATUS_ENABLED_ACCESS "RO" 287 // ============================================================================= 288 // Register : ROSC_RANDOMBIT 289 // Description : This just reads the state of the oscillator output so 290 // randomness is compromised if the ring oscillator is stopped or 291 // run at a harmonic of the bus frequency 292 #define ROSC_RANDOMBIT_OFFSET 0x0000001c 293 #define ROSC_RANDOMBIT_BITS 0x00000001 294 #define ROSC_RANDOMBIT_RESET 0x00000001 295 #define ROSC_RANDOMBIT_MSB 0 296 #define ROSC_RANDOMBIT_LSB 0 297 #define ROSC_RANDOMBIT_ACCESS "RO" 298 // ============================================================================= 299 // Register : ROSC_COUNT 300 // Description : A down counter running at the ROSC frequency which counts to 301 // zero and stops. 302 // To start the counter write a non-zero value. 303 // Can be used for short software pauses when setting up time 304 // sensitive hardware. 305 #define ROSC_COUNT_OFFSET 0x00000020 306 #define ROSC_COUNT_BITS 0x000000ff 307 #define ROSC_COUNT_RESET 0x00000000 308 #define ROSC_COUNT_MSB 7 309 #define ROSC_COUNT_LSB 0 310 #define ROSC_COUNT_ACCESS "RW" 311 // ============================================================================= 312 #endif // HARDWARE_REGS_ROSC_DEFINED 313