1 /** 2 * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 // ============================================================================= 7 // Register block : SPI 8 // Version : 1 9 // Bus type : apb 10 // Description : None 11 // ============================================================================= 12 #ifndef HARDWARE_REGS_SPI_DEFINED 13 #define HARDWARE_REGS_SPI_DEFINED 14 // ============================================================================= 15 // Register : SPI_SSPCR0 16 // Description : Control register 0, SSPCR0 on page 3-4 17 #define SPI_SSPCR0_OFFSET 0x00000000 18 #define SPI_SSPCR0_BITS 0x0000ffff 19 #define SPI_SSPCR0_RESET 0x00000000 20 // ----------------------------------------------------------------------------- 21 // Field : SPI_SSPCR0_SCR 22 // Description : Serial clock rate. The value SCR is used to generate the 23 // transmit and receive bit rate of the PrimeCell SSP. The bit 24 // rate is: F SSPCLK CPSDVSR x (1+SCR) where CPSDVSR is an even 25 // value from 2-254, programmed through the SSPCPSR register and 26 // SCR is a value from 0-255. 27 #define SPI_SSPCR0_SCR_RESET 0x00 28 #define SPI_SSPCR0_SCR_BITS 0x0000ff00 29 #define SPI_SSPCR0_SCR_MSB 15 30 #define SPI_SSPCR0_SCR_LSB 8 31 #define SPI_SSPCR0_SCR_ACCESS "RW" 32 // ----------------------------------------------------------------------------- 33 // Field : SPI_SSPCR0_SPH 34 // Description : SSPCLKOUT phase, applicable to Motorola SPI frame format only. 35 // See Motorola SPI frame format on page 2-10. 36 #define SPI_SSPCR0_SPH_RESET 0x0 37 #define SPI_SSPCR0_SPH_BITS 0x00000080 38 #define SPI_SSPCR0_SPH_MSB 7 39 #define SPI_SSPCR0_SPH_LSB 7 40 #define SPI_SSPCR0_SPH_ACCESS "RW" 41 // ----------------------------------------------------------------------------- 42 // Field : SPI_SSPCR0_SPO 43 // Description : SSPCLKOUT polarity, applicable to Motorola SPI frame format 44 // only. See Motorola SPI frame format on page 2-10. 45 #define SPI_SSPCR0_SPO_RESET 0x0 46 #define SPI_SSPCR0_SPO_BITS 0x00000040 47 #define SPI_SSPCR0_SPO_MSB 6 48 #define SPI_SSPCR0_SPO_LSB 6 49 #define SPI_SSPCR0_SPO_ACCESS "RW" 50 // ----------------------------------------------------------------------------- 51 // Field : SPI_SSPCR0_FRF 52 // Description : Frame format: 00 Motorola SPI frame format. 01 TI synchronous 53 // serial frame format. 10 National Microwire frame format. 11 54 // Reserved, undefined operation. 55 #define SPI_SSPCR0_FRF_RESET 0x0 56 #define SPI_SSPCR0_FRF_BITS 0x00000030 57 #define SPI_SSPCR0_FRF_MSB 5 58 #define SPI_SSPCR0_FRF_LSB 4 59 #define SPI_SSPCR0_FRF_ACCESS "RW" 60 // ----------------------------------------------------------------------------- 61 // Field : SPI_SSPCR0_DSS 62 // Description : Data Size Select: 0000 Reserved, undefined operation. 0001 63 // Reserved, undefined operation. 0010 Reserved, undefined 64 // operation. 0011 4-bit data. 0100 5-bit data. 0101 6-bit data. 65 // 0110 7-bit data. 0111 8-bit data. 1000 9-bit data. 1001 10-bit 66 // data. 1010 11-bit data. 1011 12-bit data. 1100 13-bit data. 67 // 1101 14-bit data. 1110 15-bit data. 1111 16-bit data. 68 #define SPI_SSPCR0_DSS_RESET 0x0 69 #define SPI_SSPCR0_DSS_BITS 0x0000000f 70 #define SPI_SSPCR0_DSS_MSB 3 71 #define SPI_SSPCR0_DSS_LSB 0 72 #define SPI_SSPCR0_DSS_ACCESS "RW" 73 // ============================================================================= 74 // Register : SPI_SSPCR1 75 // Description : Control register 1, SSPCR1 on page 3-5 76 #define SPI_SSPCR1_OFFSET 0x00000004 77 #define SPI_SSPCR1_BITS 0x0000000f 78 #define SPI_SSPCR1_RESET 0x00000000 79 // ----------------------------------------------------------------------------- 80 // Field : SPI_SSPCR1_SOD 81 // Description : Slave-mode output disable. This bit is relevant only in the 82 // slave mode, MS=1. In multiple-slave systems, it is possible for 83 // an PrimeCell SSP master to broadcast a message to all slaves in 84 // the system while ensuring that only one slave drives data onto 85 // its serial output line. In such systems the RXD lines from 86 // multiple slaves could be tied together. To operate in such 87 // systems, the SOD bit can be set if the PrimeCell SSP slave is 88 // not supposed to drive the SSPTXD line: 0 SSP can drive the 89 // SSPTXD output in slave mode. 1 SSP must not drive the SSPTXD 90 // output in slave mode. 91 #define SPI_SSPCR1_SOD_RESET 0x0 92 #define SPI_SSPCR1_SOD_BITS 0x00000008 93 #define SPI_SSPCR1_SOD_MSB 3 94 #define SPI_SSPCR1_SOD_LSB 3 95 #define SPI_SSPCR1_SOD_ACCESS "RW" 96 // ----------------------------------------------------------------------------- 97 // Field : SPI_SSPCR1_MS 98 // Description : Master or slave mode select. This bit can be modified only when 99 // the PrimeCell SSP is disabled, SSE=0: 0 Device configured as 100 // master, default. 1 Device configured as slave. 101 #define SPI_SSPCR1_MS_RESET 0x0 102 #define SPI_SSPCR1_MS_BITS 0x00000004 103 #define SPI_SSPCR1_MS_MSB 2 104 #define SPI_SSPCR1_MS_LSB 2 105 #define SPI_SSPCR1_MS_ACCESS "RW" 106 // ----------------------------------------------------------------------------- 107 // Field : SPI_SSPCR1_SSE 108 // Description : Synchronous serial port enable: 0 SSP operation disabled. 1 SSP 109 // operation enabled. 110 #define SPI_SSPCR1_SSE_RESET 0x0 111 #define SPI_SSPCR1_SSE_BITS 0x00000002 112 #define SPI_SSPCR1_SSE_MSB 1 113 #define SPI_SSPCR1_SSE_LSB 1 114 #define SPI_SSPCR1_SSE_ACCESS "RW" 115 // ----------------------------------------------------------------------------- 116 // Field : SPI_SSPCR1_LBM 117 // Description : Loop back mode: 0 Normal serial port operation enabled. 1 118 // Output of transmit serial shifter is connected to input of 119 // receive serial shifter internally. 120 #define SPI_SSPCR1_LBM_RESET 0x0 121 #define SPI_SSPCR1_LBM_BITS 0x00000001 122 #define SPI_SSPCR1_LBM_MSB 0 123 #define SPI_SSPCR1_LBM_LSB 0 124 #define SPI_SSPCR1_LBM_ACCESS "RW" 125 // ============================================================================= 126 // Register : SPI_SSPDR 127 // Description : Data register, SSPDR on page 3-6 128 #define SPI_SSPDR_OFFSET 0x00000008 129 #define SPI_SSPDR_BITS 0x0000ffff 130 #define SPI_SSPDR_RESET "-" 131 // ----------------------------------------------------------------------------- 132 // Field : SPI_SSPDR_DATA 133 // Description : Transmit/Receive FIFO: Read Receive FIFO. Write Transmit FIFO. 134 // You must right-justify data when the PrimeCell SSP is 135 // programmed for a data size that is less than 16 bits. Unused 136 // bits at the top are ignored by transmit logic. The receive 137 // logic automatically right-justifies. 138 #define SPI_SSPDR_DATA_RESET "-" 139 #define SPI_SSPDR_DATA_BITS 0x0000ffff 140 #define SPI_SSPDR_DATA_MSB 15 141 #define SPI_SSPDR_DATA_LSB 0 142 #define SPI_SSPDR_DATA_ACCESS "RWF" 143 // ============================================================================= 144 // Register : SPI_SSPSR 145 // Description : Status register, SSPSR on page 3-7 146 #define SPI_SSPSR_OFFSET 0x0000000c 147 #define SPI_SSPSR_BITS 0x0000001f 148 #define SPI_SSPSR_RESET 0x00000003 149 // ----------------------------------------------------------------------------- 150 // Field : SPI_SSPSR_BSY 151 // Description : PrimeCell SSP busy flag, RO: 0 SSP is idle. 1 SSP is currently 152 // transmitting and/or receiving a frame or the transmit FIFO is 153 // not empty. 154 #define SPI_SSPSR_BSY_RESET 0x0 155 #define SPI_SSPSR_BSY_BITS 0x00000010 156 #define SPI_SSPSR_BSY_MSB 4 157 #define SPI_SSPSR_BSY_LSB 4 158 #define SPI_SSPSR_BSY_ACCESS "RO" 159 // ----------------------------------------------------------------------------- 160 // Field : SPI_SSPSR_RFF 161 // Description : Receive FIFO full, RO: 0 Receive FIFO is not full. 1 Receive 162 // FIFO is full. 163 #define SPI_SSPSR_RFF_RESET 0x0 164 #define SPI_SSPSR_RFF_BITS 0x00000008 165 #define SPI_SSPSR_RFF_MSB 3 166 #define SPI_SSPSR_RFF_LSB 3 167 #define SPI_SSPSR_RFF_ACCESS "RO" 168 // ----------------------------------------------------------------------------- 169 // Field : SPI_SSPSR_RNE 170 // Description : Receive FIFO not empty, RO: 0 Receive FIFO is empty. 1 Receive 171 // FIFO is not empty. 172 #define SPI_SSPSR_RNE_RESET 0x0 173 #define SPI_SSPSR_RNE_BITS 0x00000004 174 #define SPI_SSPSR_RNE_MSB 2 175 #define SPI_SSPSR_RNE_LSB 2 176 #define SPI_SSPSR_RNE_ACCESS "RO" 177 // ----------------------------------------------------------------------------- 178 // Field : SPI_SSPSR_TNF 179 // Description : Transmit FIFO not full, RO: 0 Transmit FIFO is full. 1 Transmit 180 // FIFO is not full. 181 #define SPI_SSPSR_TNF_RESET 0x1 182 #define SPI_SSPSR_TNF_BITS 0x00000002 183 #define SPI_SSPSR_TNF_MSB 1 184 #define SPI_SSPSR_TNF_LSB 1 185 #define SPI_SSPSR_TNF_ACCESS "RO" 186 // ----------------------------------------------------------------------------- 187 // Field : SPI_SSPSR_TFE 188 // Description : Transmit FIFO empty, RO: 0 Transmit FIFO is not empty. 1 189 // Transmit FIFO is empty. 190 #define SPI_SSPSR_TFE_RESET 0x1 191 #define SPI_SSPSR_TFE_BITS 0x00000001 192 #define SPI_SSPSR_TFE_MSB 0 193 #define SPI_SSPSR_TFE_LSB 0 194 #define SPI_SSPSR_TFE_ACCESS "RO" 195 // ============================================================================= 196 // Register : SPI_SSPCPSR 197 // Description : Clock prescale register, SSPCPSR on page 3-8 198 #define SPI_SSPCPSR_OFFSET 0x00000010 199 #define SPI_SSPCPSR_BITS 0x000000ff 200 #define SPI_SSPCPSR_RESET 0x00000000 201 // ----------------------------------------------------------------------------- 202 // Field : SPI_SSPCPSR_CPSDVSR 203 // Description : Clock prescale divisor. Must be an even number from 2-254, 204 // depending on the frequency of SSPCLK. The least significant bit 205 // always returns zero on reads. 206 #define SPI_SSPCPSR_CPSDVSR_RESET 0x00 207 #define SPI_SSPCPSR_CPSDVSR_BITS 0x000000ff 208 #define SPI_SSPCPSR_CPSDVSR_MSB 7 209 #define SPI_SSPCPSR_CPSDVSR_LSB 0 210 #define SPI_SSPCPSR_CPSDVSR_ACCESS "RW" 211 // ============================================================================= 212 // Register : SPI_SSPIMSC 213 // Description : Interrupt mask set or clear register, SSPIMSC on page 3-9 214 #define SPI_SSPIMSC_OFFSET 0x00000014 215 #define SPI_SSPIMSC_BITS 0x0000000f 216 #define SPI_SSPIMSC_RESET 0x00000000 217 // ----------------------------------------------------------------------------- 218 // Field : SPI_SSPIMSC_TXIM 219 // Description : Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or 220 // less condition interrupt is masked. 1 Transmit FIFO half empty 221 // or less condition interrupt is not masked. 222 #define SPI_SSPIMSC_TXIM_RESET 0x0 223 #define SPI_SSPIMSC_TXIM_BITS 0x00000008 224 #define SPI_SSPIMSC_TXIM_MSB 3 225 #define SPI_SSPIMSC_TXIM_LSB 3 226 #define SPI_SSPIMSC_TXIM_ACCESS "RW" 227 // ----------------------------------------------------------------------------- 228 // Field : SPI_SSPIMSC_RXIM 229 // Description : Receive FIFO interrupt mask: 0 Receive FIFO half full or less 230 // condition interrupt is masked. 1 Receive FIFO half full or less 231 // condition interrupt is not masked. 232 #define SPI_SSPIMSC_RXIM_RESET 0x0 233 #define SPI_SSPIMSC_RXIM_BITS 0x00000004 234 #define SPI_SSPIMSC_RXIM_MSB 2 235 #define SPI_SSPIMSC_RXIM_LSB 2 236 #define SPI_SSPIMSC_RXIM_ACCESS "RW" 237 // ----------------------------------------------------------------------------- 238 // Field : SPI_SSPIMSC_RTIM 239 // Description : Receive timeout interrupt mask: 0 Receive FIFO not empty and no 240 // read prior to timeout period interrupt is masked. 1 Receive 241 // FIFO not empty and no read prior to timeout period interrupt is 242 // not masked. 243 #define SPI_SSPIMSC_RTIM_RESET 0x0 244 #define SPI_SSPIMSC_RTIM_BITS 0x00000002 245 #define SPI_SSPIMSC_RTIM_MSB 1 246 #define SPI_SSPIMSC_RTIM_LSB 1 247 #define SPI_SSPIMSC_RTIM_ACCESS "RW" 248 // ----------------------------------------------------------------------------- 249 // Field : SPI_SSPIMSC_RORIM 250 // Description : Receive overrun interrupt mask: 0 Receive FIFO written to while 251 // full condition interrupt is masked. 1 Receive FIFO written to 252 // while full condition interrupt is not masked. 253 #define SPI_SSPIMSC_RORIM_RESET 0x0 254 #define SPI_SSPIMSC_RORIM_BITS 0x00000001 255 #define SPI_SSPIMSC_RORIM_MSB 0 256 #define SPI_SSPIMSC_RORIM_LSB 0 257 #define SPI_SSPIMSC_RORIM_ACCESS "RW" 258 // ============================================================================= 259 // Register : SPI_SSPRIS 260 // Description : Raw interrupt status register, SSPRIS on page 3-10 261 #define SPI_SSPRIS_OFFSET 0x00000018 262 #define SPI_SSPRIS_BITS 0x0000000f 263 #define SPI_SSPRIS_RESET 0x00000008 264 // ----------------------------------------------------------------------------- 265 // Field : SPI_SSPRIS_TXRIS 266 // Description : Gives the raw interrupt state, prior to masking, of the 267 // SSPTXINTR interrupt 268 #define SPI_SSPRIS_TXRIS_RESET 0x1 269 #define SPI_SSPRIS_TXRIS_BITS 0x00000008 270 #define SPI_SSPRIS_TXRIS_MSB 3 271 #define SPI_SSPRIS_TXRIS_LSB 3 272 #define SPI_SSPRIS_TXRIS_ACCESS "RO" 273 // ----------------------------------------------------------------------------- 274 // Field : SPI_SSPRIS_RXRIS 275 // Description : Gives the raw interrupt state, prior to masking, of the 276 // SSPRXINTR interrupt 277 #define SPI_SSPRIS_RXRIS_RESET 0x0 278 #define SPI_SSPRIS_RXRIS_BITS 0x00000004 279 #define SPI_SSPRIS_RXRIS_MSB 2 280 #define SPI_SSPRIS_RXRIS_LSB 2 281 #define SPI_SSPRIS_RXRIS_ACCESS "RO" 282 // ----------------------------------------------------------------------------- 283 // Field : SPI_SSPRIS_RTRIS 284 // Description : Gives the raw interrupt state, prior to masking, of the 285 // SSPRTINTR interrupt 286 #define SPI_SSPRIS_RTRIS_RESET 0x0 287 #define SPI_SSPRIS_RTRIS_BITS 0x00000002 288 #define SPI_SSPRIS_RTRIS_MSB 1 289 #define SPI_SSPRIS_RTRIS_LSB 1 290 #define SPI_SSPRIS_RTRIS_ACCESS "RO" 291 // ----------------------------------------------------------------------------- 292 // Field : SPI_SSPRIS_RORRIS 293 // Description : Gives the raw interrupt state, prior to masking, of the 294 // SSPRORINTR interrupt 295 #define SPI_SSPRIS_RORRIS_RESET 0x0 296 #define SPI_SSPRIS_RORRIS_BITS 0x00000001 297 #define SPI_SSPRIS_RORRIS_MSB 0 298 #define SPI_SSPRIS_RORRIS_LSB 0 299 #define SPI_SSPRIS_RORRIS_ACCESS "RO" 300 // ============================================================================= 301 // Register : SPI_SSPMIS 302 // Description : Masked interrupt status register, SSPMIS on page 3-11 303 #define SPI_SSPMIS_OFFSET 0x0000001c 304 #define SPI_SSPMIS_BITS 0x0000000f 305 #define SPI_SSPMIS_RESET 0x00000000 306 // ----------------------------------------------------------------------------- 307 // Field : SPI_SSPMIS_TXMIS 308 // Description : Gives the transmit FIFO masked interrupt state, after masking, 309 // of the SSPTXINTR interrupt 310 #define SPI_SSPMIS_TXMIS_RESET 0x0 311 #define SPI_SSPMIS_TXMIS_BITS 0x00000008 312 #define SPI_SSPMIS_TXMIS_MSB 3 313 #define SPI_SSPMIS_TXMIS_LSB 3 314 #define SPI_SSPMIS_TXMIS_ACCESS "RO" 315 // ----------------------------------------------------------------------------- 316 // Field : SPI_SSPMIS_RXMIS 317 // Description : Gives the receive FIFO masked interrupt state, after masking, 318 // of the SSPRXINTR interrupt 319 #define SPI_SSPMIS_RXMIS_RESET 0x0 320 #define SPI_SSPMIS_RXMIS_BITS 0x00000004 321 #define SPI_SSPMIS_RXMIS_MSB 2 322 #define SPI_SSPMIS_RXMIS_LSB 2 323 #define SPI_SSPMIS_RXMIS_ACCESS "RO" 324 // ----------------------------------------------------------------------------- 325 // Field : SPI_SSPMIS_RTMIS 326 // Description : Gives the receive timeout masked interrupt state, after 327 // masking, of the SSPRTINTR interrupt 328 #define SPI_SSPMIS_RTMIS_RESET 0x0 329 #define SPI_SSPMIS_RTMIS_BITS 0x00000002 330 #define SPI_SSPMIS_RTMIS_MSB 1 331 #define SPI_SSPMIS_RTMIS_LSB 1 332 #define SPI_SSPMIS_RTMIS_ACCESS "RO" 333 // ----------------------------------------------------------------------------- 334 // Field : SPI_SSPMIS_RORMIS 335 // Description : Gives the receive over run masked interrupt status, after 336 // masking, of the SSPRORINTR interrupt 337 #define SPI_SSPMIS_RORMIS_RESET 0x0 338 #define SPI_SSPMIS_RORMIS_BITS 0x00000001 339 #define SPI_SSPMIS_RORMIS_MSB 0 340 #define SPI_SSPMIS_RORMIS_LSB 0 341 #define SPI_SSPMIS_RORMIS_ACCESS "RO" 342 // ============================================================================= 343 // Register : SPI_SSPICR 344 // Description : Interrupt clear register, SSPICR on page 3-11 345 #define SPI_SSPICR_OFFSET 0x00000020 346 #define SPI_SSPICR_BITS 0x00000003 347 #define SPI_SSPICR_RESET 0x00000000 348 // ----------------------------------------------------------------------------- 349 // Field : SPI_SSPICR_RTIC 350 // Description : Clears the SSPRTINTR interrupt 351 #define SPI_SSPICR_RTIC_RESET 0x0 352 #define SPI_SSPICR_RTIC_BITS 0x00000002 353 #define SPI_SSPICR_RTIC_MSB 1 354 #define SPI_SSPICR_RTIC_LSB 1 355 #define SPI_SSPICR_RTIC_ACCESS "WC" 356 // ----------------------------------------------------------------------------- 357 // Field : SPI_SSPICR_RORIC 358 // Description : Clears the SSPRORINTR interrupt 359 #define SPI_SSPICR_RORIC_RESET 0x0 360 #define SPI_SSPICR_RORIC_BITS 0x00000001 361 #define SPI_SSPICR_RORIC_MSB 0 362 #define SPI_SSPICR_RORIC_LSB 0 363 #define SPI_SSPICR_RORIC_ACCESS "WC" 364 // ============================================================================= 365 // Register : SPI_SSPDMACR 366 // Description : DMA control register, SSPDMACR on page 3-12 367 #define SPI_SSPDMACR_OFFSET 0x00000024 368 #define SPI_SSPDMACR_BITS 0x00000003 369 #define SPI_SSPDMACR_RESET 0x00000000 370 // ----------------------------------------------------------------------------- 371 // Field : SPI_SSPDMACR_TXDMAE 372 // Description : Transmit DMA Enable. If this bit is set to 1, DMA for the 373 // transmit FIFO is enabled. 374 #define SPI_SSPDMACR_TXDMAE_RESET 0x0 375 #define SPI_SSPDMACR_TXDMAE_BITS 0x00000002 376 #define SPI_SSPDMACR_TXDMAE_MSB 1 377 #define SPI_SSPDMACR_TXDMAE_LSB 1 378 #define SPI_SSPDMACR_TXDMAE_ACCESS "RW" 379 // ----------------------------------------------------------------------------- 380 // Field : SPI_SSPDMACR_RXDMAE 381 // Description : Receive DMA Enable. If this bit is set to 1, DMA for the 382 // receive FIFO is enabled. 383 #define SPI_SSPDMACR_RXDMAE_RESET 0x0 384 #define SPI_SSPDMACR_RXDMAE_BITS 0x00000001 385 #define SPI_SSPDMACR_RXDMAE_MSB 0 386 #define SPI_SSPDMACR_RXDMAE_LSB 0 387 #define SPI_SSPDMACR_RXDMAE_ACCESS "RW" 388 // ============================================================================= 389 // Register : SPI_SSPPERIPHID0 390 // Description : Peripheral identification registers, SSPPeriphID0-3 on page 391 // 3-13 392 #define SPI_SSPPERIPHID0_OFFSET 0x00000fe0 393 #define SPI_SSPPERIPHID0_BITS 0x000000ff 394 #define SPI_SSPPERIPHID0_RESET 0x00000022 395 // ----------------------------------------------------------------------------- 396 // Field : SPI_SSPPERIPHID0_PARTNUMBER0 397 // Description : These bits read back as 0x22 398 #define SPI_SSPPERIPHID0_PARTNUMBER0_RESET 0x22 399 #define SPI_SSPPERIPHID0_PARTNUMBER0_BITS 0x000000ff 400 #define SPI_SSPPERIPHID0_PARTNUMBER0_MSB 7 401 #define SPI_SSPPERIPHID0_PARTNUMBER0_LSB 0 402 #define SPI_SSPPERIPHID0_PARTNUMBER0_ACCESS "RO" 403 // ============================================================================= 404 // Register : SPI_SSPPERIPHID1 405 // Description : Peripheral identification registers, SSPPeriphID0-3 on page 406 // 3-13 407 #define SPI_SSPPERIPHID1_OFFSET 0x00000fe4 408 #define SPI_SSPPERIPHID1_BITS 0x000000ff 409 #define SPI_SSPPERIPHID1_RESET 0x00000010 410 // ----------------------------------------------------------------------------- 411 // Field : SPI_SSPPERIPHID1_DESIGNER0 412 // Description : These bits read back as 0x1 413 #define SPI_SSPPERIPHID1_DESIGNER0_RESET 0x1 414 #define SPI_SSPPERIPHID1_DESIGNER0_BITS 0x000000f0 415 #define SPI_SSPPERIPHID1_DESIGNER0_MSB 7 416 #define SPI_SSPPERIPHID1_DESIGNER0_LSB 4 417 #define SPI_SSPPERIPHID1_DESIGNER0_ACCESS "RO" 418 // ----------------------------------------------------------------------------- 419 // Field : SPI_SSPPERIPHID1_PARTNUMBER1 420 // Description : These bits read back as 0x0 421 #define SPI_SSPPERIPHID1_PARTNUMBER1_RESET 0x0 422 #define SPI_SSPPERIPHID1_PARTNUMBER1_BITS 0x0000000f 423 #define SPI_SSPPERIPHID1_PARTNUMBER1_MSB 3 424 #define SPI_SSPPERIPHID1_PARTNUMBER1_LSB 0 425 #define SPI_SSPPERIPHID1_PARTNUMBER1_ACCESS "RO" 426 // ============================================================================= 427 // Register : SPI_SSPPERIPHID2 428 // Description : Peripheral identification registers, SSPPeriphID0-3 on page 429 // 3-13 430 #define SPI_SSPPERIPHID2_OFFSET 0x00000fe8 431 #define SPI_SSPPERIPHID2_BITS 0x000000ff 432 #define SPI_SSPPERIPHID2_RESET 0x00000034 433 // ----------------------------------------------------------------------------- 434 // Field : SPI_SSPPERIPHID2_REVISION 435 // Description : These bits return the peripheral revision 436 #define SPI_SSPPERIPHID2_REVISION_RESET 0x3 437 #define SPI_SSPPERIPHID2_REVISION_BITS 0x000000f0 438 #define SPI_SSPPERIPHID2_REVISION_MSB 7 439 #define SPI_SSPPERIPHID2_REVISION_LSB 4 440 #define SPI_SSPPERIPHID2_REVISION_ACCESS "RO" 441 // ----------------------------------------------------------------------------- 442 // Field : SPI_SSPPERIPHID2_DESIGNER1 443 // Description : These bits read back as 0x4 444 #define SPI_SSPPERIPHID2_DESIGNER1_RESET 0x4 445 #define SPI_SSPPERIPHID2_DESIGNER1_BITS 0x0000000f 446 #define SPI_SSPPERIPHID2_DESIGNER1_MSB 3 447 #define SPI_SSPPERIPHID2_DESIGNER1_LSB 0 448 #define SPI_SSPPERIPHID2_DESIGNER1_ACCESS "RO" 449 // ============================================================================= 450 // Register : SPI_SSPPERIPHID3 451 // Description : Peripheral identification registers, SSPPeriphID0-3 on page 452 // 3-13 453 #define SPI_SSPPERIPHID3_OFFSET 0x00000fec 454 #define SPI_SSPPERIPHID3_BITS 0x000000ff 455 #define SPI_SSPPERIPHID3_RESET 0x00000000 456 // ----------------------------------------------------------------------------- 457 // Field : SPI_SSPPERIPHID3_CONFIGURATION 458 // Description : These bits read back as 0x00 459 #define SPI_SSPPERIPHID3_CONFIGURATION_RESET 0x00 460 #define SPI_SSPPERIPHID3_CONFIGURATION_BITS 0x000000ff 461 #define SPI_SSPPERIPHID3_CONFIGURATION_MSB 7 462 #define SPI_SSPPERIPHID3_CONFIGURATION_LSB 0 463 #define SPI_SSPPERIPHID3_CONFIGURATION_ACCESS "RO" 464 // ============================================================================= 465 // Register : SPI_SSPPCELLID0 466 // Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16 467 #define SPI_SSPPCELLID0_OFFSET 0x00000ff0 468 #define SPI_SSPPCELLID0_BITS 0x000000ff 469 #define SPI_SSPPCELLID0_RESET 0x0000000d 470 // ----------------------------------------------------------------------------- 471 // Field : SPI_SSPPCELLID0_SSPPCELLID0 472 // Description : These bits read back as 0x0D 473 #define SPI_SSPPCELLID0_SSPPCELLID0_RESET 0x0d 474 #define SPI_SSPPCELLID0_SSPPCELLID0_BITS 0x000000ff 475 #define SPI_SSPPCELLID0_SSPPCELLID0_MSB 7 476 #define SPI_SSPPCELLID0_SSPPCELLID0_LSB 0 477 #define SPI_SSPPCELLID0_SSPPCELLID0_ACCESS "RO" 478 // ============================================================================= 479 // Register : SPI_SSPPCELLID1 480 // Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16 481 #define SPI_SSPPCELLID1_OFFSET 0x00000ff4 482 #define SPI_SSPPCELLID1_BITS 0x000000ff 483 #define SPI_SSPPCELLID1_RESET 0x000000f0 484 // ----------------------------------------------------------------------------- 485 // Field : SPI_SSPPCELLID1_SSPPCELLID1 486 // Description : These bits read back as 0xF0 487 #define SPI_SSPPCELLID1_SSPPCELLID1_RESET 0xf0 488 #define SPI_SSPPCELLID1_SSPPCELLID1_BITS 0x000000ff 489 #define SPI_SSPPCELLID1_SSPPCELLID1_MSB 7 490 #define SPI_SSPPCELLID1_SSPPCELLID1_LSB 0 491 #define SPI_SSPPCELLID1_SSPPCELLID1_ACCESS "RO" 492 // ============================================================================= 493 // Register : SPI_SSPPCELLID2 494 // Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16 495 #define SPI_SSPPCELLID2_OFFSET 0x00000ff8 496 #define SPI_SSPPCELLID2_BITS 0x000000ff 497 #define SPI_SSPPCELLID2_RESET 0x00000005 498 // ----------------------------------------------------------------------------- 499 // Field : SPI_SSPPCELLID2_SSPPCELLID2 500 // Description : These bits read back as 0x05 501 #define SPI_SSPPCELLID2_SSPPCELLID2_RESET 0x05 502 #define SPI_SSPPCELLID2_SSPPCELLID2_BITS 0x000000ff 503 #define SPI_SSPPCELLID2_SSPPCELLID2_MSB 7 504 #define SPI_SSPPCELLID2_SSPPCELLID2_LSB 0 505 #define SPI_SSPPCELLID2_SSPPCELLID2_ACCESS "RO" 506 // ============================================================================= 507 // Register : SPI_SSPPCELLID3 508 // Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16 509 #define SPI_SSPPCELLID3_OFFSET 0x00000ffc 510 #define SPI_SSPPCELLID3_BITS 0x000000ff 511 #define SPI_SSPPCELLID3_RESET 0x000000b1 512 // ----------------------------------------------------------------------------- 513 // Field : SPI_SSPPCELLID3_SSPPCELLID3 514 // Description : These bits read back as 0xB1 515 #define SPI_SSPPCELLID3_SSPPCELLID3_RESET 0xb1 516 #define SPI_SSPPCELLID3_SSPPCELLID3_BITS 0x000000ff 517 #define SPI_SSPPCELLID3_SSPPCELLID3_MSB 7 518 #define SPI_SSPPCELLID3_SSPPCELLID3_LSB 0 519 #define SPI_SSPPCELLID3_SSPPCELLID3_ACCESS "RO" 520 // ============================================================================= 521 #endif // HARDWARE_REGS_SPI_DEFINED 522