1 /** 2 * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 // ============================================================================= 7 // Register block : SSI 8 // Version : 1 9 // Bus type : apb 10 // Description : DW_apb_ssi has the following features: 11 // * APB interface – Allows for easy integration into a 12 // DesignWare Synthesizable Components for AMBA 2 13 // implementation. 14 // * APB3 and APB4 protocol support. 15 // * Scalable APB data bus width – Supports APB data bus widths 16 // of 8, 16, and 32 bits. 17 // * Serial-master or serial-slave operation – Enables serial 18 // communication with serial-master or serial-slave peripheral 19 // devices. 20 // * Programmable Dual/Quad/Octal SPI support in Master Mode. 21 // * Dual Data Rate (DDR) and Read Data Strobe (RDS) Support - 22 // Enables the DW_apb_ssi master to perform operations with the 23 // device in DDR and RDS modes when working in Dual/Quad/Octal 24 // mode of operation. 25 // * Data Mask Support - Enables the DW_apb_ssi to selectively 26 // update the bytes in the device. This feature is applicable 27 // only in enhanced SPI modes. 28 // * eXecute-In-Place (XIP) support - Enables the DW_apb_ssi 29 // master to behave as a memory mapped I/O and fetches the data 30 // from the device based on the APB read request. This feature 31 // is applicable only in enhanced SPI modes. 32 // * DMA Controller Interface – Enables the DW_apb_ssi to 33 // interface to a DMA controller over the bus using a 34 // handshaking interface for transfer requests. 35 // * Independent masking of interrupts – Master collision, 36 // transmit FIFO overflow, transmit FIFO empty, receive FIFO 37 // full, receive FIFO underflow, and receive FIFO overflow 38 // interrupts can all be masked independently. 39 // * Multi-master contention detection – Informs the processor 40 // of multiple serial-master accesses on the serial bus. 41 // * Bypass of meta-stability flip-flops for synchronous clocks 42 // – When the APB clock (pclk) and the DW_apb_ssi serial clock 43 // (ssi_clk) are synchronous, meta-stable flip-flops are not 44 // used when transferring control signals across these clock 45 // domains. 46 // * Programmable delay on the sample time of the received 47 // serial data bit (rxd); enables programmable control of 48 // routing delays resulting in higher serial data-bit rates. 49 // * Programmable features: 50 // - Serial interface operation – Choice of Motorola SPI, Texas 51 // Instruments Synchronous Serial Protocol or National 52 // Semiconductor Microwire. 53 // - Clock bit-rate – Dynamic control of the serial bit rate of 54 // the data transfer; used in only serial-master mode of 55 // operation. 56 // - Data Item size (4 to 32 bits) – Item size of each data 57 // transfer under the control of the programmer. 58 // * Configured features: 59 // - FIFO depth – 16 words deep. The FIFO width is fixed at 32 60 // bits. 61 // - 1 slave select output. 62 // - Hardware slave-select – Dedicated hardware slave-select 63 // line. 64 // - Combined interrupt line - one combined interrupt line from 65 // the DW_apb_ssi to the interrupt controller. 66 // - Interrupt polarity – active high interrupt lines. 67 // - Serial clock polarity – low serial-clock polarity directly 68 // after reset. 69 // - Serial clock phase – capture on first edge of serial-clock 70 // directly after reset. 71 // ============================================================================= 72 #ifndef HARDWARE_REGS_SSI_DEFINED 73 #define HARDWARE_REGS_SSI_DEFINED 74 // ============================================================================= 75 // Register : SSI_CTRLR0 76 // Description : Control register 0 77 #define SSI_CTRLR0_OFFSET 0x00000000 78 #define SSI_CTRLR0_BITS 0x017fffff 79 #define SSI_CTRLR0_RESET 0x00000000 80 // ----------------------------------------------------------------------------- 81 // Field : SSI_CTRLR0_SSTE 82 // Description : Slave select toggle enable 83 #define SSI_CTRLR0_SSTE_RESET 0x0 84 #define SSI_CTRLR0_SSTE_BITS 0x01000000 85 #define SSI_CTRLR0_SSTE_MSB 24 86 #define SSI_CTRLR0_SSTE_LSB 24 87 #define SSI_CTRLR0_SSTE_ACCESS "RW" 88 // ----------------------------------------------------------------------------- 89 // Field : SSI_CTRLR0_SPI_FRF 90 // Description : SPI frame format 91 // 0x0 -> Standard 1-bit SPI frame format; 1 bit per SCK, 92 // full-duplex 93 // 0x1 -> Dual-SPI frame format; two bits per SCK, half-duplex 94 // 0x2 -> Quad-SPI frame format; four bits per SCK, half-duplex 95 #define SSI_CTRLR0_SPI_FRF_RESET 0x0 96 #define SSI_CTRLR0_SPI_FRF_BITS 0x00600000 97 #define SSI_CTRLR0_SPI_FRF_MSB 22 98 #define SSI_CTRLR0_SPI_FRF_LSB 21 99 #define SSI_CTRLR0_SPI_FRF_ACCESS "RW" 100 #define SSI_CTRLR0_SPI_FRF_VALUE_STD 0x0 101 #define SSI_CTRLR0_SPI_FRF_VALUE_DUAL 0x1 102 #define SSI_CTRLR0_SPI_FRF_VALUE_QUAD 0x2 103 // ----------------------------------------------------------------------------- 104 // Field : SSI_CTRLR0_DFS_32 105 // Description : Data frame size in 32b transfer mode 106 // Value of n -> n+1 clocks per frame. 107 #define SSI_CTRLR0_DFS_32_RESET 0x00 108 #define SSI_CTRLR0_DFS_32_BITS 0x001f0000 109 #define SSI_CTRLR0_DFS_32_MSB 20 110 #define SSI_CTRLR0_DFS_32_LSB 16 111 #define SSI_CTRLR0_DFS_32_ACCESS "RW" 112 // ----------------------------------------------------------------------------- 113 // Field : SSI_CTRLR0_CFS 114 // Description : Control frame size 115 // Value of n -> n+1 clocks per frame. 116 #define SSI_CTRLR0_CFS_RESET 0x0 117 #define SSI_CTRLR0_CFS_BITS 0x0000f000 118 #define SSI_CTRLR0_CFS_MSB 15 119 #define SSI_CTRLR0_CFS_LSB 12 120 #define SSI_CTRLR0_CFS_ACCESS "RW" 121 // ----------------------------------------------------------------------------- 122 // Field : SSI_CTRLR0_SRL 123 // Description : Shift register loop (test mode) 124 #define SSI_CTRLR0_SRL_RESET 0x0 125 #define SSI_CTRLR0_SRL_BITS 0x00000800 126 #define SSI_CTRLR0_SRL_MSB 11 127 #define SSI_CTRLR0_SRL_LSB 11 128 #define SSI_CTRLR0_SRL_ACCESS "RW" 129 // ----------------------------------------------------------------------------- 130 // Field : SSI_CTRLR0_SLV_OE 131 // Description : Slave output enable 132 #define SSI_CTRLR0_SLV_OE_RESET 0x0 133 #define SSI_CTRLR0_SLV_OE_BITS 0x00000400 134 #define SSI_CTRLR0_SLV_OE_MSB 10 135 #define SSI_CTRLR0_SLV_OE_LSB 10 136 #define SSI_CTRLR0_SLV_OE_ACCESS "RW" 137 // ----------------------------------------------------------------------------- 138 // Field : SSI_CTRLR0_TMOD 139 // Description : Transfer mode 140 // 0x0 -> Both transmit and receive 141 // 0x1 -> Transmit only (not for FRF == 0, standard SPI mode) 142 // 0x2 -> Receive only (not for FRF == 0, standard SPI mode) 143 // 0x3 -> EEPROM read mode (TX then RX; RX starts after control 144 // data TX'd) 145 #define SSI_CTRLR0_TMOD_RESET 0x0 146 #define SSI_CTRLR0_TMOD_BITS 0x00000300 147 #define SSI_CTRLR0_TMOD_MSB 9 148 #define SSI_CTRLR0_TMOD_LSB 8 149 #define SSI_CTRLR0_TMOD_ACCESS "RW" 150 #define SSI_CTRLR0_TMOD_VALUE_TX_AND_RX 0x0 151 #define SSI_CTRLR0_TMOD_VALUE_TX_ONLY 0x1 152 #define SSI_CTRLR0_TMOD_VALUE_RX_ONLY 0x2 153 #define SSI_CTRLR0_TMOD_VALUE_EEPROM_READ 0x3 154 // ----------------------------------------------------------------------------- 155 // Field : SSI_CTRLR0_SCPOL 156 // Description : Serial clock polarity 157 #define SSI_CTRLR0_SCPOL_RESET 0x0 158 #define SSI_CTRLR0_SCPOL_BITS 0x00000080 159 #define SSI_CTRLR0_SCPOL_MSB 7 160 #define SSI_CTRLR0_SCPOL_LSB 7 161 #define SSI_CTRLR0_SCPOL_ACCESS "RW" 162 // ----------------------------------------------------------------------------- 163 // Field : SSI_CTRLR0_SCPH 164 // Description : Serial clock phase 165 #define SSI_CTRLR0_SCPH_RESET 0x0 166 #define SSI_CTRLR0_SCPH_BITS 0x00000040 167 #define SSI_CTRLR0_SCPH_MSB 6 168 #define SSI_CTRLR0_SCPH_LSB 6 169 #define SSI_CTRLR0_SCPH_ACCESS "RW" 170 // ----------------------------------------------------------------------------- 171 // Field : SSI_CTRLR0_FRF 172 // Description : Frame format 173 #define SSI_CTRLR0_FRF_RESET 0x0 174 #define SSI_CTRLR0_FRF_BITS 0x00000030 175 #define SSI_CTRLR0_FRF_MSB 5 176 #define SSI_CTRLR0_FRF_LSB 4 177 #define SSI_CTRLR0_FRF_ACCESS "RW" 178 // ----------------------------------------------------------------------------- 179 // Field : SSI_CTRLR0_DFS 180 // Description : Data frame size 181 #define SSI_CTRLR0_DFS_RESET 0x0 182 #define SSI_CTRLR0_DFS_BITS 0x0000000f 183 #define SSI_CTRLR0_DFS_MSB 3 184 #define SSI_CTRLR0_DFS_LSB 0 185 #define SSI_CTRLR0_DFS_ACCESS "RW" 186 // ============================================================================= 187 // Register : SSI_CTRLR1 188 // Description : Master Control register 1 189 #define SSI_CTRLR1_OFFSET 0x00000004 190 #define SSI_CTRLR1_BITS 0x0000ffff 191 #define SSI_CTRLR1_RESET 0x00000000 192 // ----------------------------------------------------------------------------- 193 // Field : SSI_CTRLR1_NDF 194 // Description : Number of data frames 195 #define SSI_CTRLR1_NDF_RESET 0x0000 196 #define SSI_CTRLR1_NDF_BITS 0x0000ffff 197 #define SSI_CTRLR1_NDF_MSB 15 198 #define SSI_CTRLR1_NDF_LSB 0 199 #define SSI_CTRLR1_NDF_ACCESS "RW" 200 // ============================================================================= 201 // Register : SSI_SSIENR 202 // Description : SSI Enable 203 #define SSI_SSIENR_OFFSET 0x00000008 204 #define SSI_SSIENR_BITS 0x00000001 205 #define SSI_SSIENR_RESET 0x00000000 206 // ----------------------------------------------------------------------------- 207 // Field : SSI_SSIENR_SSI_EN 208 // Description : SSI enable 209 #define SSI_SSIENR_SSI_EN_RESET 0x0 210 #define SSI_SSIENR_SSI_EN_BITS 0x00000001 211 #define SSI_SSIENR_SSI_EN_MSB 0 212 #define SSI_SSIENR_SSI_EN_LSB 0 213 #define SSI_SSIENR_SSI_EN_ACCESS "RW" 214 // ============================================================================= 215 // Register : SSI_MWCR 216 // Description : Microwire Control 217 #define SSI_MWCR_OFFSET 0x0000000c 218 #define SSI_MWCR_BITS 0x00000007 219 #define SSI_MWCR_RESET 0x00000000 220 // ----------------------------------------------------------------------------- 221 // Field : SSI_MWCR_MHS 222 // Description : Microwire handshaking 223 #define SSI_MWCR_MHS_RESET 0x0 224 #define SSI_MWCR_MHS_BITS 0x00000004 225 #define SSI_MWCR_MHS_MSB 2 226 #define SSI_MWCR_MHS_LSB 2 227 #define SSI_MWCR_MHS_ACCESS "RW" 228 // ----------------------------------------------------------------------------- 229 // Field : SSI_MWCR_MDD 230 // Description : Microwire control 231 #define SSI_MWCR_MDD_RESET 0x0 232 #define SSI_MWCR_MDD_BITS 0x00000002 233 #define SSI_MWCR_MDD_MSB 1 234 #define SSI_MWCR_MDD_LSB 1 235 #define SSI_MWCR_MDD_ACCESS "RW" 236 // ----------------------------------------------------------------------------- 237 // Field : SSI_MWCR_MWMOD 238 // Description : Microwire transfer mode 239 #define SSI_MWCR_MWMOD_RESET 0x0 240 #define SSI_MWCR_MWMOD_BITS 0x00000001 241 #define SSI_MWCR_MWMOD_MSB 0 242 #define SSI_MWCR_MWMOD_LSB 0 243 #define SSI_MWCR_MWMOD_ACCESS "RW" 244 // ============================================================================= 245 // Register : SSI_SER 246 // Description : Slave enable 247 // For each bit: 248 // 0 -> slave not selected 249 // 1 -> slave selected 250 #define SSI_SER_OFFSET 0x00000010 251 #define SSI_SER_BITS 0x00000001 252 #define SSI_SER_RESET 0x00000000 253 #define SSI_SER_MSB 0 254 #define SSI_SER_LSB 0 255 #define SSI_SER_ACCESS "RW" 256 // ============================================================================= 257 // Register : SSI_BAUDR 258 // Description : Baud rate 259 #define SSI_BAUDR_OFFSET 0x00000014 260 #define SSI_BAUDR_BITS 0x0000ffff 261 #define SSI_BAUDR_RESET 0x00000000 262 // ----------------------------------------------------------------------------- 263 // Field : SSI_BAUDR_SCKDV 264 // Description : SSI clock divider 265 #define SSI_BAUDR_SCKDV_RESET 0x0000 266 #define SSI_BAUDR_SCKDV_BITS 0x0000ffff 267 #define SSI_BAUDR_SCKDV_MSB 15 268 #define SSI_BAUDR_SCKDV_LSB 0 269 #define SSI_BAUDR_SCKDV_ACCESS "RW" 270 // ============================================================================= 271 // Register : SSI_TXFTLR 272 // Description : TX FIFO threshold level 273 #define SSI_TXFTLR_OFFSET 0x00000018 274 #define SSI_TXFTLR_BITS 0x000000ff 275 #define SSI_TXFTLR_RESET 0x00000000 276 // ----------------------------------------------------------------------------- 277 // Field : SSI_TXFTLR_TFT 278 // Description : Transmit FIFO threshold 279 #define SSI_TXFTLR_TFT_RESET 0x00 280 #define SSI_TXFTLR_TFT_BITS 0x000000ff 281 #define SSI_TXFTLR_TFT_MSB 7 282 #define SSI_TXFTLR_TFT_LSB 0 283 #define SSI_TXFTLR_TFT_ACCESS "RW" 284 // ============================================================================= 285 // Register : SSI_RXFTLR 286 // Description : RX FIFO threshold level 287 #define SSI_RXFTLR_OFFSET 0x0000001c 288 #define SSI_RXFTLR_BITS 0x000000ff 289 #define SSI_RXFTLR_RESET 0x00000000 290 // ----------------------------------------------------------------------------- 291 // Field : SSI_RXFTLR_RFT 292 // Description : Receive FIFO threshold 293 #define SSI_RXFTLR_RFT_RESET 0x00 294 #define SSI_RXFTLR_RFT_BITS 0x000000ff 295 #define SSI_RXFTLR_RFT_MSB 7 296 #define SSI_RXFTLR_RFT_LSB 0 297 #define SSI_RXFTLR_RFT_ACCESS "RW" 298 // ============================================================================= 299 // Register : SSI_TXFLR 300 // Description : TX FIFO level 301 #define SSI_TXFLR_OFFSET 0x00000020 302 #define SSI_TXFLR_BITS 0x000000ff 303 #define SSI_TXFLR_RESET 0x00000000 304 // ----------------------------------------------------------------------------- 305 // Field : SSI_TXFLR_TFTFL 306 // Description : Transmit FIFO level 307 #define SSI_TXFLR_TFTFL_RESET 0x00 308 #define SSI_TXFLR_TFTFL_BITS 0x000000ff 309 #define SSI_TXFLR_TFTFL_MSB 7 310 #define SSI_TXFLR_TFTFL_LSB 0 311 #define SSI_TXFLR_TFTFL_ACCESS "RO" 312 // ============================================================================= 313 // Register : SSI_RXFLR 314 // Description : RX FIFO level 315 #define SSI_RXFLR_OFFSET 0x00000024 316 #define SSI_RXFLR_BITS 0x000000ff 317 #define SSI_RXFLR_RESET 0x00000000 318 // ----------------------------------------------------------------------------- 319 // Field : SSI_RXFLR_RXTFL 320 // Description : Receive FIFO level 321 #define SSI_RXFLR_RXTFL_RESET 0x00 322 #define SSI_RXFLR_RXTFL_BITS 0x000000ff 323 #define SSI_RXFLR_RXTFL_MSB 7 324 #define SSI_RXFLR_RXTFL_LSB 0 325 #define SSI_RXFLR_RXTFL_ACCESS "RO" 326 // ============================================================================= 327 // Register : SSI_SR 328 // Description : Status register 329 #define SSI_SR_OFFSET 0x00000028 330 #define SSI_SR_BITS 0x0000007f 331 #define SSI_SR_RESET 0x00000000 332 // ----------------------------------------------------------------------------- 333 // Field : SSI_SR_DCOL 334 // Description : Data collision error 335 #define SSI_SR_DCOL_RESET 0x0 336 #define SSI_SR_DCOL_BITS 0x00000040 337 #define SSI_SR_DCOL_MSB 6 338 #define SSI_SR_DCOL_LSB 6 339 #define SSI_SR_DCOL_ACCESS "RO" 340 // ----------------------------------------------------------------------------- 341 // Field : SSI_SR_TXE 342 // Description : Transmission error 343 #define SSI_SR_TXE_RESET 0x0 344 #define SSI_SR_TXE_BITS 0x00000020 345 #define SSI_SR_TXE_MSB 5 346 #define SSI_SR_TXE_LSB 5 347 #define SSI_SR_TXE_ACCESS "RO" 348 // ----------------------------------------------------------------------------- 349 // Field : SSI_SR_RFF 350 // Description : Receive FIFO full 351 #define SSI_SR_RFF_RESET 0x0 352 #define SSI_SR_RFF_BITS 0x00000010 353 #define SSI_SR_RFF_MSB 4 354 #define SSI_SR_RFF_LSB 4 355 #define SSI_SR_RFF_ACCESS "RO" 356 // ----------------------------------------------------------------------------- 357 // Field : SSI_SR_RFNE 358 // Description : Receive FIFO not empty 359 #define SSI_SR_RFNE_RESET 0x0 360 #define SSI_SR_RFNE_BITS 0x00000008 361 #define SSI_SR_RFNE_MSB 3 362 #define SSI_SR_RFNE_LSB 3 363 #define SSI_SR_RFNE_ACCESS "RO" 364 // ----------------------------------------------------------------------------- 365 // Field : SSI_SR_TFE 366 // Description : Transmit FIFO empty 367 #define SSI_SR_TFE_RESET 0x0 368 #define SSI_SR_TFE_BITS 0x00000004 369 #define SSI_SR_TFE_MSB 2 370 #define SSI_SR_TFE_LSB 2 371 #define SSI_SR_TFE_ACCESS "RO" 372 // ----------------------------------------------------------------------------- 373 // Field : SSI_SR_TFNF 374 // Description : Transmit FIFO not full 375 #define SSI_SR_TFNF_RESET 0x0 376 #define SSI_SR_TFNF_BITS 0x00000002 377 #define SSI_SR_TFNF_MSB 1 378 #define SSI_SR_TFNF_LSB 1 379 #define SSI_SR_TFNF_ACCESS "RO" 380 // ----------------------------------------------------------------------------- 381 // Field : SSI_SR_BUSY 382 // Description : SSI busy flag 383 #define SSI_SR_BUSY_RESET 0x0 384 #define SSI_SR_BUSY_BITS 0x00000001 385 #define SSI_SR_BUSY_MSB 0 386 #define SSI_SR_BUSY_LSB 0 387 #define SSI_SR_BUSY_ACCESS "RO" 388 // ============================================================================= 389 // Register : SSI_IMR 390 // Description : Interrupt mask 391 #define SSI_IMR_OFFSET 0x0000002c 392 #define SSI_IMR_BITS 0x0000003f 393 #define SSI_IMR_RESET 0x00000000 394 // ----------------------------------------------------------------------------- 395 // Field : SSI_IMR_MSTIM 396 // Description : Multi-master contention interrupt mask 397 #define SSI_IMR_MSTIM_RESET 0x0 398 #define SSI_IMR_MSTIM_BITS 0x00000020 399 #define SSI_IMR_MSTIM_MSB 5 400 #define SSI_IMR_MSTIM_LSB 5 401 #define SSI_IMR_MSTIM_ACCESS "RW" 402 // ----------------------------------------------------------------------------- 403 // Field : SSI_IMR_RXFIM 404 // Description : Receive FIFO full interrupt mask 405 #define SSI_IMR_RXFIM_RESET 0x0 406 #define SSI_IMR_RXFIM_BITS 0x00000010 407 #define SSI_IMR_RXFIM_MSB 4 408 #define SSI_IMR_RXFIM_LSB 4 409 #define SSI_IMR_RXFIM_ACCESS "RW" 410 // ----------------------------------------------------------------------------- 411 // Field : SSI_IMR_RXOIM 412 // Description : Receive FIFO overflow interrupt mask 413 #define SSI_IMR_RXOIM_RESET 0x0 414 #define SSI_IMR_RXOIM_BITS 0x00000008 415 #define SSI_IMR_RXOIM_MSB 3 416 #define SSI_IMR_RXOIM_LSB 3 417 #define SSI_IMR_RXOIM_ACCESS "RW" 418 // ----------------------------------------------------------------------------- 419 // Field : SSI_IMR_RXUIM 420 // Description : Receive FIFO underflow interrupt mask 421 #define SSI_IMR_RXUIM_RESET 0x0 422 #define SSI_IMR_RXUIM_BITS 0x00000004 423 #define SSI_IMR_RXUIM_MSB 2 424 #define SSI_IMR_RXUIM_LSB 2 425 #define SSI_IMR_RXUIM_ACCESS "RW" 426 // ----------------------------------------------------------------------------- 427 // Field : SSI_IMR_TXOIM 428 // Description : Transmit FIFO overflow interrupt mask 429 #define SSI_IMR_TXOIM_RESET 0x0 430 #define SSI_IMR_TXOIM_BITS 0x00000002 431 #define SSI_IMR_TXOIM_MSB 1 432 #define SSI_IMR_TXOIM_LSB 1 433 #define SSI_IMR_TXOIM_ACCESS "RW" 434 // ----------------------------------------------------------------------------- 435 // Field : SSI_IMR_TXEIM 436 // Description : Transmit FIFO empty interrupt mask 437 #define SSI_IMR_TXEIM_RESET 0x0 438 #define SSI_IMR_TXEIM_BITS 0x00000001 439 #define SSI_IMR_TXEIM_MSB 0 440 #define SSI_IMR_TXEIM_LSB 0 441 #define SSI_IMR_TXEIM_ACCESS "RW" 442 // ============================================================================= 443 // Register : SSI_ISR 444 // Description : Interrupt status 445 #define SSI_ISR_OFFSET 0x00000030 446 #define SSI_ISR_BITS 0x0000003f 447 #define SSI_ISR_RESET 0x00000000 448 // ----------------------------------------------------------------------------- 449 // Field : SSI_ISR_MSTIS 450 // Description : Multi-master contention interrupt status 451 #define SSI_ISR_MSTIS_RESET 0x0 452 #define SSI_ISR_MSTIS_BITS 0x00000020 453 #define SSI_ISR_MSTIS_MSB 5 454 #define SSI_ISR_MSTIS_LSB 5 455 #define SSI_ISR_MSTIS_ACCESS "RO" 456 // ----------------------------------------------------------------------------- 457 // Field : SSI_ISR_RXFIS 458 // Description : Receive FIFO full interrupt status 459 #define SSI_ISR_RXFIS_RESET 0x0 460 #define SSI_ISR_RXFIS_BITS 0x00000010 461 #define SSI_ISR_RXFIS_MSB 4 462 #define SSI_ISR_RXFIS_LSB 4 463 #define SSI_ISR_RXFIS_ACCESS "RO" 464 // ----------------------------------------------------------------------------- 465 // Field : SSI_ISR_RXOIS 466 // Description : Receive FIFO overflow interrupt status 467 #define SSI_ISR_RXOIS_RESET 0x0 468 #define SSI_ISR_RXOIS_BITS 0x00000008 469 #define SSI_ISR_RXOIS_MSB 3 470 #define SSI_ISR_RXOIS_LSB 3 471 #define SSI_ISR_RXOIS_ACCESS "RO" 472 // ----------------------------------------------------------------------------- 473 // Field : SSI_ISR_RXUIS 474 // Description : Receive FIFO underflow interrupt status 475 #define SSI_ISR_RXUIS_RESET 0x0 476 #define SSI_ISR_RXUIS_BITS 0x00000004 477 #define SSI_ISR_RXUIS_MSB 2 478 #define SSI_ISR_RXUIS_LSB 2 479 #define SSI_ISR_RXUIS_ACCESS "RO" 480 // ----------------------------------------------------------------------------- 481 // Field : SSI_ISR_TXOIS 482 // Description : Transmit FIFO overflow interrupt status 483 #define SSI_ISR_TXOIS_RESET 0x0 484 #define SSI_ISR_TXOIS_BITS 0x00000002 485 #define SSI_ISR_TXOIS_MSB 1 486 #define SSI_ISR_TXOIS_LSB 1 487 #define SSI_ISR_TXOIS_ACCESS "RO" 488 // ----------------------------------------------------------------------------- 489 // Field : SSI_ISR_TXEIS 490 // Description : Transmit FIFO empty interrupt status 491 #define SSI_ISR_TXEIS_RESET 0x0 492 #define SSI_ISR_TXEIS_BITS 0x00000001 493 #define SSI_ISR_TXEIS_MSB 0 494 #define SSI_ISR_TXEIS_LSB 0 495 #define SSI_ISR_TXEIS_ACCESS "RO" 496 // ============================================================================= 497 // Register : SSI_RISR 498 // Description : Raw interrupt status 499 #define SSI_RISR_OFFSET 0x00000034 500 #define SSI_RISR_BITS 0x0000003f 501 #define SSI_RISR_RESET 0x00000000 502 // ----------------------------------------------------------------------------- 503 // Field : SSI_RISR_MSTIR 504 // Description : Multi-master contention raw interrupt status 505 #define SSI_RISR_MSTIR_RESET 0x0 506 #define SSI_RISR_MSTIR_BITS 0x00000020 507 #define SSI_RISR_MSTIR_MSB 5 508 #define SSI_RISR_MSTIR_LSB 5 509 #define SSI_RISR_MSTIR_ACCESS "RO" 510 // ----------------------------------------------------------------------------- 511 // Field : SSI_RISR_RXFIR 512 // Description : Receive FIFO full raw interrupt status 513 #define SSI_RISR_RXFIR_RESET 0x0 514 #define SSI_RISR_RXFIR_BITS 0x00000010 515 #define SSI_RISR_RXFIR_MSB 4 516 #define SSI_RISR_RXFIR_LSB 4 517 #define SSI_RISR_RXFIR_ACCESS "RO" 518 // ----------------------------------------------------------------------------- 519 // Field : SSI_RISR_RXOIR 520 // Description : Receive FIFO overflow raw interrupt status 521 #define SSI_RISR_RXOIR_RESET 0x0 522 #define SSI_RISR_RXOIR_BITS 0x00000008 523 #define SSI_RISR_RXOIR_MSB 3 524 #define SSI_RISR_RXOIR_LSB 3 525 #define SSI_RISR_RXOIR_ACCESS "RO" 526 // ----------------------------------------------------------------------------- 527 // Field : SSI_RISR_RXUIR 528 // Description : Receive FIFO underflow raw interrupt status 529 #define SSI_RISR_RXUIR_RESET 0x0 530 #define SSI_RISR_RXUIR_BITS 0x00000004 531 #define SSI_RISR_RXUIR_MSB 2 532 #define SSI_RISR_RXUIR_LSB 2 533 #define SSI_RISR_RXUIR_ACCESS "RO" 534 // ----------------------------------------------------------------------------- 535 // Field : SSI_RISR_TXOIR 536 // Description : Transmit FIFO overflow raw interrupt status 537 #define SSI_RISR_TXOIR_RESET 0x0 538 #define SSI_RISR_TXOIR_BITS 0x00000002 539 #define SSI_RISR_TXOIR_MSB 1 540 #define SSI_RISR_TXOIR_LSB 1 541 #define SSI_RISR_TXOIR_ACCESS "RO" 542 // ----------------------------------------------------------------------------- 543 // Field : SSI_RISR_TXEIR 544 // Description : Transmit FIFO empty raw interrupt status 545 #define SSI_RISR_TXEIR_RESET 0x0 546 #define SSI_RISR_TXEIR_BITS 0x00000001 547 #define SSI_RISR_TXEIR_MSB 0 548 #define SSI_RISR_TXEIR_LSB 0 549 #define SSI_RISR_TXEIR_ACCESS "RO" 550 // ============================================================================= 551 // Register : SSI_TXOICR 552 // Description : TX FIFO overflow interrupt clear 553 // Clear-on-read transmit FIFO overflow interrupt 554 #define SSI_TXOICR_OFFSET 0x00000038 555 #define SSI_TXOICR_BITS 0x00000001 556 #define SSI_TXOICR_RESET 0x00000000 557 #define SSI_TXOICR_MSB 0 558 #define SSI_TXOICR_LSB 0 559 #define SSI_TXOICR_ACCESS "RO" 560 // ============================================================================= 561 // Register : SSI_RXOICR 562 // Description : RX FIFO overflow interrupt clear 563 // Clear-on-read receive FIFO overflow interrupt 564 #define SSI_RXOICR_OFFSET 0x0000003c 565 #define SSI_RXOICR_BITS 0x00000001 566 #define SSI_RXOICR_RESET 0x00000000 567 #define SSI_RXOICR_MSB 0 568 #define SSI_RXOICR_LSB 0 569 #define SSI_RXOICR_ACCESS "RO" 570 // ============================================================================= 571 // Register : SSI_RXUICR 572 // Description : RX FIFO underflow interrupt clear 573 // Clear-on-read receive FIFO underflow interrupt 574 #define SSI_RXUICR_OFFSET 0x00000040 575 #define SSI_RXUICR_BITS 0x00000001 576 #define SSI_RXUICR_RESET 0x00000000 577 #define SSI_RXUICR_MSB 0 578 #define SSI_RXUICR_LSB 0 579 #define SSI_RXUICR_ACCESS "RO" 580 // ============================================================================= 581 // Register : SSI_MSTICR 582 // Description : Multi-master interrupt clear 583 // Clear-on-read multi-master contention interrupt 584 #define SSI_MSTICR_OFFSET 0x00000044 585 #define SSI_MSTICR_BITS 0x00000001 586 #define SSI_MSTICR_RESET 0x00000000 587 #define SSI_MSTICR_MSB 0 588 #define SSI_MSTICR_LSB 0 589 #define SSI_MSTICR_ACCESS "RO" 590 // ============================================================================= 591 // Register : SSI_ICR 592 // Description : Interrupt clear 593 // Clear-on-read all active interrupts 594 #define SSI_ICR_OFFSET 0x00000048 595 #define SSI_ICR_BITS 0x00000001 596 #define SSI_ICR_RESET 0x00000000 597 #define SSI_ICR_MSB 0 598 #define SSI_ICR_LSB 0 599 #define SSI_ICR_ACCESS "RO" 600 // ============================================================================= 601 // Register : SSI_DMACR 602 // Description : DMA control 603 #define SSI_DMACR_OFFSET 0x0000004c 604 #define SSI_DMACR_BITS 0x00000003 605 #define SSI_DMACR_RESET 0x00000000 606 // ----------------------------------------------------------------------------- 607 // Field : SSI_DMACR_TDMAE 608 // Description : Transmit DMA enable 609 #define SSI_DMACR_TDMAE_RESET 0x0 610 #define SSI_DMACR_TDMAE_BITS 0x00000002 611 #define SSI_DMACR_TDMAE_MSB 1 612 #define SSI_DMACR_TDMAE_LSB 1 613 #define SSI_DMACR_TDMAE_ACCESS "RW" 614 // ----------------------------------------------------------------------------- 615 // Field : SSI_DMACR_RDMAE 616 // Description : Receive DMA enable 617 #define SSI_DMACR_RDMAE_RESET 0x0 618 #define SSI_DMACR_RDMAE_BITS 0x00000001 619 #define SSI_DMACR_RDMAE_MSB 0 620 #define SSI_DMACR_RDMAE_LSB 0 621 #define SSI_DMACR_RDMAE_ACCESS "RW" 622 // ============================================================================= 623 // Register : SSI_DMATDLR 624 // Description : DMA TX data level 625 #define SSI_DMATDLR_OFFSET 0x00000050 626 #define SSI_DMATDLR_BITS 0x000000ff 627 #define SSI_DMATDLR_RESET 0x00000000 628 // ----------------------------------------------------------------------------- 629 // Field : SSI_DMATDLR_DMATDL 630 // Description : Transmit data watermark level 631 #define SSI_DMATDLR_DMATDL_RESET 0x00 632 #define SSI_DMATDLR_DMATDL_BITS 0x000000ff 633 #define SSI_DMATDLR_DMATDL_MSB 7 634 #define SSI_DMATDLR_DMATDL_LSB 0 635 #define SSI_DMATDLR_DMATDL_ACCESS "RW" 636 // ============================================================================= 637 // Register : SSI_DMARDLR 638 // Description : DMA RX data level 639 #define SSI_DMARDLR_OFFSET 0x00000054 640 #define SSI_DMARDLR_BITS 0x000000ff 641 #define SSI_DMARDLR_RESET 0x00000000 642 // ----------------------------------------------------------------------------- 643 // Field : SSI_DMARDLR_DMARDL 644 // Description : Receive data watermark level (DMARDLR+1) 645 #define SSI_DMARDLR_DMARDL_RESET 0x00 646 #define SSI_DMARDLR_DMARDL_BITS 0x000000ff 647 #define SSI_DMARDLR_DMARDL_MSB 7 648 #define SSI_DMARDLR_DMARDL_LSB 0 649 #define SSI_DMARDLR_DMARDL_ACCESS "RW" 650 // ============================================================================= 651 // Register : SSI_IDR 652 // Description : Identification register 653 #define SSI_IDR_OFFSET 0x00000058 654 #define SSI_IDR_BITS 0xffffffff 655 #define SSI_IDR_RESET 0x51535049 656 // ----------------------------------------------------------------------------- 657 // Field : SSI_IDR_IDCODE 658 // Description : Peripheral dentification code 659 #define SSI_IDR_IDCODE_RESET 0x51535049 660 #define SSI_IDR_IDCODE_BITS 0xffffffff 661 #define SSI_IDR_IDCODE_MSB 31 662 #define SSI_IDR_IDCODE_LSB 0 663 #define SSI_IDR_IDCODE_ACCESS "RO" 664 // ============================================================================= 665 // Register : SSI_SSI_VERSION_ID 666 // Description : Version ID 667 #define SSI_SSI_VERSION_ID_OFFSET 0x0000005c 668 #define SSI_SSI_VERSION_ID_BITS 0xffffffff 669 #define SSI_SSI_VERSION_ID_RESET 0x3430312a 670 // ----------------------------------------------------------------------------- 671 // Field : SSI_SSI_VERSION_ID_SSI_COMP_VERSION 672 // Description : SNPS component version (format X.YY) 673 #define SSI_SSI_VERSION_ID_SSI_COMP_VERSION_RESET 0x3430312a 674 #define SSI_SSI_VERSION_ID_SSI_COMP_VERSION_BITS 0xffffffff 675 #define SSI_SSI_VERSION_ID_SSI_COMP_VERSION_MSB 31 676 #define SSI_SSI_VERSION_ID_SSI_COMP_VERSION_LSB 0 677 #define SSI_SSI_VERSION_ID_SSI_COMP_VERSION_ACCESS "RO" 678 // ============================================================================= 679 // Register : SSI_DR0 680 // Description : Data Register 0 (of 36) 681 #define SSI_DR0_OFFSET 0x00000060 682 #define SSI_DR0_BITS 0xffffffff 683 #define SSI_DR0_RESET 0x00000000 684 // ----------------------------------------------------------------------------- 685 // Field : SSI_DR0_DR 686 // Description : First data register of 36 687 #define SSI_DR0_DR_RESET 0x00000000 688 #define SSI_DR0_DR_BITS 0xffffffff 689 #define SSI_DR0_DR_MSB 31 690 #define SSI_DR0_DR_LSB 0 691 #define SSI_DR0_DR_ACCESS "RW" 692 // ============================================================================= 693 // Register : SSI_RX_SAMPLE_DLY 694 // Description : RX sample delay 695 #define SSI_RX_SAMPLE_DLY_OFFSET 0x000000f0 696 #define SSI_RX_SAMPLE_DLY_BITS 0x000000ff 697 #define SSI_RX_SAMPLE_DLY_RESET 0x00000000 698 // ----------------------------------------------------------------------------- 699 // Field : SSI_RX_SAMPLE_DLY_RSD 700 // Description : RXD sample delay (in SCLK cycles) 701 #define SSI_RX_SAMPLE_DLY_RSD_RESET 0x00 702 #define SSI_RX_SAMPLE_DLY_RSD_BITS 0x000000ff 703 #define SSI_RX_SAMPLE_DLY_RSD_MSB 7 704 #define SSI_RX_SAMPLE_DLY_RSD_LSB 0 705 #define SSI_RX_SAMPLE_DLY_RSD_ACCESS "RW" 706 // ============================================================================= 707 // Register : SSI_SPI_CTRLR0 708 // Description : SPI control 709 #define SSI_SPI_CTRLR0_OFFSET 0x000000f4 710 #define SSI_SPI_CTRLR0_BITS 0xff07fb3f 711 #define SSI_SPI_CTRLR0_RESET 0x03000000 712 // ----------------------------------------------------------------------------- 713 // Field : SSI_SPI_CTRLR0_XIP_CMD 714 // Description : SPI Command to send in XIP mode (INST_L = 8-bit) or to append 715 // to Address (INST_L = 0-bit) 716 #define SSI_SPI_CTRLR0_XIP_CMD_RESET 0x03 717 #define SSI_SPI_CTRLR0_XIP_CMD_BITS 0xff000000 718 #define SSI_SPI_CTRLR0_XIP_CMD_MSB 31 719 #define SSI_SPI_CTRLR0_XIP_CMD_LSB 24 720 #define SSI_SPI_CTRLR0_XIP_CMD_ACCESS "RW" 721 // ----------------------------------------------------------------------------- 722 // Field : SSI_SPI_CTRLR0_SPI_RXDS_EN 723 // Description : Read data strobe enable 724 #define SSI_SPI_CTRLR0_SPI_RXDS_EN_RESET 0x0 725 #define SSI_SPI_CTRLR0_SPI_RXDS_EN_BITS 0x00040000 726 #define SSI_SPI_CTRLR0_SPI_RXDS_EN_MSB 18 727 #define SSI_SPI_CTRLR0_SPI_RXDS_EN_LSB 18 728 #define SSI_SPI_CTRLR0_SPI_RXDS_EN_ACCESS "RW" 729 // ----------------------------------------------------------------------------- 730 // Field : SSI_SPI_CTRLR0_INST_DDR_EN 731 // Description : Instruction DDR transfer enable 732 #define SSI_SPI_CTRLR0_INST_DDR_EN_RESET 0x0 733 #define SSI_SPI_CTRLR0_INST_DDR_EN_BITS 0x00020000 734 #define SSI_SPI_CTRLR0_INST_DDR_EN_MSB 17 735 #define SSI_SPI_CTRLR0_INST_DDR_EN_LSB 17 736 #define SSI_SPI_CTRLR0_INST_DDR_EN_ACCESS "RW" 737 // ----------------------------------------------------------------------------- 738 // Field : SSI_SPI_CTRLR0_SPI_DDR_EN 739 // Description : SPI DDR transfer enable 740 #define SSI_SPI_CTRLR0_SPI_DDR_EN_RESET 0x0 741 #define SSI_SPI_CTRLR0_SPI_DDR_EN_BITS 0x00010000 742 #define SSI_SPI_CTRLR0_SPI_DDR_EN_MSB 16 743 #define SSI_SPI_CTRLR0_SPI_DDR_EN_LSB 16 744 #define SSI_SPI_CTRLR0_SPI_DDR_EN_ACCESS "RW" 745 // ----------------------------------------------------------------------------- 746 // Field : SSI_SPI_CTRLR0_WAIT_CYCLES 747 // Description : Wait cycles between control frame transmit and data reception 748 // (in SCLK cycles) 749 #define SSI_SPI_CTRLR0_WAIT_CYCLES_RESET 0x00 750 #define SSI_SPI_CTRLR0_WAIT_CYCLES_BITS 0x0000f800 751 #define SSI_SPI_CTRLR0_WAIT_CYCLES_MSB 15 752 #define SSI_SPI_CTRLR0_WAIT_CYCLES_LSB 11 753 #define SSI_SPI_CTRLR0_WAIT_CYCLES_ACCESS "RW" 754 // ----------------------------------------------------------------------------- 755 // Field : SSI_SPI_CTRLR0_INST_L 756 // Description : Instruction length (0/4/8/16b) 757 // 0x0 -> No instruction 758 // 0x1 -> 4-bit instruction 759 // 0x2 -> 8-bit instruction 760 // 0x3 -> 16-bit instruction 761 #define SSI_SPI_CTRLR0_INST_L_RESET 0x0 762 #define SSI_SPI_CTRLR0_INST_L_BITS 0x00000300 763 #define SSI_SPI_CTRLR0_INST_L_MSB 9 764 #define SSI_SPI_CTRLR0_INST_L_LSB 8 765 #define SSI_SPI_CTRLR0_INST_L_ACCESS "RW" 766 #define SSI_SPI_CTRLR0_INST_L_VALUE_NONE 0x0 767 #define SSI_SPI_CTRLR0_INST_L_VALUE_4B 0x1 768 #define SSI_SPI_CTRLR0_INST_L_VALUE_8B 0x2 769 #define SSI_SPI_CTRLR0_INST_L_VALUE_16B 0x3 770 // ----------------------------------------------------------------------------- 771 // Field : SSI_SPI_CTRLR0_ADDR_L 772 // Description : Address length (0b-60b in 4b increments) 773 #define SSI_SPI_CTRLR0_ADDR_L_RESET 0x0 774 #define SSI_SPI_CTRLR0_ADDR_L_BITS 0x0000003c 775 #define SSI_SPI_CTRLR0_ADDR_L_MSB 5 776 #define SSI_SPI_CTRLR0_ADDR_L_LSB 2 777 #define SSI_SPI_CTRLR0_ADDR_L_ACCESS "RW" 778 // ----------------------------------------------------------------------------- 779 // Field : SSI_SPI_CTRLR0_TRANS_TYPE 780 // Description : Address and instruction transfer format 781 // 0x0 -> Command and address both in standard SPI frame format 782 // 0x1 -> Command in standard SPI format, address in format 783 // specified by FRF 784 // 0x2 -> Command and address both in format specified by FRF 785 // (e.g. Dual-SPI) 786 #define SSI_SPI_CTRLR0_TRANS_TYPE_RESET 0x0 787 #define SSI_SPI_CTRLR0_TRANS_TYPE_BITS 0x00000003 788 #define SSI_SPI_CTRLR0_TRANS_TYPE_MSB 1 789 #define SSI_SPI_CTRLR0_TRANS_TYPE_LSB 0 790 #define SSI_SPI_CTRLR0_TRANS_TYPE_ACCESS "RW" 791 #define SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C1A 0x0 792 #define SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C2A 0x1 793 #define SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_2C2A 0x2 794 // ============================================================================= 795 // Register : SSI_TXD_DRIVE_EDGE 796 // Description : TX drive edge 797 #define SSI_TXD_DRIVE_EDGE_OFFSET 0x000000f8 798 #define SSI_TXD_DRIVE_EDGE_BITS 0x000000ff 799 #define SSI_TXD_DRIVE_EDGE_RESET 0x00000000 800 // ----------------------------------------------------------------------------- 801 // Field : SSI_TXD_DRIVE_EDGE_TDE 802 // Description : TXD drive edge 803 #define SSI_TXD_DRIVE_EDGE_TDE_RESET 0x00 804 #define SSI_TXD_DRIVE_EDGE_TDE_BITS 0x000000ff 805 #define SSI_TXD_DRIVE_EDGE_TDE_MSB 7 806 #define SSI_TXD_DRIVE_EDGE_TDE_LSB 0 807 #define SSI_TXD_DRIVE_EDGE_TDE_ACCESS "RW" 808 // ============================================================================= 809 #endif // HARDWARE_REGS_SSI_DEFINED 810