1 /** 2 * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 // ============================================================================= 7 // Register block : SYSCFG 8 // Version : 1 9 // Bus type : apb 10 // Description : Register block for various chip control signals 11 // ============================================================================= 12 #ifndef HARDWARE_REGS_SYSCFG_DEFINED 13 #define HARDWARE_REGS_SYSCFG_DEFINED 14 // ============================================================================= 15 // Register : SYSCFG_PROC0_NMI_MASK 16 // Description : Processor core 0 NMI source mask 17 // Set a bit high to enable NMI from that IRQ 18 #define SYSCFG_PROC0_NMI_MASK_OFFSET 0x00000000 19 #define SYSCFG_PROC0_NMI_MASK_BITS 0xffffffff 20 #define SYSCFG_PROC0_NMI_MASK_RESET 0x00000000 21 #define SYSCFG_PROC0_NMI_MASK_MSB 31 22 #define SYSCFG_PROC0_NMI_MASK_LSB 0 23 #define SYSCFG_PROC0_NMI_MASK_ACCESS "RW" 24 // ============================================================================= 25 // Register : SYSCFG_PROC1_NMI_MASK 26 // Description : Processor core 1 NMI source mask 27 // Set a bit high to enable NMI from that IRQ 28 #define SYSCFG_PROC1_NMI_MASK_OFFSET 0x00000004 29 #define SYSCFG_PROC1_NMI_MASK_BITS 0xffffffff 30 #define SYSCFG_PROC1_NMI_MASK_RESET 0x00000000 31 #define SYSCFG_PROC1_NMI_MASK_MSB 31 32 #define SYSCFG_PROC1_NMI_MASK_LSB 0 33 #define SYSCFG_PROC1_NMI_MASK_ACCESS "RW" 34 // ============================================================================= 35 // Register : SYSCFG_PROC_CONFIG 36 // Description : Configuration for processors 37 #define SYSCFG_PROC_CONFIG_OFFSET 0x00000008 38 #define SYSCFG_PROC_CONFIG_BITS 0xff000003 39 #define SYSCFG_PROC_CONFIG_RESET 0x10000000 40 // ----------------------------------------------------------------------------- 41 // Field : SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID 42 // Description : Configure proc1 DAP instance ID. 43 // Recommend that this is NOT changed until you require debug 44 // access in multi-chip environment 45 // WARNING: do not set to 15 as this is reserved for RescueDP 46 #define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_RESET 0x1 47 #define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_BITS 0xf0000000 48 #define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_MSB 31 49 #define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_LSB 28 50 #define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_ACCESS "RW" 51 // ----------------------------------------------------------------------------- 52 // Field : SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID 53 // Description : Configure proc0 DAP instance ID. 54 // Recommend that this is NOT changed until you require debug 55 // access in multi-chip environment 56 // WARNING: do not set to 15 as this is reserved for RescueDP 57 #define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_RESET 0x0 58 #define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_BITS 0x0f000000 59 #define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_MSB 27 60 #define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_LSB 24 61 #define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_ACCESS "RW" 62 // ----------------------------------------------------------------------------- 63 // Field : SYSCFG_PROC_CONFIG_PROC1_HALTED 64 // Description : Indication that proc1 has halted 65 #define SYSCFG_PROC_CONFIG_PROC1_HALTED_RESET 0x0 66 #define SYSCFG_PROC_CONFIG_PROC1_HALTED_BITS 0x00000002 67 #define SYSCFG_PROC_CONFIG_PROC1_HALTED_MSB 1 68 #define SYSCFG_PROC_CONFIG_PROC1_HALTED_LSB 1 69 #define SYSCFG_PROC_CONFIG_PROC1_HALTED_ACCESS "RO" 70 // ----------------------------------------------------------------------------- 71 // Field : SYSCFG_PROC_CONFIG_PROC0_HALTED 72 // Description : Indication that proc0 has halted 73 #define SYSCFG_PROC_CONFIG_PROC0_HALTED_RESET 0x0 74 #define SYSCFG_PROC_CONFIG_PROC0_HALTED_BITS 0x00000001 75 #define SYSCFG_PROC_CONFIG_PROC0_HALTED_MSB 0 76 #define SYSCFG_PROC_CONFIG_PROC0_HALTED_LSB 0 77 #define SYSCFG_PROC_CONFIG_PROC0_HALTED_ACCESS "RO" 78 // ============================================================================= 79 // Register : SYSCFG_PROC_IN_SYNC_BYPASS 80 // Description : For each bit, if 1, bypass the input synchronizer between that 81 // GPIO 82 // and the GPIO input register in the SIO. The input synchronizers 83 // should 84 // generally be unbypassed, to avoid injecting metastabilities 85 // into processors. 86 // If you're feeling brave, you can bypass to save two cycles of 87 // input 88 // latency. This register applies to GPIO 0...29. 89 #define SYSCFG_PROC_IN_SYNC_BYPASS_OFFSET 0x0000000c 90 #define SYSCFG_PROC_IN_SYNC_BYPASS_BITS 0x3fffffff 91 #define SYSCFG_PROC_IN_SYNC_BYPASS_RESET 0x00000000 92 #define SYSCFG_PROC_IN_SYNC_BYPASS_MSB 29 93 #define SYSCFG_PROC_IN_SYNC_BYPASS_LSB 0 94 #define SYSCFG_PROC_IN_SYNC_BYPASS_ACCESS "RW" 95 // ============================================================================= 96 // Register : SYSCFG_PROC_IN_SYNC_BYPASS_HI 97 // Description : For each bit, if 1, bypass the input synchronizer between that 98 // GPIO 99 // and the GPIO input register in the SIO. The input synchronizers 100 // should 101 // generally be unbypassed, to avoid injecting metastabilities 102 // into processors. 103 // If you're feeling brave, you can bypass to save two cycles of 104 // input 105 // latency. This register applies to GPIO 30...35 (the QSPI IOs). 106 #define SYSCFG_PROC_IN_SYNC_BYPASS_HI_OFFSET 0x00000010 107 #define SYSCFG_PROC_IN_SYNC_BYPASS_HI_BITS 0x0000003f 108 #define SYSCFG_PROC_IN_SYNC_BYPASS_HI_RESET 0x00000000 109 #define SYSCFG_PROC_IN_SYNC_BYPASS_HI_MSB 5 110 #define SYSCFG_PROC_IN_SYNC_BYPASS_HI_LSB 0 111 #define SYSCFG_PROC_IN_SYNC_BYPASS_HI_ACCESS "RW" 112 // ============================================================================= 113 // Register : SYSCFG_DBGFORCE 114 // Description : Directly control the SWD debug port of either processor 115 #define SYSCFG_DBGFORCE_OFFSET 0x00000014 116 #define SYSCFG_DBGFORCE_BITS 0x000000ff 117 #define SYSCFG_DBGFORCE_RESET 0x00000066 118 // ----------------------------------------------------------------------------- 119 // Field : SYSCFG_DBGFORCE_PROC1_ATTACH 120 // Description : Attach processor 1 debug port to syscfg controls, and 121 // disconnect it from external SWD pads. 122 #define SYSCFG_DBGFORCE_PROC1_ATTACH_RESET 0x0 123 #define SYSCFG_DBGFORCE_PROC1_ATTACH_BITS 0x00000080 124 #define SYSCFG_DBGFORCE_PROC1_ATTACH_MSB 7 125 #define SYSCFG_DBGFORCE_PROC1_ATTACH_LSB 7 126 #define SYSCFG_DBGFORCE_PROC1_ATTACH_ACCESS "RW" 127 // ----------------------------------------------------------------------------- 128 // Field : SYSCFG_DBGFORCE_PROC1_SWCLK 129 // Description : Directly drive processor 1 SWCLK, if PROC1_ATTACH is set 130 #define SYSCFG_DBGFORCE_PROC1_SWCLK_RESET 0x1 131 #define SYSCFG_DBGFORCE_PROC1_SWCLK_BITS 0x00000040 132 #define SYSCFG_DBGFORCE_PROC1_SWCLK_MSB 6 133 #define SYSCFG_DBGFORCE_PROC1_SWCLK_LSB 6 134 #define SYSCFG_DBGFORCE_PROC1_SWCLK_ACCESS "RW" 135 // ----------------------------------------------------------------------------- 136 // Field : SYSCFG_DBGFORCE_PROC1_SWDI 137 // Description : Directly drive processor 1 SWDIO input, if PROC1_ATTACH is set 138 #define SYSCFG_DBGFORCE_PROC1_SWDI_RESET 0x1 139 #define SYSCFG_DBGFORCE_PROC1_SWDI_BITS 0x00000020 140 #define SYSCFG_DBGFORCE_PROC1_SWDI_MSB 5 141 #define SYSCFG_DBGFORCE_PROC1_SWDI_LSB 5 142 #define SYSCFG_DBGFORCE_PROC1_SWDI_ACCESS "RW" 143 // ----------------------------------------------------------------------------- 144 // Field : SYSCFG_DBGFORCE_PROC1_SWDO 145 // Description : Observe the value of processor 1 SWDIO output. 146 #define SYSCFG_DBGFORCE_PROC1_SWDO_RESET "-" 147 #define SYSCFG_DBGFORCE_PROC1_SWDO_BITS 0x00000010 148 #define SYSCFG_DBGFORCE_PROC1_SWDO_MSB 4 149 #define SYSCFG_DBGFORCE_PROC1_SWDO_LSB 4 150 #define SYSCFG_DBGFORCE_PROC1_SWDO_ACCESS "RO" 151 // ----------------------------------------------------------------------------- 152 // Field : SYSCFG_DBGFORCE_PROC0_ATTACH 153 // Description : Attach processor 0 debug port to syscfg controls, and 154 // disconnect it from external SWD pads. 155 #define SYSCFG_DBGFORCE_PROC0_ATTACH_RESET 0x0 156 #define SYSCFG_DBGFORCE_PROC0_ATTACH_BITS 0x00000008 157 #define SYSCFG_DBGFORCE_PROC0_ATTACH_MSB 3 158 #define SYSCFG_DBGFORCE_PROC0_ATTACH_LSB 3 159 #define SYSCFG_DBGFORCE_PROC0_ATTACH_ACCESS "RW" 160 // ----------------------------------------------------------------------------- 161 // Field : SYSCFG_DBGFORCE_PROC0_SWCLK 162 // Description : Directly drive processor 0 SWCLK, if PROC0_ATTACH is set 163 #define SYSCFG_DBGFORCE_PROC0_SWCLK_RESET 0x1 164 #define SYSCFG_DBGFORCE_PROC0_SWCLK_BITS 0x00000004 165 #define SYSCFG_DBGFORCE_PROC0_SWCLK_MSB 2 166 #define SYSCFG_DBGFORCE_PROC0_SWCLK_LSB 2 167 #define SYSCFG_DBGFORCE_PROC0_SWCLK_ACCESS "RW" 168 // ----------------------------------------------------------------------------- 169 // Field : SYSCFG_DBGFORCE_PROC0_SWDI 170 // Description : Directly drive processor 0 SWDIO input, if PROC0_ATTACH is set 171 #define SYSCFG_DBGFORCE_PROC0_SWDI_RESET 0x1 172 #define SYSCFG_DBGFORCE_PROC0_SWDI_BITS 0x00000002 173 #define SYSCFG_DBGFORCE_PROC0_SWDI_MSB 1 174 #define SYSCFG_DBGFORCE_PROC0_SWDI_LSB 1 175 #define SYSCFG_DBGFORCE_PROC0_SWDI_ACCESS "RW" 176 // ----------------------------------------------------------------------------- 177 // Field : SYSCFG_DBGFORCE_PROC0_SWDO 178 // Description : Observe the value of processor 0 SWDIO output. 179 #define SYSCFG_DBGFORCE_PROC0_SWDO_RESET "-" 180 #define SYSCFG_DBGFORCE_PROC0_SWDO_BITS 0x00000001 181 #define SYSCFG_DBGFORCE_PROC0_SWDO_MSB 0 182 #define SYSCFG_DBGFORCE_PROC0_SWDO_LSB 0 183 #define SYSCFG_DBGFORCE_PROC0_SWDO_ACCESS "RO" 184 // ============================================================================= 185 // Register : SYSCFG_MEMPOWERDOWN 186 // Description : Control power downs to memories. Set high to power down 187 // memories. 188 // Use with extreme caution 189 #define SYSCFG_MEMPOWERDOWN_OFFSET 0x00000018 190 #define SYSCFG_MEMPOWERDOWN_BITS 0x000000ff 191 #define SYSCFG_MEMPOWERDOWN_RESET 0x00000000 192 // ----------------------------------------------------------------------------- 193 // Field : SYSCFG_MEMPOWERDOWN_ROM 194 // Description : None 195 #define SYSCFG_MEMPOWERDOWN_ROM_RESET 0x0 196 #define SYSCFG_MEMPOWERDOWN_ROM_BITS 0x00000080 197 #define SYSCFG_MEMPOWERDOWN_ROM_MSB 7 198 #define SYSCFG_MEMPOWERDOWN_ROM_LSB 7 199 #define SYSCFG_MEMPOWERDOWN_ROM_ACCESS "RW" 200 // ----------------------------------------------------------------------------- 201 // Field : SYSCFG_MEMPOWERDOWN_USB 202 // Description : None 203 #define SYSCFG_MEMPOWERDOWN_USB_RESET 0x0 204 #define SYSCFG_MEMPOWERDOWN_USB_BITS 0x00000040 205 #define SYSCFG_MEMPOWERDOWN_USB_MSB 6 206 #define SYSCFG_MEMPOWERDOWN_USB_LSB 6 207 #define SYSCFG_MEMPOWERDOWN_USB_ACCESS "RW" 208 // ----------------------------------------------------------------------------- 209 // Field : SYSCFG_MEMPOWERDOWN_SRAM5 210 // Description : None 211 #define SYSCFG_MEMPOWERDOWN_SRAM5_RESET 0x0 212 #define SYSCFG_MEMPOWERDOWN_SRAM5_BITS 0x00000020 213 #define SYSCFG_MEMPOWERDOWN_SRAM5_MSB 5 214 #define SYSCFG_MEMPOWERDOWN_SRAM5_LSB 5 215 #define SYSCFG_MEMPOWERDOWN_SRAM5_ACCESS "RW" 216 // ----------------------------------------------------------------------------- 217 // Field : SYSCFG_MEMPOWERDOWN_SRAM4 218 // Description : None 219 #define SYSCFG_MEMPOWERDOWN_SRAM4_RESET 0x0 220 #define SYSCFG_MEMPOWERDOWN_SRAM4_BITS 0x00000010 221 #define SYSCFG_MEMPOWERDOWN_SRAM4_MSB 4 222 #define SYSCFG_MEMPOWERDOWN_SRAM4_LSB 4 223 #define SYSCFG_MEMPOWERDOWN_SRAM4_ACCESS "RW" 224 // ----------------------------------------------------------------------------- 225 // Field : SYSCFG_MEMPOWERDOWN_SRAM3 226 // Description : None 227 #define SYSCFG_MEMPOWERDOWN_SRAM3_RESET 0x0 228 #define SYSCFG_MEMPOWERDOWN_SRAM3_BITS 0x00000008 229 #define SYSCFG_MEMPOWERDOWN_SRAM3_MSB 3 230 #define SYSCFG_MEMPOWERDOWN_SRAM3_LSB 3 231 #define SYSCFG_MEMPOWERDOWN_SRAM3_ACCESS "RW" 232 // ----------------------------------------------------------------------------- 233 // Field : SYSCFG_MEMPOWERDOWN_SRAM2 234 // Description : None 235 #define SYSCFG_MEMPOWERDOWN_SRAM2_RESET 0x0 236 #define SYSCFG_MEMPOWERDOWN_SRAM2_BITS 0x00000004 237 #define SYSCFG_MEMPOWERDOWN_SRAM2_MSB 2 238 #define SYSCFG_MEMPOWERDOWN_SRAM2_LSB 2 239 #define SYSCFG_MEMPOWERDOWN_SRAM2_ACCESS "RW" 240 // ----------------------------------------------------------------------------- 241 // Field : SYSCFG_MEMPOWERDOWN_SRAM1 242 // Description : None 243 #define SYSCFG_MEMPOWERDOWN_SRAM1_RESET 0x0 244 #define SYSCFG_MEMPOWERDOWN_SRAM1_BITS 0x00000002 245 #define SYSCFG_MEMPOWERDOWN_SRAM1_MSB 1 246 #define SYSCFG_MEMPOWERDOWN_SRAM1_LSB 1 247 #define SYSCFG_MEMPOWERDOWN_SRAM1_ACCESS "RW" 248 // ----------------------------------------------------------------------------- 249 // Field : SYSCFG_MEMPOWERDOWN_SRAM0 250 // Description : None 251 #define SYSCFG_MEMPOWERDOWN_SRAM0_RESET 0x0 252 #define SYSCFG_MEMPOWERDOWN_SRAM0_BITS 0x00000001 253 #define SYSCFG_MEMPOWERDOWN_SRAM0_MSB 0 254 #define SYSCFG_MEMPOWERDOWN_SRAM0_LSB 0 255 #define SYSCFG_MEMPOWERDOWN_SRAM0_ACCESS "RW" 256 // ============================================================================= 257 #endif // HARDWARE_REGS_SYSCFG_DEFINED 258