1 /** 2 * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 // ============================================================================= 7 // Register block : TIMER 8 // Version : 1 9 // Bus type : apb 10 // Description : Controls time and alarms 11 // time is a 64 bit value indicating the time in usec since 12 // power-on 13 // timeh is the top 32 bits of time & timel is the bottom 32 14 // bits 15 // to change time write to timelw before timehw 16 // to read time read from timelr before timehr 17 // An alarm is set by setting alarm_enable and writing to the 18 // corresponding alarm register 19 // When an alarm is pending, the corresponding alarm_running 20 // signal will be high 21 // An alarm can be cancelled before it has finished by clearing 22 // the alarm_enable 23 // When an alarm fires, the corresponding alarm_irq is set and 24 // alarm_running is cleared 25 // To clear the interrupt write a 1 to the corresponding 26 // alarm_irq 27 // ============================================================================= 28 #ifndef HARDWARE_REGS_TIMER_DEFINED 29 #define HARDWARE_REGS_TIMER_DEFINED 30 // ============================================================================= 31 // Register : TIMER_TIMEHW 32 // Description : Write to bits 63:32 of time 33 // always write timelw before timehw 34 #define TIMER_TIMEHW_OFFSET 0x00000000 35 #define TIMER_TIMEHW_BITS 0xffffffff 36 #define TIMER_TIMEHW_RESET 0x00000000 37 #define TIMER_TIMEHW_MSB 31 38 #define TIMER_TIMEHW_LSB 0 39 #define TIMER_TIMEHW_ACCESS "WF" 40 // ============================================================================= 41 // Register : TIMER_TIMELW 42 // Description : Write to bits 31:0 of time 43 // writes do not get copied to time until timehw is written 44 #define TIMER_TIMELW_OFFSET 0x00000004 45 #define TIMER_TIMELW_BITS 0xffffffff 46 #define TIMER_TIMELW_RESET 0x00000000 47 #define TIMER_TIMELW_MSB 31 48 #define TIMER_TIMELW_LSB 0 49 #define TIMER_TIMELW_ACCESS "WF" 50 // ============================================================================= 51 // Register : TIMER_TIMEHR 52 // Description : Read from bits 63:32 of time 53 // always read timelr before timehr 54 #define TIMER_TIMEHR_OFFSET 0x00000008 55 #define TIMER_TIMEHR_BITS 0xffffffff 56 #define TIMER_TIMEHR_RESET 0x00000000 57 #define TIMER_TIMEHR_MSB 31 58 #define TIMER_TIMEHR_LSB 0 59 #define TIMER_TIMEHR_ACCESS "RO" 60 // ============================================================================= 61 // Register : TIMER_TIMELR 62 // Description : Read from bits 31:0 of time 63 #define TIMER_TIMELR_OFFSET 0x0000000c 64 #define TIMER_TIMELR_BITS 0xffffffff 65 #define TIMER_TIMELR_RESET 0x00000000 66 #define TIMER_TIMELR_MSB 31 67 #define TIMER_TIMELR_LSB 0 68 #define TIMER_TIMELR_ACCESS "RO" 69 // ============================================================================= 70 // Register : TIMER_ALARM0 71 // Description : Arm alarm 0, and configure the time it will fire. 72 // Once armed, the alarm fires when TIMER_ALARM0 == TIMELR. 73 // The alarm will disarm itself once it fires, and can 74 // be disarmed early using the ARMED status register. 75 #define TIMER_ALARM0_OFFSET 0x00000010 76 #define TIMER_ALARM0_BITS 0xffffffff 77 #define TIMER_ALARM0_RESET 0x00000000 78 #define TIMER_ALARM0_MSB 31 79 #define TIMER_ALARM0_LSB 0 80 #define TIMER_ALARM0_ACCESS "RW" 81 // ============================================================================= 82 // Register : TIMER_ALARM1 83 // Description : Arm alarm 1, and configure the time it will fire. 84 // Once armed, the alarm fires when TIMER_ALARM1 == TIMELR. 85 // The alarm will disarm itself once it fires, and can 86 // be disarmed early using the ARMED status register. 87 #define TIMER_ALARM1_OFFSET 0x00000014 88 #define TIMER_ALARM1_BITS 0xffffffff 89 #define TIMER_ALARM1_RESET 0x00000000 90 #define TIMER_ALARM1_MSB 31 91 #define TIMER_ALARM1_LSB 0 92 #define TIMER_ALARM1_ACCESS "RW" 93 // ============================================================================= 94 // Register : TIMER_ALARM2 95 // Description : Arm alarm 2, and configure the time it will fire. 96 // Once armed, the alarm fires when TIMER_ALARM2 == TIMELR. 97 // The alarm will disarm itself once it fires, and can 98 // be disarmed early using the ARMED status register. 99 #define TIMER_ALARM2_OFFSET 0x00000018 100 #define TIMER_ALARM2_BITS 0xffffffff 101 #define TIMER_ALARM2_RESET 0x00000000 102 #define TIMER_ALARM2_MSB 31 103 #define TIMER_ALARM2_LSB 0 104 #define TIMER_ALARM2_ACCESS "RW" 105 // ============================================================================= 106 // Register : TIMER_ALARM3 107 // Description : Arm alarm 3, and configure the time it will fire. 108 // Once armed, the alarm fires when TIMER_ALARM3 == TIMELR. 109 // The alarm will disarm itself once it fires, and can 110 // be disarmed early using the ARMED status register. 111 #define TIMER_ALARM3_OFFSET 0x0000001c 112 #define TIMER_ALARM3_BITS 0xffffffff 113 #define TIMER_ALARM3_RESET 0x00000000 114 #define TIMER_ALARM3_MSB 31 115 #define TIMER_ALARM3_LSB 0 116 #define TIMER_ALARM3_ACCESS "RW" 117 // ============================================================================= 118 // Register : TIMER_ARMED 119 // Description : Indicates the armed/disarmed status of each alarm. 120 // A write to the corresponding ALARMx register arms the alarm. 121 // Alarms automatically disarm upon firing, but writing ones here 122 // will disarm immediately without waiting to fire. 123 #define TIMER_ARMED_OFFSET 0x00000020 124 #define TIMER_ARMED_BITS 0x0000000f 125 #define TIMER_ARMED_RESET 0x00000000 126 #define TIMER_ARMED_MSB 3 127 #define TIMER_ARMED_LSB 0 128 #define TIMER_ARMED_ACCESS "WC" 129 // ============================================================================= 130 // Register : TIMER_TIMERAWH 131 // Description : Raw read from bits 63:32 of time (no side effects) 132 #define TIMER_TIMERAWH_OFFSET 0x00000024 133 #define TIMER_TIMERAWH_BITS 0xffffffff 134 #define TIMER_TIMERAWH_RESET 0x00000000 135 #define TIMER_TIMERAWH_MSB 31 136 #define TIMER_TIMERAWH_LSB 0 137 #define TIMER_TIMERAWH_ACCESS "RO" 138 // ============================================================================= 139 // Register : TIMER_TIMERAWL 140 // Description : Raw read from bits 31:0 of time (no side effects) 141 #define TIMER_TIMERAWL_OFFSET 0x00000028 142 #define TIMER_TIMERAWL_BITS 0xffffffff 143 #define TIMER_TIMERAWL_RESET 0x00000000 144 #define TIMER_TIMERAWL_MSB 31 145 #define TIMER_TIMERAWL_LSB 0 146 #define TIMER_TIMERAWL_ACCESS "RO" 147 // ============================================================================= 148 // Register : TIMER_DBGPAUSE 149 // Description : Set bits high to enable pause when the corresponding debug 150 // ports are active 151 #define TIMER_DBGPAUSE_OFFSET 0x0000002c 152 #define TIMER_DBGPAUSE_BITS 0x00000006 153 #define TIMER_DBGPAUSE_RESET 0x00000007 154 // ----------------------------------------------------------------------------- 155 // Field : TIMER_DBGPAUSE_DBG1 156 // Description : Pause when processor 1 is in debug mode 157 #define TIMER_DBGPAUSE_DBG1_RESET 0x1 158 #define TIMER_DBGPAUSE_DBG1_BITS 0x00000004 159 #define TIMER_DBGPAUSE_DBG1_MSB 2 160 #define TIMER_DBGPAUSE_DBG1_LSB 2 161 #define TIMER_DBGPAUSE_DBG1_ACCESS "RW" 162 // ----------------------------------------------------------------------------- 163 // Field : TIMER_DBGPAUSE_DBG0 164 // Description : Pause when processor 0 is in debug mode 165 #define TIMER_DBGPAUSE_DBG0_RESET 0x1 166 #define TIMER_DBGPAUSE_DBG0_BITS 0x00000002 167 #define TIMER_DBGPAUSE_DBG0_MSB 1 168 #define TIMER_DBGPAUSE_DBG0_LSB 1 169 #define TIMER_DBGPAUSE_DBG0_ACCESS "RW" 170 // ============================================================================= 171 // Register : TIMER_PAUSE 172 // Description : Set high to pause the timer 173 #define TIMER_PAUSE_OFFSET 0x00000030 174 #define TIMER_PAUSE_BITS 0x00000001 175 #define TIMER_PAUSE_RESET 0x00000000 176 #define TIMER_PAUSE_MSB 0 177 #define TIMER_PAUSE_LSB 0 178 #define TIMER_PAUSE_ACCESS "RW" 179 // ============================================================================= 180 // Register : TIMER_INTR 181 // Description : Raw Interrupts 182 #define TIMER_INTR_OFFSET 0x00000034 183 #define TIMER_INTR_BITS 0x0000000f 184 #define TIMER_INTR_RESET 0x00000000 185 // ----------------------------------------------------------------------------- 186 // Field : TIMER_INTR_ALARM_3 187 // Description : None 188 #define TIMER_INTR_ALARM_3_RESET 0x0 189 #define TIMER_INTR_ALARM_3_BITS 0x00000008 190 #define TIMER_INTR_ALARM_3_MSB 3 191 #define TIMER_INTR_ALARM_3_LSB 3 192 #define TIMER_INTR_ALARM_3_ACCESS "WC" 193 // ----------------------------------------------------------------------------- 194 // Field : TIMER_INTR_ALARM_2 195 // Description : None 196 #define TIMER_INTR_ALARM_2_RESET 0x0 197 #define TIMER_INTR_ALARM_2_BITS 0x00000004 198 #define TIMER_INTR_ALARM_2_MSB 2 199 #define TIMER_INTR_ALARM_2_LSB 2 200 #define TIMER_INTR_ALARM_2_ACCESS "WC" 201 // ----------------------------------------------------------------------------- 202 // Field : TIMER_INTR_ALARM_1 203 // Description : None 204 #define TIMER_INTR_ALARM_1_RESET 0x0 205 #define TIMER_INTR_ALARM_1_BITS 0x00000002 206 #define TIMER_INTR_ALARM_1_MSB 1 207 #define TIMER_INTR_ALARM_1_LSB 1 208 #define TIMER_INTR_ALARM_1_ACCESS "WC" 209 // ----------------------------------------------------------------------------- 210 // Field : TIMER_INTR_ALARM_0 211 // Description : None 212 #define TIMER_INTR_ALARM_0_RESET 0x0 213 #define TIMER_INTR_ALARM_0_BITS 0x00000001 214 #define TIMER_INTR_ALARM_0_MSB 0 215 #define TIMER_INTR_ALARM_0_LSB 0 216 #define TIMER_INTR_ALARM_0_ACCESS "WC" 217 // ============================================================================= 218 // Register : TIMER_INTE 219 // Description : Interrupt Enable 220 #define TIMER_INTE_OFFSET 0x00000038 221 #define TIMER_INTE_BITS 0x0000000f 222 #define TIMER_INTE_RESET 0x00000000 223 // ----------------------------------------------------------------------------- 224 // Field : TIMER_INTE_ALARM_3 225 // Description : None 226 #define TIMER_INTE_ALARM_3_RESET 0x0 227 #define TIMER_INTE_ALARM_3_BITS 0x00000008 228 #define TIMER_INTE_ALARM_3_MSB 3 229 #define TIMER_INTE_ALARM_3_LSB 3 230 #define TIMER_INTE_ALARM_3_ACCESS "RW" 231 // ----------------------------------------------------------------------------- 232 // Field : TIMER_INTE_ALARM_2 233 // Description : None 234 #define TIMER_INTE_ALARM_2_RESET 0x0 235 #define TIMER_INTE_ALARM_2_BITS 0x00000004 236 #define TIMER_INTE_ALARM_2_MSB 2 237 #define TIMER_INTE_ALARM_2_LSB 2 238 #define TIMER_INTE_ALARM_2_ACCESS "RW" 239 // ----------------------------------------------------------------------------- 240 // Field : TIMER_INTE_ALARM_1 241 // Description : None 242 #define TIMER_INTE_ALARM_1_RESET 0x0 243 #define TIMER_INTE_ALARM_1_BITS 0x00000002 244 #define TIMER_INTE_ALARM_1_MSB 1 245 #define TIMER_INTE_ALARM_1_LSB 1 246 #define TIMER_INTE_ALARM_1_ACCESS "RW" 247 // ----------------------------------------------------------------------------- 248 // Field : TIMER_INTE_ALARM_0 249 // Description : None 250 #define TIMER_INTE_ALARM_0_RESET 0x0 251 #define TIMER_INTE_ALARM_0_BITS 0x00000001 252 #define TIMER_INTE_ALARM_0_MSB 0 253 #define TIMER_INTE_ALARM_0_LSB 0 254 #define TIMER_INTE_ALARM_0_ACCESS "RW" 255 // ============================================================================= 256 // Register : TIMER_INTF 257 // Description : Interrupt Force 258 #define TIMER_INTF_OFFSET 0x0000003c 259 #define TIMER_INTF_BITS 0x0000000f 260 #define TIMER_INTF_RESET 0x00000000 261 // ----------------------------------------------------------------------------- 262 // Field : TIMER_INTF_ALARM_3 263 // Description : None 264 #define TIMER_INTF_ALARM_3_RESET 0x0 265 #define TIMER_INTF_ALARM_3_BITS 0x00000008 266 #define TIMER_INTF_ALARM_3_MSB 3 267 #define TIMER_INTF_ALARM_3_LSB 3 268 #define TIMER_INTF_ALARM_3_ACCESS "RW" 269 // ----------------------------------------------------------------------------- 270 // Field : TIMER_INTF_ALARM_2 271 // Description : None 272 #define TIMER_INTF_ALARM_2_RESET 0x0 273 #define TIMER_INTF_ALARM_2_BITS 0x00000004 274 #define TIMER_INTF_ALARM_2_MSB 2 275 #define TIMER_INTF_ALARM_2_LSB 2 276 #define TIMER_INTF_ALARM_2_ACCESS "RW" 277 // ----------------------------------------------------------------------------- 278 // Field : TIMER_INTF_ALARM_1 279 // Description : None 280 #define TIMER_INTF_ALARM_1_RESET 0x0 281 #define TIMER_INTF_ALARM_1_BITS 0x00000002 282 #define TIMER_INTF_ALARM_1_MSB 1 283 #define TIMER_INTF_ALARM_1_LSB 1 284 #define TIMER_INTF_ALARM_1_ACCESS "RW" 285 // ----------------------------------------------------------------------------- 286 // Field : TIMER_INTF_ALARM_0 287 // Description : None 288 #define TIMER_INTF_ALARM_0_RESET 0x0 289 #define TIMER_INTF_ALARM_0_BITS 0x00000001 290 #define TIMER_INTF_ALARM_0_MSB 0 291 #define TIMER_INTF_ALARM_0_LSB 0 292 #define TIMER_INTF_ALARM_0_ACCESS "RW" 293 // ============================================================================= 294 // Register : TIMER_INTS 295 // Description : Interrupt status after masking & forcing 296 #define TIMER_INTS_OFFSET 0x00000040 297 #define TIMER_INTS_BITS 0x0000000f 298 #define TIMER_INTS_RESET 0x00000000 299 // ----------------------------------------------------------------------------- 300 // Field : TIMER_INTS_ALARM_3 301 // Description : None 302 #define TIMER_INTS_ALARM_3_RESET 0x0 303 #define TIMER_INTS_ALARM_3_BITS 0x00000008 304 #define TIMER_INTS_ALARM_3_MSB 3 305 #define TIMER_INTS_ALARM_3_LSB 3 306 #define TIMER_INTS_ALARM_3_ACCESS "RO" 307 // ----------------------------------------------------------------------------- 308 // Field : TIMER_INTS_ALARM_2 309 // Description : None 310 #define TIMER_INTS_ALARM_2_RESET 0x0 311 #define TIMER_INTS_ALARM_2_BITS 0x00000004 312 #define TIMER_INTS_ALARM_2_MSB 2 313 #define TIMER_INTS_ALARM_2_LSB 2 314 #define TIMER_INTS_ALARM_2_ACCESS "RO" 315 // ----------------------------------------------------------------------------- 316 // Field : TIMER_INTS_ALARM_1 317 // Description : None 318 #define TIMER_INTS_ALARM_1_RESET 0x0 319 #define TIMER_INTS_ALARM_1_BITS 0x00000002 320 #define TIMER_INTS_ALARM_1_MSB 1 321 #define TIMER_INTS_ALARM_1_LSB 1 322 #define TIMER_INTS_ALARM_1_ACCESS "RO" 323 // ----------------------------------------------------------------------------- 324 // Field : TIMER_INTS_ALARM_0 325 // Description : None 326 #define TIMER_INTS_ALARM_0_RESET 0x0 327 #define TIMER_INTS_ALARM_0_BITS 0x00000001 328 #define TIMER_INTS_ALARM_0_MSB 0 329 #define TIMER_INTS_ALARM_0_LSB 0 330 #define TIMER_INTS_ALARM_0_ACCESS "RO" 331 // ============================================================================= 332 #endif // HARDWARE_REGS_TIMER_DEFINED 333