1 /** 2 * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 // ============================================================================= 7 // Register block : WATCHDOG 8 // Version : 1 9 // Bus type : apb 10 // Description : None 11 // ============================================================================= 12 #ifndef HARDWARE_REGS_WATCHDOG_DEFINED 13 #define HARDWARE_REGS_WATCHDOG_DEFINED 14 // ============================================================================= 15 // Register : WATCHDOG_CTRL 16 // Description : Watchdog control 17 // The rst_wdsel register determines which subsystems are reset 18 // when the watchdog is triggered. 19 // The watchdog can be triggered in software. 20 #define WATCHDOG_CTRL_OFFSET 0x00000000 21 #define WATCHDOG_CTRL_BITS 0xc7ffffff 22 #define WATCHDOG_CTRL_RESET 0x07000000 23 // ----------------------------------------------------------------------------- 24 // Field : WATCHDOG_CTRL_TRIGGER 25 // Description : Trigger a watchdog reset 26 #define WATCHDOG_CTRL_TRIGGER_RESET 0x0 27 #define WATCHDOG_CTRL_TRIGGER_BITS 0x80000000 28 #define WATCHDOG_CTRL_TRIGGER_MSB 31 29 #define WATCHDOG_CTRL_TRIGGER_LSB 31 30 #define WATCHDOG_CTRL_TRIGGER_ACCESS "SC" 31 // ----------------------------------------------------------------------------- 32 // Field : WATCHDOG_CTRL_ENABLE 33 // Description : When not enabled the watchdog timer is paused 34 #define WATCHDOG_CTRL_ENABLE_RESET 0x0 35 #define WATCHDOG_CTRL_ENABLE_BITS 0x40000000 36 #define WATCHDOG_CTRL_ENABLE_MSB 30 37 #define WATCHDOG_CTRL_ENABLE_LSB 30 38 #define WATCHDOG_CTRL_ENABLE_ACCESS "RW" 39 // ----------------------------------------------------------------------------- 40 // Field : WATCHDOG_CTRL_PAUSE_DBG1 41 // Description : Pause the watchdog timer when processor 1 is in debug mode 42 #define WATCHDOG_CTRL_PAUSE_DBG1_RESET 0x1 43 #define WATCHDOG_CTRL_PAUSE_DBG1_BITS 0x04000000 44 #define WATCHDOG_CTRL_PAUSE_DBG1_MSB 26 45 #define WATCHDOG_CTRL_PAUSE_DBG1_LSB 26 46 #define WATCHDOG_CTRL_PAUSE_DBG1_ACCESS "RW" 47 // ----------------------------------------------------------------------------- 48 // Field : WATCHDOG_CTRL_PAUSE_DBG0 49 // Description : Pause the watchdog timer when processor 0 is in debug mode 50 #define WATCHDOG_CTRL_PAUSE_DBG0_RESET 0x1 51 #define WATCHDOG_CTRL_PAUSE_DBG0_BITS 0x02000000 52 #define WATCHDOG_CTRL_PAUSE_DBG0_MSB 25 53 #define WATCHDOG_CTRL_PAUSE_DBG0_LSB 25 54 #define WATCHDOG_CTRL_PAUSE_DBG0_ACCESS "RW" 55 // ----------------------------------------------------------------------------- 56 // Field : WATCHDOG_CTRL_PAUSE_JTAG 57 // Description : Pause the watchdog timer when JTAG is accessing the bus fabric 58 #define WATCHDOG_CTRL_PAUSE_JTAG_RESET 0x1 59 #define WATCHDOG_CTRL_PAUSE_JTAG_BITS 0x01000000 60 #define WATCHDOG_CTRL_PAUSE_JTAG_MSB 24 61 #define WATCHDOG_CTRL_PAUSE_JTAG_LSB 24 62 #define WATCHDOG_CTRL_PAUSE_JTAG_ACCESS "RW" 63 // ----------------------------------------------------------------------------- 64 // Field : WATCHDOG_CTRL_TIME 65 // Description : Indicates the number of ticks / 2 (see errata RP2040-E1) before 66 // a watchdog reset will be triggered 67 #define WATCHDOG_CTRL_TIME_RESET 0x000000 68 #define WATCHDOG_CTRL_TIME_BITS 0x00ffffff 69 #define WATCHDOG_CTRL_TIME_MSB 23 70 #define WATCHDOG_CTRL_TIME_LSB 0 71 #define WATCHDOG_CTRL_TIME_ACCESS "RO" 72 // ============================================================================= 73 // Register : WATCHDOG_LOAD 74 // Description : Load the watchdog timer. The maximum setting is 0xffffff which 75 // corresponds to 0xffffff / 2 ticks before triggering a watchdog 76 // reset (see errata RP2040-E1). 77 #define WATCHDOG_LOAD_OFFSET 0x00000004 78 #define WATCHDOG_LOAD_BITS 0x00ffffff 79 #define WATCHDOG_LOAD_RESET 0x00000000 80 #define WATCHDOG_LOAD_MSB 23 81 #define WATCHDOG_LOAD_LSB 0 82 #define WATCHDOG_LOAD_ACCESS "WF" 83 // ============================================================================= 84 // Register : WATCHDOG_REASON 85 // Description : Logs the reason for the last reset. Both bits are zero for the 86 // case of a hardware reset. 87 #define WATCHDOG_REASON_OFFSET 0x00000008 88 #define WATCHDOG_REASON_BITS 0x00000003 89 #define WATCHDOG_REASON_RESET 0x00000000 90 // ----------------------------------------------------------------------------- 91 // Field : WATCHDOG_REASON_FORCE 92 // Description : None 93 #define WATCHDOG_REASON_FORCE_RESET 0x0 94 #define WATCHDOG_REASON_FORCE_BITS 0x00000002 95 #define WATCHDOG_REASON_FORCE_MSB 1 96 #define WATCHDOG_REASON_FORCE_LSB 1 97 #define WATCHDOG_REASON_FORCE_ACCESS "RO" 98 // ----------------------------------------------------------------------------- 99 // Field : WATCHDOG_REASON_TIMER 100 // Description : None 101 #define WATCHDOG_REASON_TIMER_RESET 0x0 102 #define WATCHDOG_REASON_TIMER_BITS 0x00000001 103 #define WATCHDOG_REASON_TIMER_MSB 0 104 #define WATCHDOG_REASON_TIMER_LSB 0 105 #define WATCHDOG_REASON_TIMER_ACCESS "RO" 106 // ============================================================================= 107 // Register : WATCHDOG_SCRATCH0 108 // Description : Scratch register. Information persists through soft reset of 109 // the chip. 110 #define WATCHDOG_SCRATCH0_OFFSET 0x0000000c 111 #define WATCHDOG_SCRATCH0_BITS 0xffffffff 112 #define WATCHDOG_SCRATCH0_RESET 0x00000000 113 #define WATCHDOG_SCRATCH0_MSB 31 114 #define WATCHDOG_SCRATCH0_LSB 0 115 #define WATCHDOG_SCRATCH0_ACCESS "RW" 116 // ============================================================================= 117 // Register : WATCHDOG_SCRATCH1 118 // Description : Scratch register. Information persists through soft reset of 119 // the chip. 120 #define WATCHDOG_SCRATCH1_OFFSET 0x00000010 121 #define WATCHDOG_SCRATCH1_BITS 0xffffffff 122 #define WATCHDOG_SCRATCH1_RESET 0x00000000 123 #define WATCHDOG_SCRATCH1_MSB 31 124 #define WATCHDOG_SCRATCH1_LSB 0 125 #define WATCHDOG_SCRATCH1_ACCESS "RW" 126 // ============================================================================= 127 // Register : WATCHDOG_SCRATCH2 128 // Description : Scratch register. Information persists through soft reset of 129 // the chip. 130 #define WATCHDOG_SCRATCH2_OFFSET 0x00000014 131 #define WATCHDOG_SCRATCH2_BITS 0xffffffff 132 #define WATCHDOG_SCRATCH2_RESET 0x00000000 133 #define WATCHDOG_SCRATCH2_MSB 31 134 #define WATCHDOG_SCRATCH2_LSB 0 135 #define WATCHDOG_SCRATCH2_ACCESS "RW" 136 // ============================================================================= 137 // Register : WATCHDOG_SCRATCH3 138 // Description : Scratch register. Information persists through soft reset of 139 // the chip. 140 #define WATCHDOG_SCRATCH3_OFFSET 0x00000018 141 #define WATCHDOG_SCRATCH3_BITS 0xffffffff 142 #define WATCHDOG_SCRATCH3_RESET 0x00000000 143 #define WATCHDOG_SCRATCH3_MSB 31 144 #define WATCHDOG_SCRATCH3_LSB 0 145 #define WATCHDOG_SCRATCH3_ACCESS "RW" 146 // ============================================================================= 147 // Register : WATCHDOG_SCRATCH4 148 // Description : Scratch register. Information persists through soft reset of 149 // the chip. 150 #define WATCHDOG_SCRATCH4_OFFSET 0x0000001c 151 #define WATCHDOG_SCRATCH4_BITS 0xffffffff 152 #define WATCHDOG_SCRATCH4_RESET 0x00000000 153 #define WATCHDOG_SCRATCH4_MSB 31 154 #define WATCHDOG_SCRATCH4_LSB 0 155 #define WATCHDOG_SCRATCH4_ACCESS "RW" 156 // ============================================================================= 157 // Register : WATCHDOG_SCRATCH5 158 // Description : Scratch register. Information persists through soft reset of 159 // the chip. 160 #define WATCHDOG_SCRATCH5_OFFSET 0x00000020 161 #define WATCHDOG_SCRATCH5_BITS 0xffffffff 162 #define WATCHDOG_SCRATCH5_RESET 0x00000000 163 #define WATCHDOG_SCRATCH5_MSB 31 164 #define WATCHDOG_SCRATCH5_LSB 0 165 #define WATCHDOG_SCRATCH5_ACCESS "RW" 166 // ============================================================================= 167 // Register : WATCHDOG_SCRATCH6 168 // Description : Scratch register. Information persists through soft reset of 169 // the chip. 170 #define WATCHDOG_SCRATCH6_OFFSET 0x00000024 171 #define WATCHDOG_SCRATCH6_BITS 0xffffffff 172 #define WATCHDOG_SCRATCH6_RESET 0x00000000 173 #define WATCHDOG_SCRATCH6_MSB 31 174 #define WATCHDOG_SCRATCH6_LSB 0 175 #define WATCHDOG_SCRATCH6_ACCESS "RW" 176 // ============================================================================= 177 // Register : WATCHDOG_SCRATCH7 178 // Description : Scratch register. Information persists through soft reset of 179 // the chip. 180 #define WATCHDOG_SCRATCH7_OFFSET 0x00000028 181 #define WATCHDOG_SCRATCH7_BITS 0xffffffff 182 #define WATCHDOG_SCRATCH7_RESET 0x00000000 183 #define WATCHDOG_SCRATCH7_MSB 31 184 #define WATCHDOG_SCRATCH7_LSB 0 185 #define WATCHDOG_SCRATCH7_ACCESS "RW" 186 // ============================================================================= 187 // Register : WATCHDOG_TICK 188 // Description : Controls the tick generator 189 #define WATCHDOG_TICK_OFFSET 0x0000002c 190 #define WATCHDOG_TICK_BITS 0x000fffff 191 #define WATCHDOG_TICK_RESET 0x00000200 192 // ----------------------------------------------------------------------------- 193 // Field : WATCHDOG_TICK_COUNT 194 // Description : Count down timer: the remaining number clk_tick cycles before 195 // the next tick is generated. 196 #define WATCHDOG_TICK_COUNT_RESET "-" 197 #define WATCHDOG_TICK_COUNT_BITS 0x000ff800 198 #define WATCHDOG_TICK_COUNT_MSB 19 199 #define WATCHDOG_TICK_COUNT_LSB 11 200 #define WATCHDOG_TICK_COUNT_ACCESS "RO" 201 // ----------------------------------------------------------------------------- 202 // Field : WATCHDOG_TICK_RUNNING 203 // Description : Is the tick generator running? 204 #define WATCHDOG_TICK_RUNNING_RESET "-" 205 #define WATCHDOG_TICK_RUNNING_BITS 0x00000400 206 #define WATCHDOG_TICK_RUNNING_MSB 10 207 #define WATCHDOG_TICK_RUNNING_LSB 10 208 #define WATCHDOG_TICK_RUNNING_ACCESS "RO" 209 // ----------------------------------------------------------------------------- 210 // Field : WATCHDOG_TICK_ENABLE 211 // Description : start / stop tick generation 212 #define WATCHDOG_TICK_ENABLE_RESET 0x1 213 #define WATCHDOG_TICK_ENABLE_BITS 0x00000200 214 #define WATCHDOG_TICK_ENABLE_MSB 9 215 #define WATCHDOG_TICK_ENABLE_LSB 9 216 #define WATCHDOG_TICK_ENABLE_ACCESS "RW" 217 // ----------------------------------------------------------------------------- 218 // Field : WATCHDOG_TICK_CYCLES 219 // Description : Total number of clk_tick cycles before the next tick. 220 #define WATCHDOG_TICK_CYCLES_RESET 0x000 221 #define WATCHDOG_TICK_CYCLES_BITS 0x000001ff 222 #define WATCHDOG_TICK_CYCLES_MSB 8 223 #define WATCHDOG_TICK_CYCLES_LSB 0 224 #define WATCHDOG_TICK_CYCLES_ACCESS "RW" 225 // ============================================================================= 226 #endif // HARDWARE_REGS_WATCHDOG_DEFINED 227