1 /* 2 * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef _HARDWARE_STRUCTS_USB_H 8 #define _HARDWARE_STRUCTS_USB_H 9 10 #include "hardware/address_mapped.h" 11 #include "hardware/regs/usb.h" 12 13 // 0-15 14 #define USB_NUM_ENDPOINTS 16 15 16 // allow user to restrict number of endpoints available to save RAN 17 #ifndef USB_MAX_ENDPOINTS 18 #define USB_MAX_ENDPOINTS USB_NUM_ENDPOINTS 19 #endif 20 21 // 1-15 22 #define USB_HOST_INTERRUPT_ENDPOINTS (USB_NUM_ENDPOINTS - 1) 23 24 // Endpoint buffer control bits 25 #define USB_BUF_CTRL_FULL 0x00008000u 26 #define USB_BUF_CTRL_LAST 0x00004000u 27 #define USB_BUF_CTRL_DATA0_PID 0x00000000u 28 #define USB_BUF_CTRL_DATA1_PID 0x00002000u 29 #define USB_BUF_CTRL_SEL 0x00001000u 30 #define USB_BUF_CTRL_STALL 0x00000800u 31 #define USB_BUF_CTRL_AVAIL 0x00000400u 32 #define USB_BUF_CTRL_LEN_MASK 0x000003FFu 33 #define USB_BUF_CTRL_LEN_LSB 0 34 35 // ep_inout_ctrl bits 36 #define EP_CTRL_ENABLE_BITS (1u << 31u) 37 #define EP_CTRL_DOUBLE_BUFFERED_BITS (1u << 30) 38 #define EP_CTRL_INTERRUPT_PER_BUFFER (1u << 29) 39 #define EP_CTRL_INTERRUPT_PER_DOUBLE_BUFFER (1u << 28) 40 #define EP_CTRL_INTERRUPT_ON_NAK (1u << 16) 41 #define EP_CTRL_INTERRUPT_ON_STALL (1u << 17) 42 #define EP_CTRL_BUFFER_TYPE_LSB 26 43 #define EP_CTRL_HOST_INTERRUPT_INTERVAL_LSB 16 44 45 #define USB_DPRAM_SIZE 4096 46 47 // PICO_CONFIG: USB_DPRAM_MAX, Set amount of USB RAM used by USB system, min=0, max=4096, default=4096, group=hardware_usb 48 // Allow user to claim some of the USB RAM for themselves 49 #ifndef USB_DPRAM_MAX 50 #define USB_DPRAM_MAX USB_DPRAM_SIZE 51 #endif 52 53 // Define maximum packet sizes 54 #define USB_MAX_ISO_PACKET_SIZE 1023 55 #define USB_MAX_PACKET_SIZE 64 56 57 typedef struct { 58 // 4K of DPSRAM at beginning. Note this supports 8, 16, and 32 bit accesses 59 volatile uint8_t setup_packet[8]; // First 8 bytes are always for setup packets 60 61 // Starts at ep1 62 struct usb_device_dpram_ep_ctrl { 63 io_rw_32 in; 64 io_rw_32 out; 65 } ep_ctrl[USB_NUM_ENDPOINTS - 1]; 66 67 // Starts at ep0 68 struct usb_device_dpram_ep_buf_ctrl { 69 io_rw_32 in; 70 io_rw_32 out; 71 } ep_buf_ctrl[USB_NUM_ENDPOINTS]; 72 73 // EP0 buffers are fixed. Assumes single buffered mode for EP0 74 uint8_t ep0_buf_a[0x40]; 75 uint8_t ep0_buf_b[0x40]; 76 77 // Rest of DPRAM can be carved up as needed 78 uint8_t epx_data[USB_DPRAM_MAX - 0x180]; 79 } usb_device_dpram_t; 80 81 static_assert(sizeof(usb_device_dpram_t) == USB_DPRAM_MAX, ""); 82 83 typedef struct { 84 // 4K of DPSRAM at beginning. Note this supports 8, 16, and 32 bit accesses 85 volatile uint8_t setup_packet[8]; // First 8 bytes are always for setup packets 86 87 // Interrupt endpoint control 1 -> 15 88 struct usb_host_dpram_ep_ctrl { 89 io_rw_32 ctrl; 90 io_rw_32 spare; 91 } int_ep_ctrl[USB_HOST_INTERRUPT_ENDPOINTS]; 92 93 io_rw_32 epx_buf_ctrl; 94 io_rw_32 _spare0; 95 96 // Interrupt endpoint buffer control 97 struct usb_host_dpram_ep_buf_ctrl { 98 io_rw_32 ctrl; 99 io_rw_32 spare; 100 } int_ep_buffer_ctrl[USB_HOST_INTERRUPT_ENDPOINTS]; 101 102 io_rw_32 epx_ctrl; 103 104 uint8_t _spare1[124]; 105 106 // Should start at 0x180 107 uint8_t epx_data[USB_DPRAM_MAX - 0x180]; 108 } usb_host_dpram_t; 109 110 static_assert(sizeof(usb_host_dpram_t) == USB_DPRAM_MAX, ""); 111 112 typedef struct { 113 io_rw_32 dev_addr_ctrl; 114 io_rw_32 int_ep_addr_ctrl[USB_HOST_INTERRUPT_ENDPOINTS]; 115 io_rw_32 main_ctrl; 116 io_rw_32 sof_rw; 117 io_ro_32 sof_rd; 118 io_rw_32 sie_ctrl; 119 io_rw_32 sie_status; 120 io_rw_32 int_ep_ctrl; 121 io_rw_32 buf_status; 122 io_rw_32 buf_cpu_should_handle; // for double buff 123 io_rw_32 abort; 124 io_rw_32 abort_done; 125 io_rw_32 ep_stall_arm; 126 io_rw_32 nak_poll; 127 io_rw_32 ep_nak_stall_status; 128 io_rw_32 muxing; 129 io_rw_32 pwr; 130 io_rw_32 phy_direct; 131 io_rw_32 phy_direct_override; 132 io_rw_32 phy_trim; 133 io_rw_32 linestate_tuning; 134 io_rw_32 intr; 135 io_rw_32 inte; 136 io_rw_32 intf; 137 io_rw_32 ints; 138 } usb_hw_t; 139 140 check_hw_layout(usb_hw_t, ints, USB_INTS_OFFSET); 141 142 #define usb_hw ((usb_hw_t *)USBCTRL_REGS_BASE) 143 144 #define usb_dpram ((usb_device_dpram_t *)USBCTRL_DPRAM_BASE) 145 #define usbh_dpram ((usb_host_dpram_t *)USBCTRL_DPRAM_BASE) 146 147 #endif 148