1 //***************************************************************************** 2 // 3 // hw_i2c.h - Macros used when accessing the I2C master and slave hardware. 4 // 5 // Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved. 6 // Software License Agreement 7 // 8 // Redistribution and use in source and binary forms, with or without 9 // modification, are permitted provided that the following conditions 10 // are met: 11 // 12 // Redistributions of source code must retain the above copyright 13 // notice, this list of conditions and the following disclaimer. 14 // 15 // Redistributions in binary form must reproduce the above copyright 16 // notice, this list of conditions and the following disclaimer in the 17 // documentation and/or other materials provided with the 18 // distribution. 19 // 20 // Neither the name of Texas Instruments Incorporated nor the names of 21 // its contributors may be used to endorse or promote products derived 22 // from this software without specific prior written permission. 23 // 24 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 // 36 // This is part of revision 9453 of the Stellaris Firmware Development Package. 37 // 38 //***************************************************************************** 39 40 #ifndef __HW_I2C_H__ 41 #define __HW_I2C_H__ 42 43 //***************************************************************************** 44 // 45 // The following are defines for the I2C register offsets. 46 // 47 //***************************************************************************** 48 #define I2C_O_MSA 0x00000000 // I2C Master Slave Address 49 #define I2C_O_SOAR 0x00000000 // I2C Slave Own Address 50 #define I2C_O_SCSR 0x00000004 // I2C Slave Control/Status 51 #define I2C_O_MCS 0x00000004 // I2C Master Control/Status 52 #define I2C_O_SDR 0x00000008 // I2C Slave Data 53 #define I2C_O_MDR 0x00000008 // I2C Master Data 54 #define I2C_O_MTPR 0x0000000C // I2C Master Timer Period 55 #define I2C_O_SIMR 0x0000000C // I2C Slave Interrupt Mask 56 #define I2C_O_SRIS 0x00000010 // I2C Slave Raw Interrupt Status 57 #define I2C_O_MIMR 0x00000010 // I2C Master Interrupt Mask 58 #define I2C_O_MRIS 0x00000014 // I2C Master Raw Interrupt Status 59 #define I2C_O_SMIS 0x00000014 // I2C Slave Masked Interrupt 60 // Status 61 #define I2C_O_SICR 0x00000018 // I2C Slave Interrupt Clear 62 #define I2C_O_MMIS 0x00000018 // I2C Master Masked Interrupt 63 // Status 64 #define I2C_O_MICR 0x0000001C // I2C Master Interrupt Clear 65 #define I2C_O_SOAR2 0x0000001C // I2C Slave Own Address 2 66 #define I2C_O_MCR 0x00000020 // I2C Master Configuration 67 #define I2C_O_SACKCTL 0x00000020 // I2C Slave ACK Control 68 #define I2C_O_MCLKOCNT 0x00000024 // I2C Master Clock Low Timeout 69 // Count 70 #define I2C_O_MBMON 0x0000002C // I2C Master Bus Monitor 71 #define I2C_O_PP 0x00000FC0 // I2C Peripheral Properties 72 #define I2C_O_PC 0x00000FC4 // I2C Peripheral Configuration 73 74 //***************************************************************************** 75 // 76 // The following are defines for the bit fields in the I2C_O_MSA register. 77 // 78 //***************************************************************************** 79 #define I2C_MSA_SA_M 0x000000FE // I2C Slave Address 80 #define I2C_MSA_RS 0x00000001 // Receive not send 81 #define I2C_MSA_SA_S 1 82 83 //***************************************************************************** 84 // 85 // The following are defines for the bit fields in the I2C_O_SOAR register. 86 // 87 //***************************************************************************** 88 #define I2C_SOAR_OAR_M 0x0000007F // I2C Slave Own Address 89 #define I2C_SOAR_OAR_S 0 90 91 //***************************************************************************** 92 // 93 // The following are defines for the bit fields in the I2C_O_SCSR register. 94 // 95 //***************************************************************************** 96 #define I2C_SCSR_QCMDRW 0x00000020 // Quick Command Read / Write 97 #define I2C_SCSR_QCMDST 0x00000010 // Quick Command Status 98 #define I2C_SCSR_OAR2SEL 0x00000008 // OAR2 Address Matched 99 #define I2C_SCSR_FBR 0x00000004 // First Byte Received 100 #define I2C_SCSR_TREQ 0x00000002 // Transmit Request 101 #define I2C_SCSR_DA 0x00000001 // Device Active 102 #define I2C_SCSR_RREQ 0x00000001 // Receive Request 103 104 //***************************************************************************** 105 // 106 // The following are defines for the bit fields in the I2C_O_MCS register. 107 // 108 //***************************************************************************** 109 #define I2C_MCS_CLKTO 0x00000080 // Clock Timeout Error 110 #define I2C_MCS_BUSBSY 0x00000040 // Bus Busy 111 #define I2C_MCS_IDLE 0x00000020 // I2C Idle 112 #define I2C_MCS_QCMD 0x00000020 // Quick Command 113 #define I2C_MCS_ARBLST 0x00000010 // Arbitration Lost 114 #define I2C_MCS_HS 0x00000010 // High-Speed Enable 115 #define I2C_MCS_ACK 0x00000008 // Data Acknowledge Enable 116 #define I2C_MCS_DATACK 0x00000008 // Acknowledge Data 117 #define I2C_MCS_ADRACK 0x00000004 // Acknowledge Address 118 #define I2C_MCS_STOP 0x00000004 // Generate STOP 119 #define I2C_MCS_ERROR 0x00000002 // Error 120 #define I2C_MCS_START 0x00000002 // Generate START 121 #define I2C_MCS_RUN 0x00000001 // I2C Master Enable 122 #define I2C_MCS_BUSY 0x00000001 // I2C Busy 123 124 //***************************************************************************** 125 // 126 // The following are defines for the bit fields in the I2C_O_SDR register. 127 // 128 //***************************************************************************** 129 #define I2C_SDR_DATA_M 0x000000FF // Data for Transfer 130 #define I2C_SDR_DATA_S 0 131 132 //***************************************************************************** 133 // 134 // The following are defines for the bit fields in the I2C_O_MDR register. 135 // 136 //***************************************************************************** 137 #define I2C_MDR_DATA_M 0x000000FF // Data Transferred 138 #define I2C_MDR_DATA_S 0 139 140 //***************************************************************************** 141 // 142 // The following are defines for the bit fields in the I2C_O_MTPR register. 143 // 144 //***************************************************************************** 145 #define I2C_MTPR_HS 0x00000080 // High-Speed Enable 146 #define I2C_MTPR_TPR_M 0x0000007F // SCL Clock Period 147 #define I2C_MTPR_TPR_S 0 148 149 //***************************************************************************** 150 // 151 // The following are defines for the bit fields in the I2C_O_SIMR register. 152 // 153 //***************************************************************************** 154 #define I2C_SIMR_STOPIM 0x00000004 // Stop Condition Interrupt Mask 155 #define I2C_SIMR_STARTIM 0x00000002 // Start Condition Interrupt Mask 156 #define I2C_SIMR_DATAIM 0x00000001 // Data Interrupt Mask 157 158 //***************************************************************************** 159 // 160 // The following are defines for the bit fields in the I2C_O_SRIS register. 161 // 162 //***************************************************************************** 163 #define I2C_SRIS_STOPRIS 0x00000004 // Stop Condition Raw Interrupt 164 // Status 165 #define I2C_SRIS_STARTRIS 0x00000002 // Start Condition Raw Interrupt 166 // Status 167 #define I2C_SRIS_DATARIS 0x00000001 // Data Raw Interrupt Status 168 169 //***************************************************************************** 170 // 171 // The following are defines for the bit fields in the I2C_O_MIMR register. 172 // 173 //***************************************************************************** 174 #define I2C_MIMR_CLKIM 0x00000002 // Clock Timeout Interrupt Mask 175 #define I2C_MIMR_IM 0x00000001 // Master Interrupt Mask 176 177 //***************************************************************************** 178 // 179 // The following are defines for the bit fields in the I2C_O_MRIS register. 180 // 181 //***************************************************************************** 182 #define I2C_MRIS_CLKRIS 0x00000002 // Clock Timeout Raw Interrupt 183 // Status 184 #define I2C_MRIS_RIS 0x00000001 // Master Raw Interrupt Status 185 186 //***************************************************************************** 187 // 188 // The following are defines for the bit fields in the I2C_O_SMIS register. 189 // 190 //***************************************************************************** 191 #define I2C_SMIS_STOPMIS 0x00000004 // Stop Condition Masked Interrupt 192 // Status 193 #define I2C_SMIS_STARTMIS 0x00000002 // Start Condition Masked Interrupt 194 // Status 195 #define I2C_SMIS_DATAMIS 0x00000001 // Data Masked Interrupt Status 196 197 //***************************************************************************** 198 // 199 // The following are defines for the bit fields in the I2C_O_SICR register. 200 // 201 //***************************************************************************** 202 #define I2C_SICR_STOPIC 0x00000004 // Stop Condition Interrupt Clear 203 #define I2C_SICR_STARTIC 0x00000002 // Start Condition Interrupt Clear 204 #define I2C_SICR_DATAIC 0x00000001 // Data Interrupt Clear 205 206 //***************************************************************************** 207 // 208 // The following are defines for the bit fields in the I2C_O_MMIS register. 209 // 210 //***************************************************************************** 211 #define I2C_MMIS_CLKMIS 0x00000002 // Clock Timeout Masked Interrupt 212 // Status 213 #define I2C_MMIS_MIS 0x00000001 // Masked Interrupt Status 214 215 //***************************************************************************** 216 // 217 // The following are defines for the bit fields in the I2C_O_MICR register. 218 // 219 //***************************************************************************** 220 #define I2C_MICR_CLKIC 0x00000002 // Clock Timeout Interrupt Clear 221 #define I2C_MICR_IC 0x00000001 // Master Interrupt Clear 222 223 //***************************************************************************** 224 // 225 // The following are defines for the bit fields in the I2C_O_SOAR2 register. 226 // 227 //***************************************************************************** 228 #define I2C_SOAR2_OAR2EN 0x00000080 // I2C Slave Own Address 2 Enable 229 #define I2C_SOAR2_OAR2_M 0x0000007F // I2C Slave Own Address 2 230 #define I2C_SOAR2_OAR2_S 0 231 232 //***************************************************************************** 233 // 234 // The following are defines for the bit fields in the I2C_O_MCR register. 235 // 236 //***************************************************************************** 237 #define I2C_MCR_SFE 0x00000020 // I2C Slave Function Enable 238 #define I2C_MCR_MFE 0x00000010 // I2C Master Function Enable 239 #define I2C_MCR_LPBK 0x00000001 // I2C Loopback 240 241 //***************************************************************************** 242 // 243 // The following are defines for the bit fields in the I2C_O_SACKCTL register. 244 // 245 //***************************************************************************** 246 #define I2C_SACKCTL_ACKOVAL 0x00000002 // I2C Slave ACK Override Value 247 #define I2C_SACKCTL_ACKOEN 0x00000001 // I2C Slave ACK Override Enable 248 249 //***************************************************************************** 250 // 251 // The following are defines for the bit fields in the I2C_O_MCLKOCNT register. 252 // 253 //***************************************************************************** 254 #define I2C_MCLKOCNT_CNTL_M 0x000000FF // I2C Master Count 255 #define I2C_MCLKOCNT_CNTL_S 0 256 257 //***************************************************************************** 258 // 259 // The following are defines for the bit fields in the I2C_O_MBMON register. 260 // 261 //***************************************************************************** 262 #define I2C_MBMON_SDA 0x00000002 // I2C SDA Status 263 #define I2C_MBMON_SCL 0x00000001 // I2C SCL Status 264 265 //***************************************************************************** 266 // 267 // The following are defines for the bit fields in the I2C_O_PP register. 268 // 269 //***************************************************************************** 270 #define I2C_PP_HS 0x00000001 // High-Speed Capable 271 272 //***************************************************************************** 273 // 274 // The following are defines for the bit fields in the I2C_O_PC register. 275 // 276 //***************************************************************************** 277 #define I2C_PC_HS 0x00000001 // High-Speed Capable 278 279 //***************************************************************************** 280 // 281 // The following definitions are deprecated. 282 // 283 //***************************************************************************** 284 #ifndef DEPRECATED 285 286 //***************************************************************************** 287 // 288 // The following are deprecated defines for the I2C register offsets. 289 // 290 //***************************************************************************** 291 #define I2C_O_SLAVE 0x00000800 // Offset from master to slave 292 293 //***************************************************************************** 294 // 295 // The following are deprecated defines for the bit fields in the I2C_O_SIMR 296 // register. 297 // 298 //***************************************************************************** 299 #define I2C_SIMR_IM 0x00000001 // Interrupt Mask 300 301 //***************************************************************************** 302 // 303 // The following are deprecated defines for the bit fields in the I2C_O_SRIS 304 // register. 305 // 306 //***************************************************************************** 307 #define I2C_SRIS_RIS 0x00000001 // Raw Interrupt Status 308 309 //***************************************************************************** 310 // 311 // The following are deprecated defines for the bit fields in the I2C_O_SMIS 312 // register. 313 // 314 //***************************************************************************** 315 #define I2C_SMIS_MIS 0x00000001 // Masked Interrupt Status 316 317 //***************************************************************************** 318 // 319 // The following are deprecated defines for the bit fields in the I2C_O_SICR 320 // register. 321 // 322 //***************************************************************************** 323 #define I2C_SICR_IC 0x00000001 // Clear Interrupt 324 325 //***************************************************************************** 326 // 327 // The following are deprecated defines for the I2C master register offsets. 328 // 329 //***************************************************************************** 330 #define I2C_MASTER_O_SA 0x00000000 // Slave address register 331 #define I2C_MASTER_O_CS 0x00000004 // Control and Status register 332 #define I2C_MASTER_O_DR 0x00000008 // Data register 333 #define I2C_MASTER_O_TPR 0x0000000C // Timer period register 334 #define I2C_MASTER_O_IMR 0x00000010 // Interrupt mask register 335 #define I2C_MASTER_O_RIS 0x00000014 // Raw interrupt status register 336 #define I2C_MASTER_O_MIS 0x00000018 // Masked interrupt status reg 337 #define I2C_MASTER_O_MICR 0x0000001C // Interrupt clear register 338 #define I2C_MASTER_O_CR 0x00000020 // Configuration register 339 340 //***************************************************************************** 341 // 342 // The following are deprecated defines for the I2C slave register offsets. 343 // 344 //***************************************************************************** 345 #define I2C_SLAVE_O_SICR 0x00000018 // Interrupt clear register 346 #define I2C_SLAVE_O_MIS 0x00000014 // Masked interrupt status reg 347 #define I2C_SLAVE_O_RIS 0x00000010 // Raw interrupt status register 348 #define I2C_SLAVE_O_IM 0x0000000C // Interrupt mask register 349 #define I2C_SLAVE_O_DR 0x00000008 // Data register 350 #define I2C_SLAVE_O_CSR 0x00000004 // Control/Status register 351 #define I2C_SLAVE_O_OAR 0x00000000 // Own address register 352 353 //***************************************************************************** 354 // 355 // The following are deprecated defines for the bit fields in the I2C master 356 // slave address register. 357 // 358 //***************************************************************************** 359 #define I2C_MASTER_SA_SA_MASK 0x000000FE // Slave address 360 #define I2C_MASTER_SA_RS 0x00000001 // Receive/send 361 #define I2C_MASTER_SA_SA_SHIFT 1 362 363 //***************************************************************************** 364 // 365 // The following are deprecated defines for the bit fields in the I2C Master 366 // Control and Status register. 367 // 368 //***************************************************************************** 369 #define I2C_MASTER_CS_BUS_BUSY 0x00000040 // Bus busy 370 #define I2C_MASTER_CS_IDLE 0x00000020 // Idle 371 #define I2C_MASTER_CS_ERR_MASK 0x0000001C 372 #define I2C_MASTER_CS_BUSY 0x00000001 // Controller is TX/RX data 373 #define I2C_MASTER_CS_ERROR 0x00000002 // Error occurred 374 #define I2C_MASTER_CS_ADDR_ACK 0x00000004 // Address byte not acknowledged 375 #define I2C_MASTER_CS_DATA_ACK 0x00000008 // Data byte not acknowledged 376 #define I2C_MASTER_CS_ARB_LOST 0x00000010 // Lost arbitration 377 #define I2C_MASTER_CS_ACK 0x00000008 // Acknowlegde 378 #define I2C_MASTER_CS_STOP 0x00000004 // Stop 379 #define I2C_MASTER_CS_START 0x00000002 // Start 380 #define I2C_MASTER_CS_RUN 0x00000001 // Run 381 382 //***************************************************************************** 383 // 384 // The following are deprecated defines for the values used in determining the 385 // contents of the I2C Master Timer Period register. 386 // 387 //***************************************************************************** 388 #define I2C_SCL_FAST 400000 // SCL fast frequency 389 #define I2C_SCL_STANDARD 100000 // SCL standard frequency 390 #define I2C_MASTER_TPR_SCL_LP 0x00000006 // SCL low period 391 #define I2C_MASTER_TPR_SCL_HP 0x00000004 // SCL high period 392 #define I2C_MASTER_TPR_SCL (I2C_MASTER_TPR_SCL_HP + I2C_MASTER_TPR_SCL_LP) 393 394 //***************************************************************************** 395 // 396 // The following are deprecated defines for the bit fields in the I2C Master 397 // Interrupt Mask register. 398 // 399 //***************************************************************************** 400 #define I2C_MASTER_IMR_IM 0x00000001 // Master interrupt mask 401 402 //***************************************************************************** 403 // 404 // The following are deprecated defines for the bit fields in the I2C Master 405 // Raw Interrupt Status register. 406 // 407 //***************************************************************************** 408 #define I2C_MASTER_RIS_RIS 0x00000001 // Master raw interrupt status 409 410 //***************************************************************************** 411 // 412 // The following are deprecated defines for the bit fields in the I2C Master 413 // Masked Interrupt Status register. 414 // 415 //***************************************************************************** 416 #define I2C_MASTER_MIS_MIS 0x00000001 // Master masked interrupt status 417 418 //***************************************************************************** 419 // 420 // The following are deprecated defines for the bit fields in the I2C Master 421 // Interrupt Clear register. 422 // 423 //***************************************************************************** 424 #define I2C_MASTER_MICR_IC 0x00000001 // Master interrupt clear 425 426 //***************************************************************************** 427 // 428 // The following are deprecated defines for the bit fields in the I2C Master 429 // Configuration register. 430 // 431 //***************************************************************************** 432 #define I2C_MASTER_CR_SFE 0x00000020 // Slave function enable 433 #define I2C_MASTER_CR_MFE 0x00000010 // Master function enable 434 #define I2C_MASTER_CR_LPBK 0x00000001 // Loopback enable 435 436 //***************************************************************************** 437 // 438 // The following are deprecated defines for the bit fields in the I2C Slave Own 439 // Address register. 440 // 441 //***************************************************************************** 442 #define I2C_SLAVE_SOAR_OAR_MASK 0x0000007F // Slave address 443 444 //***************************************************************************** 445 // 446 // The following are deprecated defines for the bit fields in the I2C Slave 447 // Control/Status register. 448 // 449 //***************************************************************************** 450 #define I2C_SLAVE_CSR_FBR 0x00000004 // First byte received from master 451 #define I2C_SLAVE_CSR_TREQ 0x00000002 // Transmit request received 452 #define I2C_SLAVE_CSR_DA 0x00000001 // Enable the device 453 #define I2C_SLAVE_CSR_RREQ 0x00000001 // Receive data from I2C master 454 455 //***************************************************************************** 456 // 457 // The following are deprecated defines for the bit fields in the I2C Slave 458 // Interrupt Mask register. 459 // 460 //***************************************************************************** 461 #define I2C_SLAVE_IMR_IM 0x00000001 // Slave interrupt mask 462 463 //***************************************************************************** 464 // 465 // The following are deprecated defines for the bit fields in the I2C Slave Raw 466 // Interrupt Status register. 467 // 468 //***************************************************************************** 469 #define I2C_SLAVE_RIS_RIS 0x00000001 // Slave raw interrupt status 470 471 //***************************************************************************** 472 // 473 // The following are deprecated defines for the bit fields in the I2C Slave 474 // Masked Interrupt Status register. 475 // 476 //***************************************************************************** 477 #define I2C_SLAVE_MIS_MIS 0x00000001 // Slave masked interrupt status 478 479 //***************************************************************************** 480 // 481 // The following are deprecated defines for the bit fields in the I2C Slave 482 // Interrupt Clear register. 483 // 484 //***************************************************************************** 485 #define I2C_SLAVE_SICR_IC 0x00000001 // Slave interrupt clear 486 487 #endif 488 489 #endif // __HW_I2C_H__ 490