1 //***************************************************************************** 2 // 3 // hw_i2s.h - Macros for use in accessing the I2S registers. 4 // 5 // Copyright (c) 2008-2012 Texas Instruments Incorporated. All rights reserved. 6 // Software License Agreement 7 // 8 // Redistribution and use in source and binary forms, with or without 9 // modification, are permitted provided that the following conditions 10 // are met: 11 // 12 // Redistributions of source code must retain the above copyright 13 // notice, this list of conditions and the following disclaimer. 14 // 15 // Redistributions in binary form must reproduce the above copyright 16 // notice, this list of conditions and the following disclaimer in the 17 // documentation and/or other materials provided with the 18 // distribution. 19 // 20 // Neither the name of Texas Instruments Incorporated nor the names of 21 // its contributors may be used to endorse or promote products derived 22 // from this software without specific prior written permission. 23 // 24 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 // 36 // This is part of revision 9453 of the Stellaris Firmware Development Package. 37 // 38 //***************************************************************************** 39 40 #ifndef __HW_I2S_H__ 41 #define __HW_I2S_H__ 42 43 //***************************************************************************** 44 // 45 // The following are defines for the Inter-Integrated Circuit Sound register 46 // offsets. 47 // 48 //***************************************************************************** 49 #define I2S_O_TXFIFO 0x00000000 // I2S Transmit FIFO Data 50 #define I2S_O_TXFIFOCFG 0x00000004 // I2S Transmit FIFO Configuration 51 #define I2S_O_TXCFG 0x00000008 // I2S Transmit Module 52 // Configuration 53 #define I2S_O_TXLIMIT 0x0000000C // I2S Transmit FIFO Limit 54 #define I2S_O_TXISM 0x00000010 // I2S Transmit Interrupt Status 55 // and Mask 56 #define I2S_O_TXLEV 0x00000018 // I2S Transmit FIFO Level 57 #define I2S_O_RXFIFO 0x00000800 // I2S Receive FIFO Data 58 #define I2S_O_RXFIFOCFG 0x00000804 // I2S Receive FIFO Configuration 59 #define I2S_O_RXCFG 0x00000808 // I2S Receive Module Configuration 60 #define I2S_O_RXLIMIT 0x0000080C // I2S Receive FIFO Limit 61 #define I2S_O_RXISM 0x00000810 // I2S Receive Interrupt Status and 62 // Mask 63 #define I2S_O_RXLEV 0x00000818 // I2S Receive FIFO Level 64 #define I2S_O_CFG 0x00000C00 // I2S Module Configuration 65 #define I2S_O_IM 0x00000C10 // I2S Interrupt Mask 66 #define I2S_O_RIS 0x00000C14 // I2S Raw Interrupt Status 67 #define I2S_O_MIS 0x00000C18 // I2S Masked Interrupt Status 68 #define I2S_O_IC 0x00000C1C // I2S Interrupt Clear 69 70 //***************************************************************************** 71 // 72 // The following are defines for the bit fields in the I2S_O_TXFIFO register. 73 // 74 //***************************************************************************** 75 #define I2S_TXFIFO_M 0xFFFFFFFF // TX Data 76 #define I2S_TXFIFO_S 0 77 78 //***************************************************************************** 79 // 80 // The following are defines for the bit fields in the I2S_O_TXFIFOCFG 81 // register. 82 // 83 //***************************************************************************** 84 #define I2S_TXFIFOCFG_CSS 0x00000002 // Compact Stereo Sample Size 85 #define I2S_TXFIFOCFG_LRS 0x00000001 // Left-Right Sample Indicator 86 87 //***************************************************************************** 88 // 89 // The following are defines for the bit fields in the I2S_O_TXCFG register. 90 // 91 //***************************************************************************** 92 #define I2S_TXCFG_JST 0x20000000 // Justification of Output Data 93 #define I2S_TXCFG_DLY 0x10000000 // Data Delay 94 #define I2S_TXCFG_SCP 0x08000000 // SCLK Polarity 95 #define I2S_TXCFG_LRP 0x04000000 // Left/Right Clock Polarity 96 #define I2S_TXCFG_WM_M 0x03000000 // Write Mode 97 #define I2S_TXCFG_WM_DUAL 0x00000000 // Stereo mode 98 #define I2S_TXCFG_WM_COMPACT 0x01000000 // Compact Stereo mode 99 #define I2S_TXCFG_WM_MONO 0x02000000 // Mono mode 100 #define I2S_TXCFG_FMT 0x00800000 // FIFO Empty 101 #define I2S_TXCFG_MSL 0x00400000 // SCLK Master/Slave 102 #define I2S_TXCFG_SSZ_M 0x0000FC00 // Sample Size 103 #define I2S_TXCFG_SDSZ_M 0x000003F0 // System Data Size 104 #define I2S_TXCFG_SSZ_S 10 105 #define I2S_TXCFG_SDSZ_S 4 106 107 //***************************************************************************** 108 // 109 // The following are defines for the bit fields in the I2S_O_TXLIMIT register. 110 // 111 //***************************************************************************** 112 #define I2S_TXLIMIT_LIMIT_M 0x0000001F // FIFO Limit 113 #define I2S_TXLIMIT_LIMIT_S 0 114 115 //***************************************************************************** 116 // 117 // The following are defines for the bit fields in the I2S_O_TXISM register. 118 // 119 //***************************************************************************** 120 #define I2S_TXISM_FFI 0x00010000 // Transmit FIFO Service Request 121 // Interrupt 122 #define I2S_TXISM_FFM 0x00000001 // FIFO Interrupt Mask 123 124 //***************************************************************************** 125 // 126 // The following are defines for the bit fields in the I2S_O_TXLEV register. 127 // 128 //***************************************************************************** 129 #define I2S_TXLEV_LEVEL_M 0x0000001F // Number of Audio Samples 130 #define I2S_TXLEV_LEVEL_S 0 131 132 //***************************************************************************** 133 // 134 // The following are defines for the bit fields in the I2S_O_RXFIFO register. 135 // 136 //***************************************************************************** 137 #define I2S_RXFIFO_M 0xFFFFFFFF // RX Data 138 #define I2S_RXFIFO_S 0 139 140 //***************************************************************************** 141 // 142 // The following are defines for the bit fields in the I2S_O_RXFIFOCFG 143 // register. 144 // 145 //***************************************************************************** 146 #define I2S_RXFIFOCFG_FMM 0x00000004 // FIFO Mono Mode 147 #define I2S_RXFIFOCFG_CSS 0x00000002 // Compact Stereo Sample Size 148 #define I2S_RXFIFOCFG_LRS 0x00000001 // Left-Right Sample Indicator 149 150 //***************************************************************************** 151 // 152 // The following are defines for the bit fields in the I2S_O_RXCFG register. 153 // 154 //***************************************************************************** 155 #define I2S_RXCFG_JST 0x20000000 // Justification of Input Data 156 #define I2S_RXCFG_DLY 0x10000000 // Data Delay 157 #define I2S_RXCFG_SCP 0x08000000 // SCLK Polarity 158 #define I2S_RXCFG_LRP 0x04000000 // Left/Right Clock Polarity 159 #define I2S_RXCFG_RM 0x01000000 // Read Mode 160 #define I2S_RXCFG_MSL 0x00400000 // SCLK Master/Slave 161 #define I2S_RXCFG_SSZ_M 0x0000FC00 // Sample Size 162 #define I2S_RXCFG_SDSZ_M 0x000003F0 // System Data Size 163 #define I2S_RXCFG_SSZ_S 10 164 #define I2S_RXCFG_SDSZ_S 4 165 166 //***************************************************************************** 167 // 168 // The following are defines for the bit fields in the I2S_O_RXLIMIT register. 169 // 170 //***************************************************************************** 171 #define I2S_RXLIMIT_LIMIT_M 0x0000001F // FIFO Limit 172 #define I2S_RXLIMIT_LIMIT_S 0 173 174 //***************************************************************************** 175 // 176 // The following are defines for the bit fields in the I2S_O_RXISM register. 177 // 178 //***************************************************************************** 179 #define I2S_RXISM_FFI 0x00010000 // Receive FIFO Service Request 180 // Interrupt 181 #define I2S_RXISM_FFM 0x00000001 // FIFO Interrupt Mask 182 183 //***************************************************************************** 184 // 185 // The following are defines for the bit fields in the I2S_O_RXLEV register. 186 // 187 //***************************************************************************** 188 #define I2S_RXLEV_LEVEL_M 0x0000001F // Number of Audio Samples 189 #define I2S_RXLEV_LEVEL_S 0 190 191 //***************************************************************************** 192 // 193 // The following are defines for the bit fields in the I2S_O_CFG register. 194 // 195 //***************************************************************************** 196 #define I2S_CFG_RXSLV 0x00000020 // Use External I2S0RXMCLK 197 #define I2S_CFG_TXSLV 0x00000010 // Use External I2S0TXMCLK 198 #define I2S_CFG_RXEN 0x00000002 // Serial Receive Engine Enable 199 #define I2S_CFG_TXEN 0x00000001 // Serial Transmit Engine Enable 200 201 //***************************************************************************** 202 // 203 // The following are defines for the bit fields in the I2S_O_IM register. 204 // 205 //***************************************************************************** 206 #define I2S_IM_RXRE 0x00000020 // Receive FIFO Read Error 207 #define I2S_IM_RXFSR 0x00000010 // Receive FIFO Service Request 208 #define I2S_IM_TXWE 0x00000002 // Transmit FIFO Write Error 209 #define I2S_IM_TXFSR 0x00000001 // Transmit FIFO Service Request 210 211 //***************************************************************************** 212 // 213 // The following are defines for the bit fields in the I2S_O_RIS register. 214 // 215 //***************************************************************************** 216 #define I2S_RIS_RXRE 0x00000020 // Receive FIFO Read Error 217 #define I2S_RIS_RXFSR 0x00000010 // Receive FIFO Service Request 218 #define I2S_RIS_TXWE 0x00000002 // Transmit FIFO Write Error 219 #define I2S_RIS_TXFSR 0x00000001 // Transmit FIFO Service Request 220 221 //***************************************************************************** 222 // 223 // The following are defines for the bit fields in the I2S_O_MIS register. 224 // 225 //***************************************************************************** 226 #define I2S_MIS_RXRE 0x00000020 // Receive FIFO Read Error 227 #define I2S_MIS_RXFSR 0x00000010 // Receive FIFO Service Request 228 #define I2S_MIS_TXWE 0x00000002 // Transmit FIFO Write Error 229 #define I2S_MIS_TXFSR 0x00000001 // Transmit FIFO Service Request 230 231 //***************************************************************************** 232 // 233 // The following are defines for the bit fields in the I2S_O_IC register. 234 // 235 //***************************************************************************** 236 #define I2S_IC_RXRE 0x00000020 // Receive FIFO Read Error 237 #define I2S_IC_TXWE 0x00000002 // Transmit FIFO Write Error 238 239 #endif // __HW_I2S_H__ 240