1 //***************************************************************************** 2 // 3 // hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware. 4 // 5 // Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved. 6 // Software License Agreement 7 // 8 // Redistribution and use in source and binary forms, with or without 9 // modification, are permitted provided that the following conditions 10 // are met: 11 // 12 // Redistributions of source code must retain the above copyright 13 // notice, this list of conditions and the following disclaimer. 14 // 15 // Redistributions in binary form must reproduce the above copyright 16 // notice, this list of conditions and the following disclaimer in the 17 // documentation and/or other materials provided with the 18 // distribution. 19 // 20 // Neither the name of Texas Instruments Incorporated nor the names of 21 // its contributors may be used to endorse or promote products derived 22 // from this software without specific prior written permission. 23 // 24 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 // 36 // This is part of revision 9453 of the Stellaris Firmware Development Package. 37 // 38 //***************************************************************************** 39 40 #ifndef __HW_WATCHDOG_H__ 41 #define __HW_WATCHDOG_H__ 42 43 //***************************************************************************** 44 // 45 // The following are defines for the Watchdog Timer register offsets. 46 // 47 //***************************************************************************** 48 #define WDT_O_LOAD 0x00000000 // Watchdog Load 49 #define WDT_O_VALUE 0x00000004 // Watchdog Value 50 #define WDT_O_CTL 0x00000008 // Watchdog Control 51 #define WDT_O_ICR 0x0000000C // Watchdog Interrupt Clear 52 #define WDT_O_RIS 0x00000010 // Watchdog Raw Interrupt Status 53 #define WDT_O_MIS 0x00000014 // Watchdog Masked Interrupt Status 54 #define WDT_O_TEST 0x00000418 // Watchdog Test 55 #define WDT_O_LOCK 0x00000C00 // Watchdog Lock 56 57 //***************************************************************************** 58 // 59 // The following are defines for the bit fields in the WDT_O_LOAD register. 60 // 61 //***************************************************************************** 62 #define WDT_LOAD_M 0xFFFFFFFF // Watchdog Load Value 63 #define WDT_LOAD_S 0 64 65 //***************************************************************************** 66 // 67 // The following are defines for the bit fields in the WDT_O_VALUE register. 68 // 69 //***************************************************************************** 70 #define WDT_VALUE_M 0xFFFFFFFF // Watchdog Value 71 #define WDT_VALUE_S 0 72 73 //***************************************************************************** 74 // 75 // The following are defines for the bit fields in the WDT_O_CTL register. 76 // 77 //***************************************************************************** 78 #define WDT_CTL_WRC 0x80000000 // Write Complete 79 #define WDT_CTL_INTTYPE 0x00000004 // Watchdog Interrupt Type 80 #define WDT_CTL_RESEN 0x00000002 // Watchdog Reset Enable 81 #define WDT_CTL_INTEN 0x00000001 // Watchdog Interrupt Enable 82 83 //***************************************************************************** 84 // 85 // The following are defines for the bit fields in the WDT_O_ICR register. 86 // 87 //***************************************************************************** 88 #define WDT_ICR_M 0xFFFFFFFF // Watchdog Interrupt Clear 89 #define WDT_ICR_S 0 90 91 //***************************************************************************** 92 // 93 // The following are defines for the bit fields in the WDT_O_RIS register. 94 // 95 //***************************************************************************** 96 #define WDT_RIS_WDTRIS 0x00000001 // Watchdog Raw Interrupt Status 97 98 //***************************************************************************** 99 // 100 // The following are defines for the bit fields in the WDT_O_MIS register. 101 // 102 //***************************************************************************** 103 #define WDT_MIS_WDTMIS 0x00000001 // Watchdog Masked Interrupt Status 104 105 //***************************************************************************** 106 // 107 // The following are defines for the bit fields in the WDT_O_TEST register. 108 // 109 //***************************************************************************** 110 #define WDT_TEST_STALL 0x00000100 // Watchdog Stall Enable 111 112 //***************************************************************************** 113 // 114 // The following are defines for the bit fields in the WDT_O_LOCK register. 115 // 116 //***************************************************************************** 117 #define WDT_LOCK_M 0xFFFFFFFF // Watchdog Lock 118 #define WDT_LOCK_UNLOCKED 0x00000000 // Unlocked 119 #define WDT_LOCK_LOCKED 0x00000001 // Locked 120 #define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer 121 122 //***************************************************************************** 123 // 124 // The following are defines for the bit fields in the WDT_ISR, WDT_RIS, and 125 // WDT_MIS registers. 126 // 127 //***************************************************************************** 128 #define WDT_INT_TIMEOUT 0x00000001 // Watchdog timer expired 129 130 //***************************************************************************** 131 // 132 // The following definitions are deprecated. 133 // 134 //***************************************************************************** 135 #ifndef DEPRECATED 136 137 //***************************************************************************** 138 // 139 // The following are deprecated defines for the Watchdog Timer register 140 // offsets. 141 // 142 //***************************************************************************** 143 #define WDT_O_PeriphID4 0x00000FD0 144 #define WDT_O_PeriphID5 0x00000FD4 145 #define WDT_O_PeriphID6 0x00000FD8 146 #define WDT_O_PeriphID7 0x00000FDC 147 #define WDT_O_PeriphID0 0x00000FE0 148 #define WDT_O_PeriphID1 0x00000FE4 149 #define WDT_O_PeriphID2 0x00000FE8 150 #define WDT_O_PeriphID3 0x00000FEC 151 #define WDT_O_PCellID0 0x00000FF0 152 #define WDT_O_PCellID1 0x00000FF4 153 #define WDT_O_PCellID2 0x00000FF8 154 #define WDT_O_PCellID3 0x00000FFC 155 156 //***************************************************************************** 157 // 158 // The following are deprecated defines for the bit fields in the WDT_O_TEST 159 // register. 160 // 161 //***************************************************************************** 162 #define WDT_TEST_STALL_EN 0x00000100 // Watchdog stall enable 163 164 //***************************************************************************** 165 // 166 // The following are deprecated defines for the reset values for the WDT 167 // registers. 168 // 169 //***************************************************************************** 170 #define WDT_RV_VALUE 0xFFFFFFFF // Current value register 171 #define WDT_RV_LOAD 0xFFFFFFFF // Load register 172 #define WDT_RV_PCellID1 0x000000F0 173 #define WDT_RV_PCellID3 0x000000B1 174 #define WDT_RV_PeriphID1 0x00000018 175 #define WDT_RV_PeriphID2 0x00000018 176 #define WDT_RV_PCellID0 0x0000000D 177 #define WDT_RV_PCellID2 0x00000005 178 #define WDT_RV_PeriphID0 0x00000005 179 #define WDT_RV_PeriphID3 0x00000001 180 #define WDT_RV_PeriphID5 0x00000000 181 #define WDT_RV_RIS 0x00000000 // Raw interrupt status register 182 #define WDT_RV_CTL 0x00000000 // Control register 183 #define WDT_RV_PeriphID4 0x00000000 184 #define WDT_RV_PeriphID6 0x00000000 185 #define WDT_RV_PeriphID7 0x00000000 186 #define WDT_RV_LOCK 0x00000000 // Lock register 187 #define WDT_RV_MIS 0x00000000 // Masked interrupt status register 188 189 #endif 190 191 #endif // __HW_WATCHDOG_H__ 192