1 /**
2 ******************************************************************************
3 * @file system_stm32f0xx.c
4 * @author MCD Application Team
5 * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
6 *
7 * 1. This file provides two functions and one global variable to be called from
8 * user application:
9 * - SystemInit(): This function is called at startup just after reset and
10 * before branch to main program. This call is made inside
11 * the "startup_stm32f0xx.s" file.
12 *
13 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
14 * by the user application to setup the SysTick
15 * timer or configure other parameters.
16 *
17 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
18 * be called whenever the core clock is changed
19 * during program execution.
20 *
21 * 2. After each device reset the HSI (8 MHz) is used as system clock source.
22 * Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to
23 * configure the system clock before to branch to main program.
24 *
25 * 3. This file configures the system clock as follows:
26 *=============================================================================
27 * Supported STM32F0xx device
28 *-----------------------------------------------------------------------------
29 * System Clock source | HSI
30 *-----------------------------------------------------------------------------
31 * SYSCLK(Hz) | 8000000
32 *-----------------------------------------------------------------------------
33 * HCLK(Hz) | 8000000
34 *-----------------------------------------------------------------------------
35 * AHB Prescaler | 1
36 *-----------------------------------------------------------------------------
37 * APB1 Prescaler | 1
38 *-----------------------------------------------------------------------------
39 *=============================================================================
40 ******************************************************************************
41 * @attention
42 *
43 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
44 *
45 * Redistribution and use in source and binary forms, with or without modification,
46 * are permitted provided that the following conditions are met:
47 * 1. Redistributions of source code must retain the above copyright notice,
48 * this list of conditions and the following disclaimer.
49 * 2. Redistributions in binary form must reproduce the above copyright notice,
50 * this list of conditions and the following disclaimer in the documentation
51 * and/or other materials provided with the distribution.
52 * 3. Neither the name of STMicroelectronics nor the names of its contributors
53 * may be used to endorse or promote products derived from this software
54 * without specific prior written permission.
55 *
56 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
57 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
58 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
59 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
60 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
61 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
62 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
63 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
64 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
65 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
66 *
67 ******************************************************************************
68 */
69
70 /** @addtogroup CMSIS
71 * @{
72 */
73
74 /** @addtogroup stm32f0xx_system
75 * @{
76 */
77
78 /** @addtogroup STM32F0xx_System_Private_Includes
79 * @{
80 */
81
82 #include "stm32f0xx.h"
83
84 /**
85 * @}
86 */
87
88 /** @addtogroup STM32F0xx_System_Private_TypesDefinitions
89 * @{
90 */
91
92 /**
93 * @}
94 */
95
96 /** @addtogroup STM32F0xx_System_Private_Defines
97 * @{
98 */
99 #if !defined (HSE_VALUE)
100 #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
101 This value can be provided and adapted by the user application. */
102 #endif /* HSE_VALUE */
103
104 #if !defined (HSI_VALUE)
105 #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
106 This value can be provided and adapted by the user application. */
107 #endif /* HSI_VALUE */
108
109 #if !defined (HSI48_VALUE)
110 #define HSI48_VALUE ((uint32_t)48000000) /*!< Default value of the HSI48 Internal oscillator in Hz.
111 This value can be provided and adapted by the user application. */
112 #endif /* HSI48_VALUE */
113 /**
114 * @}
115 */
116
117 /** @addtogroup STM32F0xx_System_Private_Macros
118 * @{
119 */
120
121 /**
122 * @}
123 */
124
125 /** @addtogroup STM32F0xx_System_Private_Variables
126 * @{
127 */
128 /* This variable is updated in three ways:
129 1) by calling CMSIS function SystemCoreClockUpdate()
130 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
131 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
132 Note: If you use this function to configure the system clock there is no need to
133 call the 2 first functions listed above, since SystemCoreClock variable is
134 updated automatically.
135 */
136 uint32_t SystemCoreClock = 8000000;
137
138 const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
139 const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
140
141 /**
142 * @}
143 */
144
145 /** @addtogroup STM32F0xx_System_Private_FunctionPrototypes
146 * @{
147 */
148
149 /**
150 * @}
151 */
152
153 /** @addtogroup STM32F0xx_System_Private_Functions
154 * @{
155 */
156
157 /**
158 * @brief Setup the microcontroller system.
159 * Initialize the default HSI clock source, vector table location and the PLL configuration is reset.
160 * @param None
161 * @retval None
162 */
SystemInit(void)163 void SystemInit(void)
164 {
165 /* Reset the RCC clock configuration to the default reset state ------------*/
166 /* Set HSION bit */
167 RCC->CR |= (uint32_t)0x00000001U;
168
169 #if defined (STM32F051x8) || defined (STM32F058x8)
170 /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
171 RCC->CFGR &= (uint32_t)0xF8FFB80CU;
172 #else
173 /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */
174 RCC->CFGR &= (uint32_t)0x08FFB80CU;
175 #endif /* STM32F051x8 or STM32F058x8 */
176
177 /* Reset HSEON, CSSON and PLLON bits */
178 RCC->CR &= (uint32_t)0xFEF6FFFFU;
179
180 /* Reset HSEBYP bit */
181 RCC->CR &= (uint32_t)0xFFFBFFFFU;
182
183 /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
184 RCC->CFGR &= (uint32_t)0xFFC0FFFFU;
185
186 /* Reset PREDIV[3:0] bits */
187 RCC->CFGR2 &= (uint32_t)0xFFFFFFF0U;
188
189 #if defined (STM32F072xB) || defined (STM32F078xx)
190 /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
191 RCC->CFGR3 &= (uint32_t)0xFFFCFE2CU;
192 #elif defined (STM32F071xB)
193 /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
194 RCC->CFGR3 &= (uint32_t)0xFFFFCEACU;
195 #elif defined (STM32F091xC) || defined (STM32F098xx)
196 /* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
197 RCC->CFGR3 &= (uint32_t)0xFFF0FEACU;
198 #elif defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC)
199 /* Reset USART1SW[1:0], I2C1SW and ADCSW bits */
200 RCC->CFGR3 &= (uint32_t)0xFFFFFEECU;
201 #elif defined (STM32F051x8) || defined (STM32F058xx)
202 /* Reset USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
203 RCC->CFGR3 &= (uint32_t)0xFFFFFEACU;
204 #elif defined (STM32F042x6) || defined (STM32F048xx)
205 /* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
206 RCC->CFGR3 &= (uint32_t)0xFFFFFE2CU;
207 #elif defined (STM32F070x6) || defined (STM32F070xB)
208 /* Reset USART1SW[1:0], I2C1SW, USBSW and ADCSW bits */
209 RCC->CFGR3 &= (uint32_t)0xFFFFFE6CU;
210 /* Set default USB clock to PLLCLK, since there is no HSI48 */
211 RCC->CFGR3 |= (uint32_t)0x00000080U;
212 #else
213 #warning "No target selected"
214 #endif
215
216 /* Reset HSI14 bit */
217 RCC->CR2 &= (uint32_t)0xFFFFFFFEU;
218
219 /* Disable all interrupts */
220 RCC->CIR = 0x00000000U;
221
222 }
223
224 /**
225 * @brief Update SystemCoreClock variable according to Clock Register Values.
226 * The SystemCoreClock variable contains the core clock (HCLK), it can
227 * be used by the user application to setup the SysTick timer or configure
228 * other parameters.
229 *
230 * @note Each time the core clock (HCLK) changes, this function must be called
231 * to update SystemCoreClock variable value. Otherwise, any configuration
232 * based on this variable will be incorrect.
233 *
234 * @note - The system frequency computed by this function is not the real
235 * frequency in the chip. It is calculated based on the predefined
236 * constant and the selected clock source:
237 *
238 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
239 *
240 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
241 *
242 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
243 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
244 *
245 * (*) HSI_VALUE is a constant defined in stm32f0xx_hal.h file (default value
246 * 8 MHz) but the real value may vary depending on the variations
247 * in voltage and temperature.
248 *
249 * (**) HSE_VALUE is a constant defined in stm32f0xx_hal.h file (default value
250 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
251 * frequency of the crystal used. Otherwise, this function may
252 * have wrong result.
253 *
254 * - The result of this function could be not correct when using fractional
255 * value for HSE crystal.
256 *
257 * @param None
258 * @retval None
259 */
SystemCoreClockUpdate(void)260 void SystemCoreClockUpdate (void)
261 {
262 uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;
263
264 /* Get SYSCLK source -------------------------------------------------------*/
265 tmp = RCC->CFGR & RCC_CFGR_SWS;
266
267 switch (tmp)
268 {
269 case RCC_CFGR_SWS_HSI: /* HSI used as system clock */
270 SystemCoreClock = HSI_VALUE;
271 break;
272 case RCC_CFGR_SWS_HSE: /* HSE used as system clock */
273 SystemCoreClock = HSE_VALUE;
274 break;
275 case RCC_CFGR_SWS_PLL: /* PLL used as system clock */
276 /* Get PLL clock source and multiplication factor ----------------------*/
277 pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
278 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
279 pllmull = ( pllmull >> 18) + 2;
280 predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
281
282 if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
283 {
284 /* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */
285 SystemCoreClock = (HSE_VALUE/predivfactor) * pllmull;
286 }
287 #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
288 else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV)
289 {
290 /* HSI48 used as PLL clock source : SystemCoreClock = HSI48/PREDIV * PLLMUL */
291 SystemCoreClock = (HSI48_VALUE/predivfactor) * pllmull;
292 }
293 #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
294 else
295 {
296 #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) \
297 || defined(STM32F078xx) || defined(STM32F071xB) || defined(STM32F072xB) \
298 || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
299 /* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */
300 SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull;
301 #else
302 /* HSI used as PLL clock source : SystemCoreClock = HSI/2 * PLLMUL */
303 SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
304 #endif /* STM32F042x6 || STM32F048xx || STM32F070x6 ||
305 STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB ||
306 STM32F091xC || STM32F098xx || STM32F030xC */
307 }
308 break;
309 default: /* HSI used as system clock */
310 SystemCoreClock = HSI_VALUE;
311 break;
312 }
313 /* Compute HCLK clock frequency ----------------*/
314 /* Get HCLK prescaler */
315 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
316 /* HCLK clock frequency */
317 SystemCoreClock >>= tmp;
318 }
319
320 /**
321 * @}
322 */
323
324 /**
325 * @}
326 */
327
328 /**
329 * @}
330 */
331
332 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
333
334