1 /*
2 * Copyright (c) 2016 Brian Swetland
3 *
4 * Use of this source code is governed by a MIT-style
5 * license that can be found in the LICENSE file or at
6 * https://opensource.org/licenses/MIT
7 */
8
9 #include <lk/debug.h>
10 #include <platform.h>
11 #include <arch/arm/cm.h>
12
13 #include <driverlib/prcm.h>
14 #include <driverlib/ioc.h>
15 #include <driverlib/uart.h>
16 #include <driverlib/osc.h>
17
18 // if GPIO_UART_?R are defined, route UART there
19 #include <target/gpioconfig.h>
20
21 void trimDevice(void);
22
23 #define UART0_BASE 0x40001000
24
platform_early_init(void)25 void platform_early_init(void) {
26 trimDevice();
27
28 PRCMPowerDomainOn(PRCM_DOMAIN_SERIAL);
29 while (PRCMPowerDomainStatus(PRCM_DOMAIN_SERIAL) != PRCM_DOMAIN_POWER_ON) ;
30
31 PRCMPowerDomainOn(PRCM_DOMAIN_PERIPH);
32 while (PRCMPowerDomainStatus(PRCM_DOMAIN_PERIPH) != PRCM_DOMAIN_POWER_ON) ;
33
34 PRCMPeripheralRunEnable(PRCM_PERIPH_UART0);
35 PRCMPeripheralRunEnable(PRCM_PERIPH_GPIO);
36 PRCMLoadSet();
37
38 #ifdef GPIO_UART_TX
39 IOCPortConfigureSet(GPIO_UART_TX, IOC_PORT_MCU_UART0_TX, 0);
40 #endif
41 #ifdef GPIO_UART_RX
42 IOCPortConfigureSet(GPIO_UART_RX, IOC_PORT_MCU_UART0_RX, IOC_INPUT_ENABLE);
43 #endif
44
45 UARTConfigSetExpClk(UART0_BASE, 48000000, 115200,
46 UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE);
47 UARTEnable(UART0_BASE);
48
49 arm_cm_systick_init(48000000);
50
51 // switch to 24MHz XOSC
52 OSCInterfaceEnable();
53 OSCClockSourceSet(OSC_SRC_CLK_HF, OSC_XOSC_HF);
54 OSCHfSourceSwitch();
55
56 #if 0
57 dprintf(INFO, "hf clk src %d\n", OSCClockSourceGet(OSC_SRC_CLK_HF));
58 dprintf(INFO, "mf clk src %d\n", OSCClockSourceGet(OSC_SRC_CLK_MF));
59 dprintf(INFO, "lf clk src %d\n", OSCClockSourceGet(OSC_SRC_CLK_LF));
60 #endif
61 }
62
platform_init(void)63 void platform_init(void) {
64 }
65
66