1 /*
2 * Copyright (c) 2008 Travis Geiselbrecht
3 *
4 * Use of this source code is governed by a MIT-style
5 * license that can be found in the LICENSE file or at
6 * https://opensource.org/licenses/MIT
7 */
8 #include <lk/debug.h>
9 #include <lk/reg.h>
10 #include <dev/uart.h>
11 #include <target/debugconfig.h>
12 #include <platform/or1ksim.h>
13
14 struct uart_stat {
15 addr_t base;
16 uint32_t clk_freq;
17 uint shift;
18 };
19
20 static struct uart_stat uart[1] = {
21 { UART1_BASE, UART1_CLOCK_FREQ, 0 },
22 };
23
write_uart_reg(int port,uint reg,unsigned char data)24 static inline void write_uart_reg(int port, uint reg, unsigned char data) {
25 *(volatile unsigned char *)(uart[port].base + (reg << uart[port].shift)) = data;
26 }
27
read_uart_reg(int port,uint reg)28 static inline unsigned char read_uart_reg(int port, uint reg) {
29 return *(volatile unsigned char *)(uart[port].base + (reg << uart[port].shift));
30 }
31
32 #define UART_RHR 0
33 #define UART_THR 0
34 #define UART_DLL 0
35 #define UART_IER 1
36 #define UART_DLH 1
37 #define UART_IIR 2
38 #define UART_FCR 2
39 #define UART_EFR 2
40 #define UART_LCR 3
41 #define UART_MCR 4
42 #define UART_LSR 5
43 #define UART_MSR 6
44 #define UART_TCR 6
45 #define UART_SPR 7
46 #define UART_TLR 7
47 #define UART_MDR1 8
48 #define UART_MDR2 9
49 #define UART_SFLSR 10
50 #define UART_RESUME 11
51 #define UART_TXFLL 10
52 #define UART_TXFLH 11
53 #define UART_SFREGL 12
54 #define UART_SFREGH 13
55 #define UART_RXFLL 12
56 #define UART_RXFLH 13
57 #define UART_BLR 14
58 #define UART_UASR 14
59 #define UART_ACREG 15
60 #define UART_SCR 16
61 #define UART_SSR 17
62 #define UART_EBLR 18
63 #define UART_MVR 19
64 #define UART_SYSC 20
65
66 #define LCR_8N1 0x03
67
68 #define FCR_FIFO_EN 0x01 /* Fifo enable */
69 #define FCR_RXSR 0x02 /* Receiver soft reset */
70 #define FCR_TXSR 0x04 /* Transmitter soft reset */
71
72 #define MCR_DTR 0x01
73 #define MCR_RTS 0x02
74 #define MCR_DMA_EN 0x04
75 #define MCR_TX_DFR 0x08
76
77 #define LCR_WLS_MSK 0x03 /* character length select mask */
78 #define LCR_WLS_5 0x00 /* 5 bit character length */
79 #define LCR_WLS_6 0x01 /* 6 bit character length */
80 #define LCR_WLS_7 0x02 /* 7 bit character length */
81 #define LCR_WLS_8 0x03 /* 8 bit character length */
82 #define LCR_STB 0x04 /* Number of stop Bits, off = 1, on = 1.5 or 2) */
83 #define LCR_PEN 0x08 /* Parity eneble */
84 #define LCR_EPS 0x10 /* Even Parity Select */
85 #define LCR_STKP 0x20 /* Stick Parity */
86 #define LCR_SBRK 0x40 /* Set Break */
87 #define LCR_BKSE 0x80 /* Bank select enable */
88
89 #define LSR_DR 0x01 /* Data ready */
90 #define LSR_OE 0x02 /* Overrun */
91 #define LSR_PE 0x04 /* Parity error */
92 #define LSR_FE 0x08 /* Framing error */
93 #define LSR_BI 0x10 /* Break */
94 #define LSR_THRE 0x20 /* Xmit holding register empty */
95 #define LSR_TEMT 0x40 /* Xmitter empty */
96 #define LSR_ERR 0x80 /* Error */
97
98 #define LCRVAL LCR_8N1 /* 8 data, 1 stop, no parity */
99 #define MCRVAL (MCR_DTR | MCR_RTS) /* RTS/DTR */
100 #define FCRVAL (FCR_FIFO_EN | FCR_RXSR | FCR_TXSR) /* Clear & enable FIFOs */
101
uart_init_port(int port,uint baud)102 void uart_init_port(int port, uint baud) {
103 /* clear the tx & rx fifo and disable */
104 uint16_t baud_divisor = (uart[port].clk_freq / 16 / baud);
105
106 write_uart_reg(port, UART_IER, 0);
107 write_uart_reg(port, UART_LCR, LCR_BKSE | LCRVAL); // config mode A
108 write_uart_reg(port, UART_DLL, baud_divisor & 0xff);
109 write_uart_reg(port, UART_DLH, (baud_divisor >> 8) & 0xff);
110 write_uart_reg(port, UART_LCR, LCRVAL); // operational mode
111 write_uart_reg(port, UART_MCR, MCRVAL);
112 write_uart_reg(port, UART_FCR, FCRVAL);
113 }
114
uart_init_early(void)115 void uart_init_early(void) {
116 uart_init_port(DEBUG_UART, 115200);
117 }
118
uart_init(void)119 void uart_init(void) {
120 }
121
uart_putc(int port,char c)122 int uart_putc(int port, char c ) {
123 while (!(read_uart_reg(port, UART_LSR) & (1<<6))) // wait for the last char to get out
124 ;
125 write_uart_reg(port, UART_THR, c);
126 return 0;
127 }
128
uart_getc(int port,bool wait)129 int uart_getc(int port, bool wait) { /* returns -1 if no data available */
130 if (wait) {
131 while (!(read_uart_reg(port, UART_LSR) & (1<<0))) // wait for data to show up in the rx fifo
132 ;
133 } else {
134 if (!(read_uart_reg(port, UART_LSR) & (1<<0)))
135 return -1;
136 }
137 return read_uart_reg(port, UART_RHR);
138 }
139
uart_flush_tx(int port)140 void uart_flush_tx(int port) {
141 while (!(read_uart_reg(port, UART_LSR) & (1<<6))) // wait for the last char to get out
142 ;
143 }
144
uart_flush_rx(int port)145 void uart_flush_rx(int port) {
146 // empty the rx fifo
147 while (read_uart_reg(port, UART_LSR) & (1<<0)) {
148 volatile char c = read_uart_reg(port, UART_RHR);
149 (void)c;
150 }
151 }
152