1 /* 2 * Copyright (c) 2012 Travis Geiselbrecht 3 * 4 * Use of this source code is governed by a MIT-style 5 * license that can be found in the LICENSE file or at 6 * https://opensource.org/licenses/MIT 7 */ 8 #include <lk/debug.h> 9 #include <assert.h> 10 #include <dev/gpio.h> 11 #include <platform/gpio.h> 12 #include "ti_driverlib.h" 13 port_to_pointer(unsigned int port)14static void *port_to_pointer(unsigned int port) { 15 switch (port) { 16 default: 17 case GPIO_PORT_A: 18 return (void *)GPIO_PORTA_AHB_BASE; 19 case GPIO_PORT_B: 20 return (void *)GPIO_PORTB_AHB_BASE; 21 case GPIO_PORT_C: 22 return (void *)GPIO_PORTC_AHB_BASE; 23 case GPIO_PORT_D: 24 return (void *)GPIO_PORTD_AHB_BASE; 25 case GPIO_PORT_E: 26 return (void *)GPIO_PORTE_AHB_BASE; 27 case GPIO_PORT_F: 28 return (void *)GPIO_PORTF_AHB_BASE; 29 case GPIO_PORT_G: 30 return (void *)GPIO_PORTG_AHB_BASE; 31 case GPIO_PORT_H: 32 return (void *)GPIO_PORTH_AHB_BASE; 33 case GPIO_PORT_J: 34 return (void *)GPIO_PORTJ_BASE; 35 case GPIO_PORT_K: 36 return (void *)GPIO_PORTK_BASE; 37 case GPIO_PORT_L: 38 return (void *)GPIO_PORTL_BASE; 39 case GPIO_PORT_M: 40 return (void *)GPIO_PORTM_BASE; 41 case GPIO_PORT_N: 42 return (void *)GPIO_PORTN_BASE; 43 case GPIO_PORT_P: 44 return (void *)GPIO_PORTP_BASE; 45 case GPIO_PORT_Q: 46 return (void *)GPIO_PORTQ_BASE; 47 } 48 } 49 stellaris_gpio_early_init(void)50void stellaris_gpio_early_init(void) { 51 /* Disable hitting the AHB bits on this target, which 52 * is probably qemu emulated. QEMU does not implement 53 * these registers and will crash. 54 */ 55 #if !TARGET_LM3S6965EVB 56 SysCtlGPIOAHBEnable(SYSCTL_PERIPH_GPIOA); 57 SysCtlGPIOAHBEnable(SYSCTL_PERIPH_GPIOB); 58 SysCtlGPIOAHBEnable(SYSCTL_PERIPH_GPIOC); 59 SysCtlGPIOAHBEnable(SYSCTL_PERIPH_GPIOD); 60 SysCtlGPIOAHBEnable(SYSCTL_PERIPH_GPIOE); 61 SysCtlGPIOAHBEnable(SYSCTL_PERIPH_GPIOF); 62 SysCtlGPIOAHBEnable(SYSCTL_PERIPH_GPIOG); 63 SysCtlGPIOAHBEnable(SYSCTL_PERIPH_GPIOH); 64 #endif 65 66 SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); 67 SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB); 68 SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC); 69 SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD); 70 SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOE); 71 SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF); 72 SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOG); 73 SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOH); 74 SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOJ); 75 } 76 stellaris_gpio_init(void)77void stellaris_gpio_init(void) { 78 } 79 80 #if 0 81 int gpio_config(unsigned nr, unsigned flags) { 82 uint port = GPIO_PORT(nr); 83 uint pin = GPIO_PIN(nr); 84 85 enable_port(port); 86 87 GPIO_InitTypeDef init; 88 init.GPIO_Speed = GPIO_Speed_50MHz; 89 90 init.GPIO_Pin = (1 << pin); 91 92 if (flags & GPIO_STM32_AF) { 93 if (flags & GPIO_STM32_OD) 94 init.GPIO_Mode = GPIO_Mode_Out_OD; 95 else 96 init.GPIO_Mode = GPIO_Mode_AF_PP; 97 } else if (flags & GPIO_OUTPUT) { 98 if (flags & GPIO_STM32_OD) 99 init.GPIO_Mode = GPIO_Mode_Out_OD; 100 else 101 init.GPIO_Mode = GPIO_Mode_Out_PP; 102 } else { // GPIO_INPUT 103 if (flags & GPIO_PULLUP) { 104 init.GPIO_Mode = GPIO_Mode_IPU; 105 } else if (flags & GPIO_PULLDOWN) { 106 init.GPIO_Mode = GPIO_Mode_IPD; 107 } else { 108 init.GPIO_Mode = GPIO_Mode_IN_FLOATING; 109 } 110 } 111 112 GPIO_Init(port_to_pointer(port), &init); 113 114 return 0; 115 } 116 #endif 117 gpio_set(unsigned nr,unsigned on)118void gpio_set(unsigned nr, unsigned on) { 119 GPIOPinWrite((unsigned int)port_to_pointer(GPIO_PORT(nr)), 1 << GPIO_PIN(nr), on ? (1 << GPIO_PIN(nr)) : 0); 120 } 121 gpio_get(unsigned nr)122int gpio_get(unsigned nr) { 123 return GPIOPinRead((unsigned int)port_to_pointer(GPIO_PORT(nr)), 1 << GPIO_PIN(nr)); 124 } 125 126 127