1 
2 #include "platform/rcc.h"
3 
4 #include <stm32f0xx.h>
5 
stm32_rcc_get_clock_en_reg(stm32_rcc_clk_t clock)6 static __IO uint32_t *stm32_rcc_get_clock_en_reg(stm32_rcc_clk_t clock) {
7     switch (STM32_RCC_CLK_REG(clock)) {
8         case STM32_RCC_REG_AHB:
9             return &RCC->AHBENR;
10 
11         case STM32_RCC_REG_APB1:
12             return &RCC->APB1ENR;
13 
14         case STM32_RCC_REG_APB2:
15             return &RCC->APB2ENR;
16 
17         default:
18             return NULL;
19     }
20 }
21 
stm32_rcc_get_clock_rst_reg(stm32_rcc_clk_t clock)22 static __IO uint32_t *stm32_rcc_get_clock_rst_reg(stm32_rcc_clk_t clock) {
23     switch (STM32_RCC_CLK_REG(clock)) {
24         case STM32_RCC_REG_AHB:
25             return &RCC->AHBRSTR;
26 
27         case STM32_RCC_REG_APB1:
28             return &RCC->APB1RSTR;
29 
30         case STM32_RCC_REG_APB2:
31             return &RCC->APB2RSTR;
32 
33         default:
34             return NULL;
35     }
36 }
37 
stm32_rcc_set_enable(stm32_rcc_clk_t clock,bool enable)38 void stm32_rcc_set_enable(stm32_rcc_clk_t clock, bool enable) {
39     __IO uint32_t *reg = stm32_rcc_get_clock_en_reg(clock);
40     if (enable) {
41         *reg |= 1 << STM32_RCC_CLK_INDEX(clock);
42     } else {
43         *reg &= ~(1 << STM32_RCC_CLK_INDEX(clock));
44     }
45 }
46 
stm32_rcc_set_reset(stm32_rcc_clk_t clock,bool reset)47 void stm32_rcc_set_reset(stm32_rcc_clk_t clock, bool reset) {
48     switch (clock) {
49         // These clocks to not have reset bits.
50         case STM32_RCC_CLK_DMA:
51         case STM32_RCC_CLK_DMA2:
52         case STM32_RCC_CLK_SRAM:
53         case STM32_RCC_CLK_FLITF:
54         case STM32_RCC_CLK_CRC:
55             return;
56 
57         default:
58             break;
59     }
60 
61     __IO uint32_t *reg = stm32_rcc_get_clock_rst_reg(clock);
62     if (reset) {
63         *reg |= 1 << STM32_RCC_CLK_INDEX(clock);
64     } else {
65         *reg &= ~(1 << STM32_RCC_CLK_INDEX(clock));
66     }
67 }
68 
69