1 /*
2 * Copyright (c) 2012 Travis Geiselbrecht
3 *
4 * Use of this source code is governed by a MIT-style
5 * license that can be found in the LICENSE file or at
6 * https://opensource.org/licenses/MIT
7 */
8 #include <lk/debug.h>
9 #include <lk/compiler.h>
10 #include <stm32f0xx.h>
11 #include <arch/arm/cm.h>
12 #include <platform/stm32.h>
13 #include <target/debugconfig.h>
14 #include <lib/cbuf.h>
15
16 /* un-overridden irq handler */
stm32_dummy_irq(void)17 void stm32_dummy_irq(void) {
18 arm_cm_irq_entry();
19
20 panic("unhandled irq\n");
21 }
22
23 /* a list of default handlers that are simply aliases to the dummy handler */
24 #define DEFAULT_HANDLER(x) \
25 void stm32_##x(void) __WEAK_ALIAS("stm32_dummy_irq");
26
27 DEFAULT_HANDLER(WWDG_IRQ)
28 DEFAULT_HANDLER(PVD_IRQ)
29 DEFAULT_HANDLER(RTC_IRQ)
30 DEFAULT_HANDLER(FLASH_IRQ)
31 DEFAULT_HANDLER(RCC_IRQ)
32 DEFAULT_HANDLER(EXTI0_1_IRQ)
33 DEFAULT_HANDLER(EXTI2_3_IRQ)
34 DEFAULT_HANDLER(EXTI4_15_IRQ)
35 DEFAULT_HANDLER(TSC_IRQ)
36 DEFAULT_HANDLER(DMA1_Channel1_IRQ)
37 DEFAULT_HANDLER(DMA1_Channel2_3_IRQ)
38 DEFAULT_HANDLER(DMA1_Channel4_5_6_7_IRQ)
39 DEFAULT_HANDLER(ADC1_COMP_IRQ)
40 DEFAULT_HANDLER(TIM1_BRK_UP_TRG_COM_IRQ)
41 DEFAULT_HANDLER(TIM1_CC_IRQ)
42 DEFAULT_HANDLER(TIM2_IRQ)
43 DEFAULT_HANDLER(TIM3_IRQ)
44 DEFAULT_HANDLER(TIM6_DAC_IRQ)
45 DEFAULT_HANDLER(TIM7_IRQ)
46 DEFAULT_HANDLER(TIM14_IRQ)
47 DEFAULT_HANDLER(TIM15_IRQ)
48 DEFAULT_HANDLER(TIM16_IRQ)
49 DEFAULT_HANDLER(TIM17_IRQ)
50 DEFAULT_HANDLER(I2C1_IRQ)
51 DEFAULT_HANDLER(I2C2_IRQ)
52 DEFAULT_HANDLER(SPI1_IRQ)
53 DEFAULT_HANDLER(SPI2_IRQ)
54 DEFAULT_HANDLER(USART1_IRQ)
55 DEFAULT_HANDLER(USART2_IRQ)
56 DEFAULT_HANDLER(USART3_4_IRQ)
57 DEFAULT_HANDLER(CEC_CAN_IRQ)
58 DEFAULT_HANDLER(USB_IRQ)
59
60 #define VECTAB_ENTRY(x) [x##n] = stm32_##x
61
62 /*
63 * Appended to the end of the main vector table.
64 *
65 * The STM32F072 and STM32F070 have different vector tables. We can't
66 * #ifdef on the existance of the constans like PVD_IRQn because they
67 * are enum values. Right now, since we only have two supported variants,
68 * we're switching on the variant. This will likely not scale.
69 */
70
71 const void *const __SECTION(".text.boot.vectab2") vectab2[] = {
72 VECTAB_ENTRY(WWDG_IRQ), // Window WatchDog Interrupt
73 #ifdef STM32F072
74 VECTAB_ENTRY(PVD_IRQ), // PVD through EXTI Line detect Interrupt
75 #endif
76 VECTAB_ENTRY(RTC_IRQ), // RTC through EXTI Line Interrupt
77 VECTAB_ENTRY(FLASH_IRQ), // FLASH Interrupt
78 VECTAB_ENTRY(RCC_IRQ), // RCC Interrupt
79 VECTAB_ENTRY(EXTI0_1_IRQ), // EXTI Line 0 and 1 Interrupts
80 VECTAB_ENTRY(EXTI2_3_IRQ), // EXTI Line 2 and 3 Interrupts
81 VECTAB_ENTRY(EXTI4_15_IRQ), // EXTI Line 4 to 15 Interrupts
82 #ifdef STM32F072
83 VECTAB_ENTRY(TSC_IRQ), // Touch sense controller Interrupt
84 #endif
85 VECTAB_ENTRY(DMA1_Channel1_IRQ), // DMA1 Channel 1 Interrupt
86 VECTAB_ENTRY(DMA1_Channel2_3_IRQ), // DMA1 Channel 2 and Channel 3 Interrupts
87 VECTAB_ENTRY(DMA1_Channel4_5_6_7_IRQ), // DMA1 Channels 4-7 Interrupts
88 VECTAB_ENTRY(ADC1_COMP_IRQ), // ADC1, COMP1 and COMP2 Interrupts
89 VECTAB_ENTRY(TIM1_BRK_UP_TRG_COM_IRQ), // TIM1 Break, Update, Trigger and Commutation Interrupts
90 VECTAB_ENTRY(TIM1_CC_IRQ), // TIM1 Capture Compare Interrupt
91 #ifdef STM32F072
92 VECTAB_ENTRY(TIM2_IRQ), // TIM2 Interrupt
93 #endif
94 #ifdef STM32F072
95 VECTAB_ENTRY(TIM3_IRQ), // TIM3 Interrupt
96 #endif
97 VECTAB_ENTRY(TIM6_DAC_IRQ), // TIM6 and DAC Interrupts
98 #ifdef STM32F072
99 VECTAB_ENTRY(TIM7_IRQ), // TIM7 Interrupts
100 #endif
101 #ifdef STM32F072
102 VECTAB_ENTRY(TIM14_IRQ), // TIM14 Interrupt
103 #endif
104 #ifdef STM32F072
105 VECTAB_ENTRY(TIM15_IRQ), // TIM15 Interrupt
106 #endif
107 #ifdef STM32F072
108 VECTAB_ENTRY(TIM16_IRQ), // TIM16 Interrupt
109 #endif
110 #ifdef STM32F072
111 VECTAB_ENTRY(TIM17_IRQ), // TIM17 Interrupt
112 #endif
113 VECTAB_ENTRY(I2C1_IRQ), // I2C1 Interrupt
114 VECTAB_ENTRY(I2C2_IRQ), // I2C2 Interrupt
115 VECTAB_ENTRY(SPI1_IRQ), // SPI1 Interrupt
116 VECTAB_ENTRY(SPI2_IRQ), // SPI2 Interrupt
117 VECTAB_ENTRY(USART1_IRQ), // USART1 Interrupt
118 VECTAB_ENTRY(USART2_IRQ), // USART2 Interrupt
119 VECTAB_ENTRY(USART3_4_IRQ), // USART3 and USART4 Interrupts
120 #ifdef STM32F072
121 VECTAB_ENTRY(CEC_CAN_IRQ), // CEC Interrupt
122 #endif
123 VECTAB_ENTRY(USB_IRQ), // USB Low Priority global Interrupt
124 };
125