1 /*
2 * Copyright (c) 2012 Travis Geiselbrecht
3 *
4 * Use of this source code is governed by a MIT-style
5 * license that can be found in the LICENSE file or at
6 * https://opensource.org/licenses/MIT
7 */
8 #include <lk/debug.h>
9 #include <lk/compiler.h>
10 #include <stm32f2xx.h>
11 #include <arch/arm/cm.h>
12 #include <platform/stm32.h>
13 #include <target/debugconfig.h>
14 #include <lib/cbuf.h>
15
16 /* un-overridden irq handler */
stm32_dummy_irq(void)17 void stm32_dummy_irq(void) {
18 arm_cm_irq_entry();
19
20 panic("unhandled irq\n");
21 }
22
23 /* a list of default handlers that are simply aliases to the dummy handler */
24 #define DEFAULT_HANDLER(x) \
25 void stm32_##x(void) __WEAK_ALIAS("stm32_dummy_irq");
26
27 DEFAULT_HANDLER(WWDG_IRQ);
28 DEFAULT_HANDLER(PVD_IRQ);
29 DEFAULT_HANDLER(TAMP_STAMP_IRQ);
30 DEFAULT_HANDLER(RTC_WKUP_IRQ);
31 DEFAULT_HANDLER(FLASH_IRQ);
32 DEFAULT_HANDLER(RCC_IRQ);
33 DEFAULT_HANDLER(EXTI0_IRQ);
34 DEFAULT_HANDLER(EXTI1_IRQ);
35 DEFAULT_HANDLER(EXTI2_IRQ);
36 DEFAULT_HANDLER(EXTI3_IRQ);
37 DEFAULT_HANDLER(EXTI4_IRQ);
38
39 DEFAULT_HANDLER(DMA1_Stream0_IRQ);
40 DEFAULT_HANDLER(DMA1_Stream1_IRQ);
41 DEFAULT_HANDLER(DMA1_Stream2_IRQ);
42 DEFAULT_HANDLER(DMA1_Stream3_IRQ);
43 DEFAULT_HANDLER(DMA1_Stream4_IRQ);
44 DEFAULT_HANDLER(DMA1_Stream5_IRQ);
45 DEFAULT_HANDLER(DMA1_Stream6_IRQ);
46
47 DEFAULT_HANDLER(ADC_IRQ);
48 DEFAULT_HANDLER(CAN1_TX_IRQ);
49 DEFAULT_HANDLER(CAN1_RX0_IRQ);
50 DEFAULT_HANDLER(CAN1_RX1_IRQ);
51 DEFAULT_HANDLER(CAN1_SCE_IRQ);
52 DEFAULT_HANDLER(EXTI9_5_IRQ);
53
54 DEFAULT_HANDLER(TIM1_BRK_TIM9_IRQ);
55 DEFAULT_HANDLER(TIM1_UP_TIM10_IRQ);
56 DEFAULT_HANDLER(TIM1_TRG_COM_TIM11_IRQ);
57 DEFAULT_HANDLER(TIM1_CC_IRQ);
58 DEFAULT_HANDLER(TIM2_IRQ);
59 DEFAULT_HANDLER(TIM3_IRQ);
60 DEFAULT_HANDLER(TIM4_IRQ);
61
62 DEFAULT_HANDLER(I2C1_EV_IRQ);
63 DEFAULT_HANDLER(I2C1_ER_IRQ);
64 DEFAULT_HANDLER(I2C2_EV_IRQ);
65 DEFAULT_HANDLER(I2C2_ER_IRQ);
66
67 DEFAULT_HANDLER(SPI1_IRQ);
68 DEFAULT_HANDLER(SPI2_IRQ);
69
70 DEFAULT_HANDLER(USART1_IRQ);
71 DEFAULT_HANDLER(USART2_IRQ);
72 DEFAULT_HANDLER(USART3_IRQ);
73
74 DEFAULT_HANDLER(EXTI15_10_IRQ);
75 DEFAULT_HANDLER(RTC_Alarm_IRQ);
76 DEFAULT_HANDLER(OTG_FS_WKUP_IRQ);
77 DEFAULT_HANDLER(TIM8_BRK_TIM12_IRQ);
78 DEFAULT_HANDLER(TIM8_UP_TIM13_IRQ);
79 DEFAULT_HANDLER(TIM8_TRG_COM_TIM14_IRQ);
80 DEFAULT_HANDLER(TIM8_CC_IRQ);
81 DEFAULT_HANDLER(DMA1_Stream7_IRQ);
82 DEFAULT_HANDLER(FSMC_IRQ);
83 DEFAULT_HANDLER(SDIO_IRQ);
84 DEFAULT_HANDLER(TIM5_IRQ);
85 DEFAULT_HANDLER(SPI3_IRQ);
86 DEFAULT_HANDLER(UART4_IRQ);
87 DEFAULT_HANDLER(UART5_IRQ);
88 DEFAULT_HANDLER(TIM6_DAC_IRQ);
89 DEFAULT_HANDLER(TIM7_IRQ);
90
91 DEFAULT_HANDLER(DMA2_Stream0_IRQ);
92 DEFAULT_HANDLER(DMA2_Stream1_IRQ);
93 DEFAULT_HANDLER(DMA2_Stream2_IRQ);
94 DEFAULT_HANDLER(DMA2_Stream3_IRQ);
95 DEFAULT_HANDLER(DMA2_Stream4_IRQ);
96
97 DEFAULT_HANDLER(ETH_IRQ);
98 DEFAULT_HANDLER(ETH_WKUP_IRQ);
99 DEFAULT_HANDLER(CAN2_TX_IRQ);
100 DEFAULT_HANDLER(CAN2_RX0_IRQ);
101 DEFAULT_HANDLER(CAN2_RX1_IRQ);
102 DEFAULT_HANDLER(CAN2_SCE_IRQ);
103 DEFAULT_HANDLER(OTG_FS_IRQ);
104 DEFAULT_HANDLER(DMA2_Stream5_IRQ);
105 DEFAULT_HANDLER(DMA2_Stream6_IRQ);
106 DEFAULT_HANDLER(DMA2_Stream7_IRQ);
107 DEFAULT_HANDLER(USART6_IRQ);
108 DEFAULT_HANDLER(I2C3_EV_IRQ);
109 DEFAULT_HANDLER(I2C3_ER_IRQ);
110 DEFAULT_HANDLER(OTG_HS_EP1_OUT_IRQ);
111 DEFAULT_HANDLER(OTG_HS_EP1_IN_IRQ);
112 DEFAULT_HANDLER(OTG_HS_WKUP_IRQ);
113 DEFAULT_HANDLER(OTG_HS_IRQ);
114 DEFAULT_HANDLER(DCMI_IRQ);
115 DEFAULT_HANDLER(CRYP_IRQ);
116 DEFAULT_HANDLER(HASH_RNG_IRQ);
117
118 #define VECTAB_ENTRY(x) [x##n] = stm32_##x
119
120 /* appended to the end of the main vector table */
121 const void *const __SECTION(".text.boot.vectab2") vectab2[] = {
122 VECTAB_ENTRY(WWDG_IRQ), /* Window WatchDog Interrupt */
123 VECTAB_ENTRY(PVD_IRQ), /* PVD through EXTI Line detection Interrupt */
124 VECTAB_ENTRY(TAMP_STAMP_IRQ), /* Tamper and TimeStamp interrupts through the EXTI line */
125 VECTAB_ENTRY(RTC_WKUP_IRQ), /* RTC Wakeup interrupt through the EXTI line */
126 VECTAB_ENTRY(FLASH_IRQ), /* FLASH global Interrupt */
127 VECTAB_ENTRY(RCC_IRQ), /* RCC global Interrupt */
128 VECTAB_ENTRY(EXTI0_IRQ), /* EXTI Line0 Interrupt */
129 VECTAB_ENTRY(EXTI1_IRQ), /* EXTI Line1 Interrupt */
130 VECTAB_ENTRY(EXTI2_IRQ), /* EXTI Line2 Interrupt */
131 VECTAB_ENTRY(EXTI3_IRQ), /* EXTI Line3 Interrupt */
132 VECTAB_ENTRY(EXTI4_IRQ), /* EXTI Line4 Interrupt */
133 VECTAB_ENTRY(DMA1_Stream0_IRQ), /* DMA1 Stream 0 global Interrupt */
134 VECTAB_ENTRY(DMA1_Stream1_IRQ), /* DMA1 Stream 1 global Interrupt */
135 VECTAB_ENTRY(DMA1_Stream2_IRQ), /* DMA1 Stream 2 global Interrupt */
136 VECTAB_ENTRY(DMA1_Stream3_IRQ), /* DMA1 Stream 3 global Interrupt */
137 VECTAB_ENTRY(DMA1_Stream4_IRQ), /* DMA1 Stream 4 global Interrupt */
138 VECTAB_ENTRY(DMA1_Stream5_IRQ), /* DMA1 Stream 5 global Interrupt */
139 VECTAB_ENTRY(DMA1_Stream6_IRQ), /* DMA1 Stream 6 global Interrupt */
140 VECTAB_ENTRY(ADC_IRQ), /* ADC1, ADC2 and ADC3 global Interrupts */
141 VECTAB_ENTRY(CAN1_TX_IRQ), /* CAN1 TX Interrupt */
142 VECTAB_ENTRY(CAN1_RX0_IRQ), /* CAN1 RX0 Interrupt */
143 VECTAB_ENTRY(CAN1_RX1_IRQ), /* CAN1 RX1 Interrupt */
144 VECTAB_ENTRY(CAN1_SCE_IRQ), /* CAN1 SCE Interrupt */
145 VECTAB_ENTRY(EXTI9_5_IRQ), /* External Line[9:5] Interrupts */
146 VECTAB_ENTRY(TIM1_BRK_TIM9_IRQ), /* TIM1 Break interrupt and TIM9 global interrupt */
147 VECTAB_ENTRY(TIM1_UP_TIM10_IRQ), /* TIM1 Update Interrupt and TIM10 global interrupt */
148 VECTAB_ENTRY(TIM1_TRG_COM_TIM11_IRQ), /* TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
149 VECTAB_ENTRY(TIM1_CC_IRQ), /* TIM1 Capture Compare Interrupt */
150 VECTAB_ENTRY(TIM2_IRQ), /* TIM2 global Interrupt */
151 VECTAB_ENTRY(TIM3_IRQ), /* TIM3 global Interrupt */
152 VECTAB_ENTRY(TIM4_IRQ), /* TIM4 global Interrupt */
153 VECTAB_ENTRY(I2C1_EV_IRQ), /* I2C1 Event Interrupt */
154 VECTAB_ENTRY(I2C1_ER_IRQ), /* I2C1 Error Interrupt */
155 VECTAB_ENTRY(I2C2_EV_IRQ), /* I2C2 Event Interrupt */
156 VECTAB_ENTRY(I2C2_ER_IRQ), /* I2C2 Error Interrupt */
157 VECTAB_ENTRY(SPI1_IRQ), /* SPI1 global Interrupt */
158 VECTAB_ENTRY(SPI2_IRQ), /* SPI2 global Interrupt */
159 VECTAB_ENTRY(USART1_IRQ), /* USART1 global Interrupt */
160 VECTAB_ENTRY(USART2_IRQ), /* USART2 global Interrupt */
161 VECTAB_ENTRY(USART3_IRQ), /* USART3 global Interrupt */
162 VECTAB_ENTRY(EXTI15_10_IRQ), /* External Line[15:10] Interrupts */
163 VECTAB_ENTRY(RTC_Alarm_IRQ), /* RTC Alarm (A and B) through EXTI Line Interrupt */
164 VECTAB_ENTRY(OTG_FS_WKUP_IRQ), /* USB OTG FS Wakeup through EXTI line interrupt */
165 VECTAB_ENTRY(TIM8_BRK_TIM12_IRQ), /* TIM8 Break Interrupt and TIM12 global interrupt */
166 VECTAB_ENTRY(TIM8_UP_TIM13_IRQ), /* TIM8 Update Interrupt and TIM13 global interrupt */
167 VECTAB_ENTRY(TIM8_TRG_COM_TIM14_IRQ), /* TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
168 VECTAB_ENTRY(TIM8_CC_IRQ), /* TIM8 Capture Compare Interrupt */
169 VECTAB_ENTRY(DMA1_Stream7_IRQ), /* DMA1 Stream7 Interrupt */
170 VECTAB_ENTRY(FSMC_IRQ), /* FSMC global Interrupt */
171 VECTAB_ENTRY(SDIO_IRQ), /* SDIO global Interrupt */
172 VECTAB_ENTRY(TIM5_IRQ), /* TIM5 global Interrupt */
173 VECTAB_ENTRY(SPI3_IRQ), /* SPI3 global Interrupt */
174 VECTAB_ENTRY(UART4_IRQ), /* UART4 global Interrupt */
175 VECTAB_ENTRY(UART5_IRQ), /* UART5 global Interrupt */
176 VECTAB_ENTRY(TIM6_DAC_IRQ), /* TIM6 global and DAC1&2 underrun error interrupts */
177 VECTAB_ENTRY(TIM7_IRQ), /* TIM7 global interrupt */
178 VECTAB_ENTRY(DMA2_Stream0_IRQ), /* DMA2 Stream 0 global Interrupt */
179 VECTAB_ENTRY(DMA2_Stream1_IRQ), /* DMA2 Stream 1 global Interrupt */
180 VECTAB_ENTRY(DMA2_Stream2_IRQ), /* DMA2 Stream 2 global Interrupt */
181 VECTAB_ENTRY(DMA2_Stream3_IRQ), /* DMA2 Stream 3 global Interrupt */
182 VECTAB_ENTRY(DMA2_Stream4_IRQ), /* DMA2 Stream 4 global Interrupt */
183 VECTAB_ENTRY(ETH_IRQ), /* Ethernet global Interrupt */
184 VECTAB_ENTRY(ETH_WKUP_IRQ), /* Ethernet Wakeup through EXTI line Interrupt */
185 VECTAB_ENTRY(CAN2_TX_IRQ), /* CAN2 TX Interrupt */
186 VECTAB_ENTRY(CAN2_RX0_IRQ), /* CAN2 RX0 Interrupt */
187 VECTAB_ENTRY(CAN2_RX1_IRQ), /* CAN2 RX1 Interrupt */
188 VECTAB_ENTRY(CAN2_SCE_IRQ), /* CAN2 SCE Interrupt */
189 VECTAB_ENTRY(OTG_FS_IRQ), /* USB OTG FS global Interrupt */
190 VECTAB_ENTRY(DMA2_Stream5_IRQ), /* DMA2 Stream 5 global interrupt */
191 VECTAB_ENTRY(DMA2_Stream6_IRQ), /* DMA2 Stream 6 global interrupt */
192 VECTAB_ENTRY(DMA2_Stream7_IRQ), /* DMA2 Stream 7 global interrupt */
193 VECTAB_ENTRY(USART6_IRQ), /* USART6 global interrupt */
194 VECTAB_ENTRY(I2C3_EV_IRQ), /* I2C3 event interrupt */
195 VECTAB_ENTRY(I2C3_ER_IRQ), /* I2C3 error interrupt */
196 VECTAB_ENTRY(OTG_HS_EP1_OUT_IRQ), /* USB OTG HS End Point 1 Out global interrupt */
197 VECTAB_ENTRY(OTG_HS_EP1_IN_IRQ), /* USB OTG HS End Point 1 In global interrupt */
198 VECTAB_ENTRY(OTG_HS_WKUP_IRQ), /* USB OTG HS Wakeup through EXTI interrupt */
199 VECTAB_ENTRY(OTG_HS_IRQ), /* USB OTG HS global interrupt */
200 VECTAB_ENTRY(DCMI_IRQ), /* DCMI global interrupt */
201 VECTAB_ENTRY(CRYP_IRQ), /* CRYP crypto global interrupt */
202 VECTAB_ENTRY(HASH_RNG_IRQ), /* Hash and Rng global interrupt */
203 };
204
205