1 /*
2  * Copyright (c) 2012 Travis Geiselbrecht
3  *
4  * Use of this source code is governed by a MIT-style
5  * license that can be found in the LICENSE file or at
6  * https://opensource.org/licenses/MIT
7  */
8 #include <stdarg.h>
9 #include <lk/reg.h>
10 #include <lk/debug.h>
11 #include <stdio.h>
12 #include <kernel/thread.h>
13 #include <platform/debug.h>
14 #include <arch/ops.h>
15 #include <dev/uart.h>
16 #include <target/debugconfig.h>
17 #include <platform/stm32.h>
18 #include <stm32f4xx_rcc.h>
19 #include <stm32f4xx_usart.h>
20 #include <arch/arm/cm.h>
21 
stm32_debug_early_init(void)22 void stm32_debug_early_init(void) {
23     uart_init_early();
24 }
25 
26 /* later in the init process */
stm32_debug_init(void)27 void stm32_debug_init(void) {
28     uart_init();
29 }
30 
31 #define ITM_STIM0   0xE0000000
32 #define ITM_TCR     0xE0000E80
33 
platform_dputc(char c)34 void platform_dputc(char c) {
35     // if ITM is enabled, send character to STIM0
36     if (readl(ITM_TCR) & 1) {
37         while (!readl(ITM_STIM0)) ;
38         writeb(c, ITM_STIM0);
39     }
40 
41     if (c == '\n')
42         uart_putc(DEBUG_UART, '\r');
43     uart_putc(DEBUG_UART, c);
44 }
45 
platform_dgetc(char * c,bool wait)46 int platform_dgetc(char *c, bool wait) {
47     int ret = uart_getc(DEBUG_UART, wait);
48     if (ret == -1)
49         return -1;
50     *c = ret;
51     return 0;
52 }
53 
54 void __debugger_console_putc(char c);
55 
56 #define DCRDR 0xE000EDF8
57 
_debugmonitor(void)58 void _debugmonitor(void) {
59     u32 n;
60     arm_cm_irq_entry();
61     n = readl(DCRDR);
62     if (n & 0x80000000) {
63         switch (n >> 24) {
64             case 0x80: // write to console
65                 __debugger_console_putc(n & 0xFF);
66                 n = 0;
67                 break;
68             default:
69                 n = 0x01000000;
70         }
71         writel(n, DCRDR);
72     }
73     arm_cm_irq_exit(1);
74 }
75