1 /* 2 * Copyright (c) 2018 Travis Geiselbrecht 3 * 4 * Use of this source code is governed by a MIT-style 5 * license that can be found in the LICENSE file or at 6 * https://opensource.org/licenses/MIT 7 */ 8 #pragma once 9 10 #define SIFIVE_IRQ_WATCHDOG 1 11 #define SIFIVE_IRQ_RTC 2 12 #define SIFIVE_IRQ_UART0 3 13 #define SIFIVE_IRQ_UART1 4 14 #define SIFIVE_IRQ_QSPI0 5 15 #define SIFIVE_IRQ_QSPI1 6 16 #define SIFIVE_IRQ_QSPI2 7 17 #define SIFIVE_IRQ_GPIO_BASE 8 18 #define SIFIVE_IRQ_GPIO(n) (SIFIVE_IRQ_GPIO_BASE+(n)) 19 #define SIFIVE_IRQ_PWM_BASE 40 20 21 #define SIFIVE_NUM_IRQS 64 22 23 #define CLINT_BASE 0x02000000 24 #define PLIC_BASE 0x0c000000 25 #define AON_BASE 0x10000000 26 #define PRCI_BASE 0x10008000 27 #define OTP_BASE 0x10010000 28 #define GPIO_BASE 0x10012000 29 #define UART0_BASE 0x10013000 30 #define QSPI0_BASE 0x10014000 31 #define PWM0_BASE 0x10015000 32 #define UART1_BASE 0x10023000 33 #define QSPI1_BASE 0x10024000 34 #define PWM1_BASE 0x10025000 35 #define QSPI2_BASE 0x10034000 36 #define PWM2_BASE 0x10035000 37 38 #define GPIO_REG_VALUE 0 39 #define GPIO_REG_INPUT_EN 1 40 #define GPIO_REG_OUTPUT_EN 2 41 #define GPIO_REG_PORT 3 42 #define GPIO_REG_IOF_EN 14 43 #define GPIO_REG_IOF_SEL 15 44 45 #define PLIC_HART_IDX(hart) 0 46 47 #define GPIO_AF0 (1U << 16) 48 #define GPIO_AF1 (1U << 17) 49