1 /*
2 * Copyright (c) 2015 Travis Geiselbrecht
3 *
4 * Use of this source code is governed by a MIT-style
5 * license that can be found in the LICENSE file or at
6 * https://opensource.org/licenses/MIT
7 */
8 /*
9 * COPYRIGHT(c) 2015 STMicroelectronics
10 *
11 * Redistribution and use in source and binary forms, with or without modification,
12 * are permitted provided that the following conditions are met:
13 * 1. Redistributions of source code must retain the above copyright notice,
14 * this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright notice,
16 * this list of conditions and the following disclaimer in the documentation
17 * and/or other materials provided with the distribution.
18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 ******************************************************************************
34 */
35
36 #include <lk/err.h>
37 #include <lk/debug.h>
38 #include <lk/trace.h>
39 #include <target.h>
40 #include <lk/compiler.h>
41 #include <dev/gpio.h>
42 #include <platform/stm32.h>
43
44 #define SRAM_OK ((uint8_t)0x00)
45 #define SRAM_ERROR ((uint8_t)0x01)
46
47 /* #define SRAM_MEMORY_WIDTH FMC_NORSRAM_MEM_BUS_WIDTH_8*/
48 #define SRAM_MEMORY_WIDTH FMC_NORSRAM_MEM_BUS_WIDTH_16
49
50 #define SRAM_BURSTACCESS FMC_BURST_ACCESS_MODE_DISABLE
51 //#define SRAM_BURSTACCESS FMC_BURST_ACCESS_MODE_ENABLE
52
53 #define SRAM_WRITEBURST FMC_WRITE_BURST_DISABLE
54 //#define SRAM_WRITEBURST FMC_WRITE_BURST_ENABLE
55
56 #define CONTINUOUSCLOCK_FEATURE FMC_CONTINUOUS_CLOCK_SYNC_ONLY
57 //#define CONTINUOUSCLOCK_FEATURE FMC_CONTINUOUS_CLOCK_SYNC_ASYNC
58
59 /* DMA definitions for SRAM DMA transfer */
60 #define __SRAM_DMAx_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
61 #define __SRAM_DMAx_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
62 #define SRAM_DMAx_CHANNEL DMA_CHANNEL_0
63 #define SRAM_DMAx_STREAM DMA2_Stream4
64 #define SRAM_DMAx_IRQn DMA2_Stream4_IRQn
65 #define SRAM_DMAx_IRQHandler DMA2_Stream4_IRQHandler
66
67 static SRAM_HandleTypeDef sramHandle;
68 static FMC_NORSRAM_TimingTypeDef Timing;
69
70 /**
71 * @brief Initializes SRAM MSP.
72 * @param hsram: SRAM handle
73 * @retval None
74 */
BSP_SRAM_MspInit(SRAM_HandleTypeDef * hsram,void * Params)75 static void BSP_SRAM_MspInit(SRAM_HandleTypeDef *hsram, void *Params) {
76 static DMA_HandleTypeDef dma_handle;
77 GPIO_InitTypeDef gpio_init_structure;
78
79 /* Enable FMC clock */
80 __HAL_RCC_FMC_CLK_ENABLE();
81
82 /* Enable chosen DMAx clock */
83 __SRAM_DMAx_CLK_ENABLE();
84
85 /* Enable GPIOs clock */
86 __HAL_RCC_GPIOD_CLK_ENABLE();
87 __HAL_RCC_GPIOE_CLK_ENABLE();
88 __HAL_RCC_GPIOF_CLK_ENABLE();
89 __HAL_RCC_GPIOG_CLK_ENABLE();
90
91 /* Common GPIO configuration */
92 gpio_init_structure.Mode = GPIO_MODE_AF_PP;
93 gpio_init_structure.Pull = GPIO_PULLUP;
94 gpio_init_structure.Speed = GPIO_SPEED_HIGH;
95 gpio_init_structure.Alternate = GPIO_AF12_FMC;
96
97 /* GPIOD configuration */
98 gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_8 |\
99 GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 |\
100 GPIO_PIN_14 | GPIO_PIN_15;
101 HAL_GPIO_Init(GPIOD, &gpio_init_structure);
102
103 /* GPIOE configuration */
104 gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_3| GPIO_PIN_4 | GPIO_PIN_7 |\
105 GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 |\
106 GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15;
107 HAL_GPIO_Init(GPIOE, &gpio_init_structure);
108
109 /* GPIOF configuration */
110 gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2| GPIO_PIN_3 | GPIO_PIN_4 |\
111 GPIO_PIN_5 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15;
112 HAL_GPIO_Init(GPIOF, &gpio_init_structure);
113
114 /* GPIOG configuration */
115 gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2| GPIO_PIN_3 | GPIO_PIN_4 |\
116 GPIO_PIN_5 | GPIO_PIN_10;
117 HAL_GPIO_Init(GPIOG, &gpio_init_structure);
118
119 /* Configure common DMA parameters */
120 dma_handle.Init.Channel = SRAM_DMAx_CHANNEL;
121 dma_handle.Init.Direction = DMA_MEMORY_TO_MEMORY;
122 dma_handle.Init.PeriphInc = DMA_PINC_ENABLE;
123 dma_handle.Init.MemInc = DMA_MINC_ENABLE;
124 dma_handle.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
125 dma_handle.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
126 dma_handle.Init.Mode = DMA_NORMAL;
127 dma_handle.Init.Priority = DMA_PRIORITY_HIGH;
128 dma_handle.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
129 dma_handle.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
130 dma_handle.Init.MemBurst = DMA_MBURST_SINGLE;
131 dma_handle.Init.PeriphBurst = DMA_PBURST_SINGLE;
132
133 dma_handle.Instance = SRAM_DMAx_STREAM;
134
135 /* Associate the DMA handle */
136 __HAL_LINKDMA(hsram, hdma, dma_handle);
137
138 /* Deinitialize the Stream for new transfer */
139 HAL_DMA_DeInit(&dma_handle);
140
141 /* Configure the DMA Stream */
142 HAL_DMA_Init(&dma_handle);
143
144 /* NVIC configuration for DMA transfer complete interrupt */
145 HAL_NVIC_SetPriority(SRAM_DMAx_IRQn, 5, 0);
146 HAL_NVIC_EnableIRQ(SRAM_DMAx_IRQn);
147 }
148
149 /**
150 * @brief Initializes the SRAM device.
151 * @retval SRAM status
152 */
BSP_SRAM_Init(void)153 uint8_t BSP_SRAM_Init(void) {
154 static uint8_t sram_status = SRAM_ERROR;
155 /* SRAM device configuration */
156 sramHandle.Instance = FMC_NORSRAM_DEVICE;
157 sramHandle.Extended = FMC_NORSRAM_EXTENDED_DEVICE;
158
159 /* SRAM device configuration */
160 /* Timing configuration derived from system clock (up to 216Mhz)
161 for 108Mhz as SRAM clock frequency */
162 Timing.AddressSetupTime = 2;
163 Timing.AddressHoldTime = 1;
164 Timing.DataSetupTime = 2;
165 Timing.BusTurnAroundDuration = 1;
166 Timing.CLKDivision = 2;
167 Timing.DataLatency = 2;
168 Timing.AccessMode = FMC_ACCESS_MODE_A;
169
170 sramHandle.Init.NSBank = FMC_NORSRAM_BANK3;
171 sramHandle.Init.DataAddressMux = FMC_DATA_ADDRESS_MUX_DISABLE;
172 sramHandle.Init.MemoryType = FMC_MEMORY_TYPE_SRAM;
173 sramHandle.Init.MemoryDataWidth = SRAM_MEMORY_WIDTH;
174 sramHandle.Init.BurstAccessMode = SRAM_BURSTACCESS;
175 sramHandle.Init.WaitSignalPolarity = FMC_WAIT_SIGNAL_POLARITY_LOW;
176 sramHandle.Init.WaitSignalActive = FMC_WAIT_TIMING_BEFORE_WS;
177 sramHandle.Init.WriteOperation = FMC_WRITE_OPERATION_ENABLE;
178 sramHandle.Init.WaitSignal = FMC_WAIT_SIGNAL_DISABLE;
179 sramHandle.Init.ExtendedMode = FMC_EXTENDED_MODE_DISABLE;
180 sramHandle.Init.AsynchronousWait = FMC_ASYNCHRONOUS_WAIT_DISABLE;
181 sramHandle.Init.WriteBurst = SRAM_WRITEBURST;
182 sramHandle.Init.ContinuousClock = CONTINUOUSCLOCK_FEATURE;
183
184 /* SRAM controller initialization */
185 BSP_SRAM_MspInit(&sramHandle, NULL); /* __weak function can be rewritten by the application */
186 if (HAL_SRAM_Init(&sramHandle, &Timing, &Timing) != HAL_OK) {
187 sram_status = SRAM_ERROR;
188 } else {
189 sram_status = SRAM_OK;
190 }
191 return sram_status;
192 }
193
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