1# Setup compiler for the core module 2ifeq ($(CFG_ARM64_core),y) 3arch-bits-core := 64 4else 5arch-bits-core := 32 6endif 7CROSS_COMPILE_core := $(CROSS_COMPILE$(arch-bits-core)) 8COMPILER_core := $(COMPILER) 9include mk/$(COMPILER_core).mk 10 11# Defines the cc-option macro using the compiler set for the core module 12include mk/cc-option.mk 13 14# Size of emulated TrustZone protected SRAM, 448 kB. 15# Only applicable when paging is enabled. 16CFG_CORE_TZSRAM_EMUL_SIZE ?= 458752 17 18ifneq ($(CFG_LPAE_ADDR_SPACE_SIZE),) 19$(warning Error: CFG_LPAE_ADDR_SPACE_SIZE is not supported any longer) 20$(error Error: Please use CFG_LPAE_ADDR_SPACE_BITS instead) 21endif 22 23CFG_LPAE_ADDR_SPACE_BITS ?= 32 24 25CFG_MMAP_REGIONS ?= 13 26CFG_RESERVED_VASPACE_SIZE ?= (1024 * 1024 * 10) 27 28ifeq ($(CFG_ARM64_core),y) 29ifeq ($(CFG_ARM32_core),y) 30$(error CFG_ARM64_core and CFG_ARM32_core cannot be both 'y') 31endif 32CFG_KERN_LINKER_FORMAT ?= elf64-littleaarch64 33CFG_KERN_LINKER_ARCH ?= aarch64 34# TCR_EL1.IPS needs to be initialized according to the largest physical 35# address that we need to map. 36# Physical address size 37# 32 bits, 4GB. 38# 36 bits, 64GB. 39# (etc.) 40CFG_CORE_ARM64_PA_BITS ?= 32 41$(call force,CFG_WITH_LPAE,y) 42else 43$(call force,CFG_ARM32_core,y) 44CFG_KERN_LINKER_FORMAT ?= elf32-littlearm 45CFG_KERN_LINKER_ARCH ?= arm 46endif 47 48ifeq ($(CFG_TA_FLOAT_SUPPORT),y) 49# Use hard-float for floating point support in user TAs instead of 50# soft-float 51CFG_WITH_VFP ?= y 52ifeq ($(CFG_ARM64_core),y) 53# AArch64 has no fallback to soft-float 54$(call force,CFG_WITH_VFP,y) 55endif 56ifeq ($(CFG_WITH_VFP),y) 57arm64-platform-hard-float-enabled := y 58ifneq ($(CFG_TA_ARM32_NO_HARD_FLOAT_SUPPORT),y) 59arm32-platform-hard-float-enabled := y 60endif 61endif 62endif 63 64# Adds protection against CVE-2017-5715 also know as Spectre 65# (https://spectreattack.com) 66# See also https://developer.arm.com/-/media/Files/pdf/Cache_Speculation_Side-channels.pdf 67# Variant 2 68CFG_CORE_WORKAROUND_SPECTRE_BP ?= y 69# Same as CFG_CORE_WORKAROUND_SPECTRE_BP but targeting exceptions from 70# secure EL0 instead of non-secure world, including mitigation for 71# CVE-2022-23960. 72CFG_CORE_WORKAROUND_SPECTRE_BP_SEC ?= $(CFG_CORE_WORKAROUND_SPECTRE_BP) 73 74# Adds protection against a tool like Cachegrab 75# (https://github.com/nccgroup/cachegrab), which uses non-secure interrupts 76# to prime and later analyze the L1D, L1I and BTB caches to gain 77# information from secure world execution. 78CFG_CORE_WORKAROUND_NSITR_CACHE_PRIME ?= y 79ifeq ($(CFG_CORE_WORKAROUND_NSITR_CACHE_PRIME),y) 80$(call force,CFG_CORE_WORKAROUND_SPECTRE_BP,y,Required by CFG_CORE_WORKAROUND_NSITR_CACHE_PRIME) 81endif 82 83# Adds workarounds against if ARM core is configured with Non-maskable FIQ 84# (NMFI) support. This is indicated by SCTLR.NMFI being true. NMFI cannot be 85# disabled by software and as it affects atomic context end result will be 86# prohibiting FIQ signal usage in OP-TEE and applying some tweaks to make sure 87# FIQ is enabled in critical places. 88CFG_CORE_WORKAROUND_ARM_NMFI ?= n 89 90CFG_CORE_RWDATA_NOEXEC ?= y 91CFG_CORE_RODATA_NOEXEC ?= n 92ifeq ($(CFG_CORE_RODATA_NOEXEC),y) 93$(call force,CFG_CORE_RWDATA_NOEXEC,y) 94endif 95# 'y' to set the Alignment Check Enable bit in SCTLR/SCTLR_EL1, 'n' to clear it 96CFG_SCTLR_ALIGNMENT_CHECK ?= n 97 98ifeq ($(CFG_CORE_LARGE_PHYS_ADDR),y) 99$(call force,CFG_WITH_LPAE,y) 100endif 101 102# SPMC configuration "S-EL1 SPMC" where SPM Core is implemented at S-EL1, 103# that is, OP-TEE. 104ifeq ($(CFG_CORE_SEL1_SPMC),y) 105$(call force,CFG_CORE_FFA,y) 106$(call force,CFG_CORE_SEL2_SPMC,n) 107$(call force,CFG_CORE_EL3_SPMC,n) 108endif 109# SPMC configuration "S-EL2 SPMC" where SPM Core is implemented at S-EL2, 110# that is, the hypervisor sandboxing OP-TEE 111ifeq ($(CFG_CORE_SEL2_SPMC),y) 112$(call force,CFG_CORE_FFA,y) 113$(call force,CFG_CORE_SEL1_SPMC,n) 114$(call force,CFG_CORE_EL3_SPMC,n) 115endif 116# SPMC configuration "EL3 SPMC" where SPM Core is implemented at EL3, that 117# is, in TF-A 118ifeq ($(CFG_CORE_EL3_SPMC),y) 119$(call force,CFG_CORE_FFA,y) 120$(call force,CFG_CORE_SEL2_SPMC,n) 121$(call force,CFG_CORE_SEL1_SPMC,n) 122endif 123 124ifeq ($(CFG_CORE_FFA)-$(CFG_WITH_PAGER),y-y) 125$(error CFG_CORE_FFA and CFG_WITH_PAGER are not compatible) 126endif 127 128# Unmaps all kernel mode code except the code needed to take exceptions 129# from user space and restore kernel mode mapping again. This gives more 130# strict control over what is accessible while in user mode. 131# Addresses CVE-2017-5715 (aka Meltdown) known to affect Arm Cortex-A75 132CFG_CORE_UNMAP_CORE_AT_EL0 ?= y 133 134# Initialize PMCR.DP to 1 to prohibit cycle counting in secure state, and 135# save/restore PMCR during world switch. 136CFG_SM_NO_CYCLE_COUNTING ?= y 137 138 139# CFG_CORE_ASYNC_NOTIF_GIC_INTID is defined by the platform to some free 140# interrupt. Setting it to a non-zero number enables support for using an 141# Arm-GIC to notify normal world. This config variable should use a value 142# larger the 32 to make it of the type SPI. 143# Note that asynchronous notifactions must be enabled with 144# CFG_CORE_ASYNC_NOTIF=y for this variable to be used. 145CFG_CORE_ASYNC_NOTIF_GIC_INTID ?= 0 146 147ifeq ($(CFG_ARM32_core),y) 148# Configration directive related to ARMv7 optee boot arguments. 149# CFG_PAGEABLE_ADDR: if defined, forces pageable data physical address. 150# CFG_NS_ENTRY_ADDR: if defined, forces NS World physical entry address. 151# CFG_DT_ADDR: if defined, forces Device Tree data physical address. 152endif 153 154# CFG_MAX_CACHE_LINE_SHIFT is used to define platform specific maximum cache 155# line size in address lines. This must cover all inner and outer cache levels. 156# When data is aligned with this and cache operations are performed then those 157# only affect correct data. 158# 159# Default value (6 lines or 64 bytes) should cover most architectures, override 160# this in platform config if different. 161CFG_MAX_CACHE_LINE_SHIFT ?= 6 162 163core-platform-cppflags += -I$(arch-dir)/include 164core-platform-subdirs += \ 165 $(addprefix $(arch-dir)/, kernel crypto mm tee) $(platform-dir) 166 167ifneq ($(CFG_WITH_ARM_TRUSTED_FW),y) 168core-platform-subdirs += $(arch-dir)/sm 169endif 170 171arm64-platform-cppflags += -DARM64=1 -D__LP64__=1 172arm32-platform-cppflags += -DARM32=1 -D__ILP32__=1 173 174platform-cflags-generic ?= -ffunction-sections -fdata-sections -pipe 175platform-aflags-generic ?= -pipe 176 177arm32-platform-aflags += -marm 178 179arm32-platform-cflags-no-hard-float ?= -mfloat-abi=soft 180arm32-platform-cflags-hard-float ?= -mfloat-abi=hard -funsafe-math-optimizations 181arm32-platform-cflags-generic-thumb ?= -mthumb \ 182 -fno-short-enums -fno-common -mno-unaligned-access 183arm32-platform-cflags-generic-arm ?= -marm -fno-omit-frame-pointer -mapcs \ 184 -fno-short-enums -fno-common -mno-unaligned-access 185arm32-platform-aflags-no-hard-float ?= 186 187arm64-platform-cflags-no-hard-float ?= -mgeneral-regs-only 188arm64-platform-cflags-hard-float ?= 189arm64-platform-cflags-generic := -mstrict-align $(call cc-option,-mno-outline-atomics,) 190 191ifeq ($(CFG_MEMTAG),y) 192arm64-platform-cflags += -march=armv8.5-a+memtag 193arm64-platform-aflags += -march=armv8.5-a+memtag 194endif 195 196platform-cflags-optimization ?= -O$(CFG_CC_OPT_LEVEL) 197 198ifeq ($(CFG_DEBUG_INFO),y) 199platform-cflags-debug-info ?= -g3 200platform-aflags-debug-info ?= -g 201endif 202 203core-platform-cflags += $(platform-cflags-optimization) 204core-platform-cflags += $(platform-cflags-generic) 205core-platform-cflags += $(platform-cflags-debug-info) 206 207core-platform-aflags += $(platform-aflags-generic) 208core-platform-aflags += $(platform-aflags-debug-info) 209 210ifeq ($(CFG_CORE_ASLR),y) 211core-platform-cflags += -fpie 212endif 213 214ifeq ($(CFG_CORE_PAUTH),y) 215bp-core-opt := $(call cc-option,-mbranch-protection=pac-ret+leaf) 216endif 217 218ifeq ($(CFG_CORE_BTI),y) 219bp-core-opt := $(call cc-option,-mbranch-protection=bti) 220endif 221 222ifeq (y-y,$(CFG_CORE_PAUTH)-$(CFG_CORE_BTI)) 223bp-core-opt := $(call cc-option,-mbranch-protection=pac-ret+leaf+bti) 224endif 225 226ifeq (y,$(filter $(CFG_CORE_BTI) $(CFG_CORE_PAUTH),y)) 227ifeq (,$(bp-core-opt)) 228$(error -mbranch-protection not supported) 229endif 230core-platform-cflags += $(bp-core-opt) 231endif 232 233ifeq ($(CFG_ARM64_core),y) 234core-platform-cppflags += $(arm64-platform-cppflags) 235core-platform-cflags += $(arm64-platform-cflags) 236core-platform-cflags += $(arm64-platform-cflags-generic) 237core-platform-cflags += $(arm64-platform-cflags-no-hard-float) 238core-platform-aflags += $(arm64-platform-aflags) 239else 240core-platform-cppflags += $(arm32-platform-cppflags) 241core-platform-cflags += $(arm32-platform-cflags) 242core-platform-cflags += $(arm32-platform-cflags-no-hard-float) 243ifeq ($(CFG_UNWIND),y) 244core-platform-cflags += -funwind-tables 245endif 246ifeq ($(CFG_SYSCALL_FTRACE),y) 247core-platform-cflags += $(arm32-platform-cflags-generic-arm) 248else 249core-platform-cflags += $(arm32-platform-cflags-generic-thumb) 250endif 251core-platform-aflags += $(core_arm32-platform-aflags) 252core-platform-aflags += $(arm32-platform-aflags) 253endif 254 255# Provide default supported-ta-targets if not set by the platform config 256ifeq (,$(supported-ta-targets)) 257supported-ta-targets = ta_arm32 258ifeq ($(CFG_ARM64_core),y) 259supported-ta-targets += ta_arm64 260endif 261endif 262 263ta-targets := $(if $(CFG_USER_TA_TARGETS),$(filter $(supported-ta-targets),$(CFG_USER_TA_TARGETS)),$(supported-ta-targets)) 264unsup-targets := $(filter-out $(ta-targets),$(CFG_USER_TA_TARGETS)) 265ifneq (,$(unsup-targets)) 266$(error CFG_USER_TA_TARGETS contains unsupported value(s): $(unsup-targets). Valid values: $(supported-ta-targets)) 267endif 268 269ifneq ($(filter ta_arm32,$(ta-targets)),) 270# Variables for ta-target/sm "ta_arm32" 271CFG_ARM32_ta_arm32 := y 272arch-bits-ta_arm32 := 32 273ta_arm32-platform-cppflags += $(arm32-platform-cppflags) 274ta_arm32-platform-cflags += $(arm32-platform-cflags) 275ta_arm32-platform-cflags += $(platform-cflags-optimization) 276ta_arm32-platform-cflags += $(platform-cflags-debug-info) 277ta_arm32-platform-cflags += -fpic 278 279# Thumb mode doesn't support function graph tracing due to missing 280# frame pointer support required to trace function call chain. So 281# rather compile in ARM mode if function tracing is enabled. 282ifeq ($(CFG_FTRACE_SUPPORT),y) 283ta_arm32-platform-cflags += $(arm32-platform-cflags-generic-arm) 284else 285ta_arm32-platform-cflags += $(arm32-platform-cflags-generic-thumb) 286endif 287 288ifeq ($(arm32-platform-hard-float-enabled),y) 289ta_arm32-platform-cflags += $(arm32-platform-cflags-hard-float) 290else 291ta_arm32-platform-cflags += $(arm32-platform-cflags-no-hard-float) 292endif 293ifeq ($(CFG_UNWIND),y) 294ta_arm32-platform-cflags += -funwind-tables 295endif 296ta_arm32-platform-aflags += $(platform-aflags-generic) 297ta_arm32-platform-aflags += $(platform-aflags-debug-info) 298ta_arm32-platform-aflags += $(arm32-platform-aflags) 299 300ta_arm32-platform-cxxflags += -fpic 301ta_arm32-platform-cxxflags += $(arm32-platform-cxxflags) 302ta_arm32-platform-cxxflags += $(platform-cflags-optimization) 303ta_arm32-platform-cxxflags += $(platform-cflags-debug-info) 304 305ifeq ($(arm32-platform-hard-float-enabled),y) 306ta_arm32-platform-cxxflags += $(arm32-platform-cflags-hard-float) 307else 308ta_arm32-platform-cxxflags += $(arm32-platform-cflags-no-hard-float) 309endif 310 311ta-mk-file-export-vars-ta_arm32 += CFG_ARM32_ta_arm32 312ta-mk-file-export-vars-ta_arm32 += ta_arm32-platform-cppflags 313ta-mk-file-export-vars-ta_arm32 += ta_arm32-platform-cflags 314ta-mk-file-export-vars-ta_arm32 += ta_arm32-platform-aflags 315ta-mk-file-export-vars-ta_arm32 += ta_arm32-platform-cxxflags 316 317ta-mk-file-export-add-ta_arm32 += CROSS_COMPILE ?= arm-linux-gnueabihf-_nl_ 318ta-mk-file-export-add-ta_arm32 += CROSS_COMPILE32 ?= $$(CROSS_COMPILE)_nl_ 319ta-mk-file-export-add-ta_arm32 += CROSS_COMPILE_ta_arm32 ?= $$(CROSS_COMPILE32)_nl_ 320ta-mk-file-export-add-ta_arm32 += COMPILER ?= gcc_nl_ 321ta-mk-file-export-add-ta_arm32 += COMPILER_ta_arm32 ?= $$(COMPILER)_nl_ 322ta-mk-file-export-add-ta_arm32 += PYTHON3 ?= python3_nl_ 323endif 324 325ifneq ($(filter ta_arm64,$(ta-targets)),) 326# Variables for ta-target/sm "ta_arm64" 327CFG_ARM64_ta_arm64 := y 328arch-bits-ta_arm64 := 64 329ta_arm64-platform-cppflags += $(arm64-platform-cppflags) 330ta_arm64-platform-cflags += $(arm64-platform-cflags) 331ta_arm64-platform-cflags += $(platform-cflags-optimization) 332ta_arm64-platform-cflags += $(platform-cflags-debug-info) 333ta_arm64-platform-cflags += -fpic 334ta_arm64-platform-cflags += $(arm64-platform-cflags-generic) 335ifeq ($(arm64-platform-hard-float-enabled),y) 336ta_arm64-platform-cflags += $(arm64-platform-cflags-hard-float) 337else 338ta_arm64-platform-cflags += $(arm64-platform-cflags-no-hard-float) 339endif 340ta_arm64-platform-aflags += $(platform-aflags-generic) 341ta_arm64-platform-aflags += $(platform-aflags-debug-info) 342ta_arm64-platform-aflags += $(arm64-platform-aflags) 343 344ta_arm64-platform-cxxflags += -fpic 345ta_arm64-platform-cxxflags += $(platform-cflags-optimization) 346ta_arm64-platform-cxxflags += $(platform-cflags-debug-info) 347 348ifeq ($(CFG_TA_PAUTH),y) 349bp-ta-opt := $(call cc-option,-mbranch-protection=pac-ret+leaf) 350endif 351 352ifeq ($(CFG_TA_BTI),y) 353bp-ta-opt := $(call cc-option,-mbranch-protection=bti) 354endif 355 356ifeq (y-y,$(CFG_TA_PAUTH)-$(CFG_TA_BTI)) 357bp-ta-opt := $(call cc-option,-mbranch-protection=pac-ret+leaf+bti) 358endif 359 360ifeq (y,$(filter $(CFG_TA_BTI) $(CFG_TA_PAUTH),y)) 361ifeq (,$(bp-ta-opt)) 362$(error -mbranch-protection not supported) 363endif 364ta_arm64-platform-cflags += $(bp-ta-opt) 365endif 366 367ta-mk-file-export-vars-ta_arm64 += CFG_ARM64_ta_arm64 368ta-mk-file-export-vars-ta_arm64 += ta_arm64-platform-cppflags 369ta-mk-file-export-vars-ta_arm64 += ta_arm64-platform-cflags 370ta-mk-file-export-vars-ta_arm64 += ta_arm64-platform-aflags 371ta-mk-file-export-vars-ta_arm64 += ta_arm64-platform-cxxflags 372 373ta-mk-file-export-add-ta_arm64 += CROSS_COMPILE64 ?= $$(CROSS_COMPILE)_nl_ 374ta-mk-file-export-add-ta_arm64 += CROSS_COMPILE_ta_arm64 ?= $$(CROSS_COMPILE64)_nl_ 375ta-mk-file-export-add-ta_arm64 += COMPILER ?= gcc_nl_ 376ta-mk-file-export-add-ta_arm64 += COMPILER_ta_arm64 ?= $$(COMPILER)_nl_ 377ta-mk-file-export-add-ta_arm64 += PYTHON3 ?= python3_nl_ 378endif 379 380# Set cross compiler prefix for each TA target 381$(foreach sm, $(ta-targets), $(eval CROSS_COMPILE_$(sm) ?= $(CROSS_COMPILE$(arch-bits-$(sm))))) 382 383arm32-sysreg-txt = core/arch/arm/kernel/arm32_sysreg.txt 384arm32-sysregs-$(arm32-sysreg-txt)-h := arm32_sysreg.h 385arm32-sysregs-$(arm32-sysreg-txt)-s := arm32_sysreg.S 386arm32-sysregs += $(arm32-sysreg-txt) 387 388ifeq ($(CFG_ARM_GICV3),y) 389arm32-gicv3-sysreg-txt = core/arch/arm/kernel/arm32_gicv3_sysreg.txt 390arm32-sysregs-$(arm32-gicv3-sysreg-txt)-h := arm32_gicv3_sysreg.h 391arm32-sysregs-$(arm32-gicv3-sysreg-txt)-s := arm32_gicv3_sysreg.S 392arm32-sysregs += $(arm32-gicv3-sysreg-txt) 393endif 394 395arm32-sysregs-out := $(out-dir)/$(sm)/include/generated 396 397define process-arm32-sysreg 398FORCE-GENSRC$(sm): $$(arm32-sysregs-out)/$$(arm32-sysregs-$(1)-h) 399cleanfiles := $$(cleanfiles) $$(arm32-sysregs-out)/$$(arm32-sysregs-$(1)-h) 400 401$$(arm32-sysregs-out)/$$(arm32-sysregs-$(1)-h): $(1) scripts/arm32_sysreg.py 402 @$(cmd-echo-silent) ' GEN $$@' 403 $(q)mkdir -p $$(dir $$@) 404 $(q)scripts/arm32_sysreg.py --guard __$$(arm32-sysregs-$(1)-h) \ 405 < $$< > $$@ 406 407FORCE-GENSRC$(sm): $$(arm32-sysregs-out)/$$(arm32-sysregs-$(1)-s) 408cleanfiles := $$(cleanfiles) $$(arm32-sysregs-out)/$$(arm32-sysregs-$(1)-s) 409 410$$(arm32-sysregs-out)/$$(arm32-sysregs-$(1)-s): $(1) scripts/arm32_sysreg.py 411 @$(cmd-echo-silent) ' GEN $$@' 412 $(q)mkdir -p $$(dir $$@) 413 $(q)scripts/arm32_sysreg.py --s_file < $$< > $$@ 414endef #process-arm32-sysreg 415 416$(foreach sr, $(arm32-sysregs), $(eval $(call process-arm32-sysreg,$(sr)))) 417